Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 Waldorf GMBH
7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
8 * Copyright (C) 1996 Paul M. Antoine
9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 */
11#ifndef _ASM_PROCESSOR_H
12#define _ASM_PROCESSOR_H
13
14#include <linux/cpumask.h>
15#include <linux/threads.h>
16
17#include <asm/cachectl.h>
18#include <asm/cpu.h>
19#include <asm/cpu-info.h>
20#include <asm/mipsregs.h>
21#include <asm/prefetch.h>
22
23/*
24 * Return current * instruction pointer ("program counter").
25 */
26#define current_text_addr() ({ __label__ _l; _l: &&_l;})
27
28/*
29 * System setup and hardware flags..
30 */
31
32extern unsigned int vced_count, vcei_count;
33
34/*
35 * MIPS does have an arch_pick_mmap_layout()
36 */
37#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
38
39/*
40 * A special page (the vdso) is mapped into all processes at the very
41 * top of the virtual memory space.
42 */
43#define SPECIAL_PAGES_SIZE PAGE_SIZE
44
45#ifdef CONFIG_32BIT
46#ifdef CONFIG_KVM_GUEST
47/* User space process size is limited to 1GB in KVM Guest Mode */
48#define TASK_SIZE 0x3fff8000UL
49#else
50/*
51 * User space process size: 2GB. This is hardcoded into a few places,
52 * so don't change it unless you know what you are doing.
53 */
54#define TASK_SIZE 0x7fff8000UL
55#endif
56
57#ifdef __KERNEL__
58#define STACK_TOP_MAX TASK_SIZE
59#endif
60
61#define TASK_IS_32BIT_ADDR 1
62
63#endif
64
65#ifdef CONFIG_64BIT
66/*
67 * User space process size: 1TB. This is hardcoded into a few places,
68 * so don't change it unless you know what you are doing. TASK_SIZE
69 * is limited to 1TB by the R4000 architecture; R10000 and better can
70 * support 16TB; the architectural reserve for future expansion is
71 * 8192EB ...
72 */
73#define TASK_SIZE32 0x7fff8000UL
74#define TASK_SIZE64 0x10000000000UL
75#define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
76
77#ifdef __KERNEL__
78#define STACK_TOP_MAX TASK_SIZE64
79#endif
80
81
82#define TASK_SIZE_OF(tsk) \
83 (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
84
85#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
86
87#endif
88
89#define STACK_TOP ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE)
90
91/*
92 * This decides where the kernel will search for a free chunk of vm
93 * space during mmap's.
94 */
95#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
96
97
98#define NUM_FPU_REGS 32
99
100#ifdef CONFIG_CPU_HAS_MSA
101# define FPU_REG_WIDTH 128
102#else
103# define FPU_REG_WIDTH 64
104#endif
105
106union fpureg {
107 __u32 val32[FPU_REG_WIDTH / 32];
108 __u64 val64[FPU_REG_WIDTH / 64];
109};
110
111#ifdef CONFIG_CPU_LITTLE_ENDIAN
112# define FPR_IDX(width, idx) (idx)
113#else
114# define FPR_IDX(width, idx) ((FPU_REG_WIDTH / (width)) - 1 - (idx))
115#endif
116
117#define BUILD_FPR_ACCESS(width) \
118static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx) \
119{ \
120 return fpr->val##width[FPR_IDX(width, idx)]; \
121} \
122 \
123static inline void set_fpr##width(union fpureg *fpr, unsigned idx, \
124 u##width val) \
125{ \
126 fpr->val##width[FPR_IDX(width, idx)] = val; \
127}
128
129BUILD_FPR_ACCESS(32)
130BUILD_FPR_ACCESS(64)
131
132/*
133 * It would be nice to add some more fields for emulator statistics,
134 * the additional information is private to the FPU emulator for now.
135 * See arch/mips/include/asm/fpu_emulator.h.
136 */
137
138struct mips_fpu_struct {
139 union fpureg fpr[NUM_FPU_REGS];
140 unsigned int fcr31;
141 unsigned int msacsr;
142};
143
144#define NUM_DSP_REGS 6
145
146typedef __u32 dspreg_t;
147
148struct mips_dsp_state {
149 dspreg_t dspr[NUM_DSP_REGS];
150 unsigned int dspcontrol;
151};
152
153#define INIT_CPUMASK { \
154 {0,} \
155}
156
157struct mips3264_watch_reg_state {
158 /* The width of watchlo is 32 in a 32 bit kernel and 64 in a
159 64 bit kernel. We use unsigned long as it has the same
160 property. */
161 unsigned long watchlo[NUM_WATCH_REGS];
162 /* Only the mask and IRW bits from watchhi. */
163 u16 watchhi[NUM_WATCH_REGS];
164};
165
166union mips_watch_reg_state {
167 struct mips3264_watch_reg_state mips3264;
168};
169
170#if defined(CONFIG_CPU_CAVIUM_OCTEON)
171
172struct octeon_cop2_state {
173 /* DMFC2 rt, 0x0201 */
174 unsigned long cop2_crc_iv;
175 /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
176 unsigned long cop2_crc_length;
177 /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
178 unsigned long cop2_crc_poly;
179 /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
180 unsigned long cop2_llm_dat[2];
181 /* DMFC2 rt, 0x0084 */
182 unsigned long cop2_3des_iv;
183 /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
184 unsigned long cop2_3des_key[3];
185 /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
186 unsigned long cop2_3des_result;
187 /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
188 unsigned long cop2_aes_inp0;
189 /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
190 unsigned long cop2_aes_iv[2];
191 /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
192 * rt, 0x0107 */
193 unsigned long cop2_aes_key[4];
194 /* DMFC2 rt, 0x0110 */
195 unsigned long cop2_aes_keylen;
196 /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
197 unsigned long cop2_aes_result[2];
198 /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
199 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
200 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
201 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
202 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
203 unsigned long cop2_hsh_datw[15];
204 /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
205 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
206 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
207 unsigned long cop2_hsh_ivw[8];
208 /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
209 unsigned long cop2_gfm_mult[2];
210 /* DMFC2 rt, 0x025E - Pass2 */
211 unsigned long cop2_gfm_poly;
212 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
213 unsigned long cop2_gfm_result[2];
214};
215#define COP2_INIT \
216 .cp2 = {0,},
217
218struct octeon_cvmseg_state {
219 unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
220 [cpu_dcache_line_size() / sizeof(unsigned long)];
221};
222
223#elif defined(CONFIG_CPU_XLP)
224struct nlm_cop2_state {
225 u64 rx[4];
226 u64 tx[4];
227 u32 tx_msg_status;
228 u32 rx_msg_status;
229};
230
231#define COP2_INIT \
232 .cp2 = {{0}, {0}, 0, 0},
233#else
234#define COP2_INIT
235#endif
236
237typedef struct {
238 unsigned long seg;
239} mm_segment_t;
240
241#ifdef CONFIG_CPU_HAS_MSA
242# define ARCH_MIN_TASKALIGN 16
243# define FPU_ALIGN __aligned(16)
244#else
245# define ARCH_MIN_TASKALIGN 8
246# define FPU_ALIGN
247#endif
248
249struct mips_abi;
250
251/*
252 * If you change thread_struct remember to change the #defines below too!
253 */
254struct thread_struct {
255 /* Saved main processor registers. */
256 unsigned long reg16;
257 unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
258 unsigned long reg29, reg30, reg31;
259
260 /* Saved cp0 stuff. */
261 unsigned long cp0_status;
262
263 /* Saved fpu/fpu emulator stuff. */
264 struct mips_fpu_struct fpu FPU_ALIGN;
265#ifdef CONFIG_MIPS_MT_FPAFF
266 /* Emulated instruction count */
267 unsigned long emulated_fp;
268 /* Saved per-thread scheduler affinity mask */
269 cpumask_t user_cpus_allowed;
270#endif /* CONFIG_MIPS_MT_FPAFF */
271
272 /* Saved state of the DSP ASE, if available. */
273 struct mips_dsp_state dsp;
274
275 /* Saved watch register state, if available. */
276 union mips_watch_reg_state watch;
277
278 /* Other stuff associated with the thread. */
279 unsigned long cp0_badvaddr; /* Last user fault */
280 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
281 unsigned long error_code;
282#ifdef CONFIG_CPU_CAVIUM_OCTEON
283 struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
284 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
285#endif
286#ifdef CONFIG_CPU_XLP
287 struct nlm_cop2_state cp2;
288#endif
289 struct mips_abi *abi;
290};
291
292#ifdef CONFIG_MIPS_MT_FPAFF
293#define FPAFF_INIT \
294 .emulated_fp = 0, \
295 .user_cpus_allowed = INIT_CPUMASK,
296#else
297#define FPAFF_INIT
298#endif /* CONFIG_MIPS_MT_FPAFF */
299
300#define INIT_THREAD { \
301 /* \
302 * Saved main processor registers \
303 */ \
304 .reg16 = 0, \
305 .reg17 = 0, \
306 .reg18 = 0, \
307 .reg19 = 0, \
308 .reg20 = 0, \
309 .reg21 = 0, \
310 .reg22 = 0, \
311 .reg23 = 0, \
312 .reg29 = 0, \
313 .reg30 = 0, \
314 .reg31 = 0, \
315 /* \
316 * Saved cp0 stuff \
317 */ \
318 .cp0_status = 0, \
319 /* \
320 * Saved FPU/FPU emulator stuff \
321 */ \
322 .fpu = { \
323 .fpr = {{{0,},},}, \
324 .fcr31 = 0, \
325 .msacsr = 0, \
326 }, \
327 /* \
328 * FPU affinity state (null if not FPAFF) \
329 */ \
330 FPAFF_INIT \
331 /* \
332 * Saved DSP stuff \
333 */ \
334 .dsp = { \
335 .dspr = {0, }, \
336 .dspcontrol = 0, \
337 }, \
338 /* \
339 * saved watch register stuff \
340 */ \
341 .watch = {{{0,},},}, \
342 /* \
343 * Other stuff associated with the process \
344 */ \
345 .cp0_badvaddr = 0, \
346 .cp0_baduaddr = 0, \
347 .error_code = 0, \
348 /* \
349 * Platform specific cop2 registers(null if no COP2) \
350 */ \
351 COP2_INIT \
352}
353
354struct task_struct;
355
356/* Free all resources held by a thread. */
357#define release_thread(thread) do { } while(0)
358
359extern unsigned long thread_saved_pc(struct task_struct *tsk);
360
361/*
362 * Do necessary setup to start up a newly executed thread.
363 */
364extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
365
366unsigned long get_wchan(struct task_struct *p);
367
368#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
369 THREAD_SIZE - 32 - sizeof(struct pt_regs))
370#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
371#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
372#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
373#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
374
375#define cpu_relax() barrier()
376#define cpu_relax_lowlatency() cpu_relax()
377
378/*
379 * Return_address is a replacement for __builtin_return_address(count)
380 * which on certain architectures cannot reasonably be implemented in GCC
381 * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
382 * Note that __builtin_return_address(x>=1) is forbidden because GCC
383 * aborts compilation on some CPUs. It's simply not possible to unwind
384 * some CPU's stackframes.
385 *
386 * __builtin_return_address works only for non-leaf functions. We avoid the
387 * overhead of a function call by forcing the compiler to save the return
388 * address register on the stack.
389 */
390#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
391
392#ifdef CONFIG_CPU_HAS_PREFETCH
393
394#define ARCH_HAS_PREFETCH
395#define prefetch(x) __builtin_prefetch((x), 0, 1)
396
397#define ARCH_HAS_PREFETCHW
398#define prefetchw(x) __builtin_prefetch((x), 1, 1)
399
400/*
401 * See Documentation/scheduler/sched-arch.txt; prevents deadlock on SMP
402 * systems.
403 */
404#define __ARCH_WANT_UNLOCKED_CTXSW
405
406#endif
407
408#endif /* _ASM_PROCESSOR_H */