Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
38
39#if defined(__LITTLE_ENDIAN)
40#define MLX5_SET_HOST_ENDIANNESS 0
41#elif defined(__BIG_ENDIAN)
42#define MLX5_SET_HOST_ENDIANNESS 0x80
43#else
44#error Host endianness not defined
45#endif
46
47enum {
48 MLX5_MAX_COMMANDS = 32,
49 MLX5_CMD_DATA_BLOCK_SIZE = 512,
50 MLX5_PCI_CMD_XPORT = 7,
51 MLX5_MKEY_BSF_OCTO_SIZE = 4,
52 MLX5_MAX_PSVS = 4,
53};
54
55enum {
56 MLX5_EXTENDED_UD_AV = 0x80000000,
57};
58
59enum {
60 MLX5_CQ_STATE_ARMED = 9,
61 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
62 MLX5_CQ_STATE_FIRED = 0xa,
63};
64
65enum {
66 MLX5_STAT_RATE_OFFSET = 5,
67};
68
69enum {
70 MLX5_INLINE_SEG = 0x80000000,
71};
72
73enum {
74 MLX5_PERM_LOCAL_READ = 1 << 2,
75 MLX5_PERM_LOCAL_WRITE = 1 << 3,
76 MLX5_PERM_REMOTE_READ = 1 << 4,
77 MLX5_PERM_REMOTE_WRITE = 1 << 5,
78 MLX5_PERM_ATOMIC = 1 << 6,
79 MLX5_PERM_UMR_EN = 1 << 7,
80};
81
82enum {
83 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
84 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
85 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
86 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
87 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
88};
89
90enum {
91 MLX5_ACCESS_MODE_PA = 0,
92 MLX5_ACCESS_MODE_MTT = 1,
93 MLX5_ACCESS_MODE_KLM = 2
94};
95
96enum {
97 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
98 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
99 MLX5_MKEY_BSF_EN = 1 << 30,
100 MLX5_MKEY_LEN64 = 1 << 31,
101};
102
103enum {
104 MLX5_EN_RD = (u64)1,
105 MLX5_EN_WR = (u64)2
106};
107
108enum {
109 MLX5_BF_REGS_PER_PAGE = 4,
110 MLX5_MAX_UAR_PAGES = 1 << 8,
111 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
112 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
113};
114
115enum {
116 MLX5_MKEY_MASK_LEN = 1ull << 0,
117 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
118 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
119 MLX5_MKEY_MASK_PD = 1ull << 7,
120 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
121 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
122 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
123 MLX5_MKEY_MASK_KEY = 1ull << 13,
124 MLX5_MKEY_MASK_QPN = 1ull << 14,
125 MLX5_MKEY_MASK_LR = 1ull << 17,
126 MLX5_MKEY_MASK_LW = 1ull << 18,
127 MLX5_MKEY_MASK_RR = 1ull << 19,
128 MLX5_MKEY_MASK_RW = 1ull << 20,
129 MLX5_MKEY_MASK_A = 1ull << 21,
130 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
131 MLX5_MKEY_MASK_FREE = 1ull << 29,
132};
133
134enum mlx5_event {
135 MLX5_EVENT_TYPE_COMP = 0x0,
136
137 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
138 MLX5_EVENT_TYPE_COMM_EST = 0x02,
139 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
140 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
141 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
142
143 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
144 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
145 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
146 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
147 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
148 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
149
150 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
151 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
152 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
153 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
154
155 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
156 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
157
158 MLX5_EVENT_TYPE_CMD = 0x0a,
159 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
160};
161
162enum {
163 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
164 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
165 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
166 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
167 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
168 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
169 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
170};
171
172enum {
173 MLX5_DEV_CAP_FLAG_RC = 1LL << 0,
174 MLX5_DEV_CAP_FLAG_UC = 1LL << 1,
175 MLX5_DEV_CAP_FLAG_UD = 1LL << 2,
176 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
177 MLX5_DEV_CAP_FLAG_SRQ = 1LL << 6,
178 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
179 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
180 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
181 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
182 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
183 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
184 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
185 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
186 MLX5_DEV_CAP_FLAG_RESIZE_SRQ = 1LL << 32,
187 MLX5_DEV_CAP_FLAG_REMOTE_FENCE = 1LL << 38,
188 MLX5_DEV_CAP_FLAG_TLP_HINTS = 1LL << 39,
189 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
190 MLX5_DEV_CAP_FLAG_DCT = 1LL << 41,
191 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
192};
193
194enum {
195 MLX5_OPCODE_NOP = 0x00,
196 MLX5_OPCODE_SEND_INVAL = 0x01,
197 MLX5_OPCODE_RDMA_WRITE = 0x08,
198 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
199 MLX5_OPCODE_SEND = 0x0a,
200 MLX5_OPCODE_SEND_IMM = 0x0b,
201 MLX5_OPCODE_RDMA_READ = 0x10,
202 MLX5_OPCODE_ATOMIC_CS = 0x11,
203 MLX5_OPCODE_ATOMIC_FA = 0x12,
204 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
205 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
206 MLX5_OPCODE_BIND_MW = 0x18,
207 MLX5_OPCODE_CONFIG_CMD = 0x1f,
208
209 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
210 MLX5_RECV_OPCODE_SEND = 0x01,
211 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
212 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
213
214 MLX5_CQE_OPCODE_ERROR = 0x1e,
215 MLX5_CQE_OPCODE_RESIZE = 0x16,
216
217 MLX5_OPCODE_SET_PSV = 0x20,
218 MLX5_OPCODE_GET_PSV = 0x21,
219 MLX5_OPCODE_CHECK_PSV = 0x22,
220 MLX5_OPCODE_RGET_PSV = 0x26,
221 MLX5_OPCODE_RCHECK_PSV = 0x27,
222
223 MLX5_OPCODE_UMR = 0x25,
224
225};
226
227enum {
228 MLX5_SET_PORT_RESET_QKEY = 0,
229 MLX5_SET_PORT_GUID0 = 16,
230 MLX5_SET_PORT_NODE_GUID = 17,
231 MLX5_SET_PORT_SYS_GUID = 18,
232 MLX5_SET_PORT_GID_TABLE = 19,
233 MLX5_SET_PORT_PKEY_TABLE = 20,
234};
235
236enum {
237 MLX5_MAX_PAGE_SHIFT = 31
238};
239
240enum {
241 MLX5_ADAPTER_PAGE_SHIFT = 12,
242 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
243};
244
245enum {
246 MLX5_CAP_OFF_DCT = 41,
247 MLX5_CAP_OFF_CMDIF_CSUM = 46,
248};
249
250struct mlx5_inbox_hdr {
251 __be16 opcode;
252 u8 rsvd[4];
253 __be16 opmod;
254};
255
256struct mlx5_outbox_hdr {
257 u8 status;
258 u8 rsvd[3];
259 __be32 syndrome;
260};
261
262struct mlx5_cmd_query_adapter_mbox_in {
263 struct mlx5_inbox_hdr hdr;
264 u8 rsvd[8];
265};
266
267struct mlx5_cmd_query_adapter_mbox_out {
268 struct mlx5_outbox_hdr hdr;
269 u8 rsvd0[24];
270 u8 intapin;
271 u8 rsvd1[13];
272 __be16 vsd_vendor_id;
273 u8 vsd[208];
274 u8 vsd_psid[16];
275};
276
277struct mlx5_hca_cap {
278 u8 rsvd1[16];
279 u8 log_max_srq_sz;
280 u8 log_max_qp_sz;
281 u8 rsvd2;
282 u8 log_max_qp;
283 u8 log_max_strq_sz;
284 u8 log_max_srqs;
285 u8 rsvd4[2];
286 u8 rsvd5;
287 u8 log_max_cq_sz;
288 u8 rsvd6;
289 u8 log_max_cq;
290 u8 log_max_eq_sz;
291 u8 log_max_mkey;
292 u8 rsvd7;
293 u8 log_max_eq;
294 u8 max_indirection;
295 u8 log_max_mrw_sz;
296 u8 log_max_bsf_list_sz;
297 u8 log_max_klm_list_sz;
298 u8 rsvd_8_0;
299 u8 log_max_ra_req_dc;
300 u8 rsvd_8_1;
301 u8 log_max_ra_res_dc;
302 u8 rsvd9;
303 u8 log_max_ra_req_qp;
304 u8 rsvd10;
305 u8 log_max_ra_res_qp;
306 u8 rsvd11[4];
307 __be16 max_qp_count;
308 __be16 rsvd12;
309 u8 rsvd13;
310 u8 local_ca_ack_delay;
311 u8 rsvd14;
312 u8 num_ports;
313 u8 log_max_msg;
314 u8 rsvd15[3];
315 __be16 stat_rate_support;
316 u8 rsvd16[2];
317 __be64 flags;
318 u8 rsvd17;
319 u8 uar_sz;
320 u8 rsvd18;
321 u8 log_pg_sz;
322 __be16 bf_log_bf_reg_size;
323 u8 rsvd19[4];
324 __be16 max_desc_sz_sq;
325 u8 rsvd20[2];
326 __be16 max_desc_sz_rq;
327 u8 rsvd21[2];
328 __be16 max_desc_sz_sq_dc;
329 __be32 max_qp_mcg;
330 u8 rsvd22[3];
331 u8 log_max_mcg;
332 u8 rsvd23;
333 u8 log_max_pd;
334 u8 rsvd24;
335 u8 log_max_xrcd;
336 u8 rsvd25[42];
337 __be16 log_uar_page_sz;
338 u8 rsvd26[28];
339 u8 log_max_atomic_size_qp;
340 u8 rsvd27[2];
341 u8 log_max_atomic_size_dc;
342 u8 rsvd28[76];
343};
344
345
346struct mlx5_cmd_query_hca_cap_mbox_in {
347 struct mlx5_inbox_hdr hdr;
348 u8 rsvd[8];
349};
350
351
352struct mlx5_cmd_query_hca_cap_mbox_out {
353 struct mlx5_outbox_hdr hdr;
354 u8 rsvd0[8];
355 struct mlx5_hca_cap hca_cap;
356};
357
358
359struct mlx5_cmd_set_hca_cap_mbox_in {
360 struct mlx5_inbox_hdr hdr;
361 u8 rsvd[8];
362 struct mlx5_hca_cap hca_cap;
363};
364
365
366struct mlx5_cmd_set_hca_cap_mbox_out {
367 struct mlx5_outbox_hdr hdr;
368 u8 rsvd0[8];
369};
370
371
372struct mlx5_cmd_init_hca_mbox_in {
373 struct mlx5_inbox_hdr hdr;
374 u8 rsvd0[2];
375 __be16 profile;
376 u8 rsvd1[4];
377};
378
379struct mlx5_cmd_init_hca_mbox_out {
380 struct mlx5_outbox_hdr hdr;
381 u8 rsvd[8];
382};
383
384struct mlx5_cmd_teardown_hca_mbox_in {
385 struct mlx5_inbox_hdr hdr;
386 u8 rsvd0[2];
387 __be16 profile;
388 u8 rsvd1[4];
389};
390
391struct mlx5_cmd_teardown_hca_mbox_out {
392 struct mlx5_outbox_hdr hdr;
393 u8 rsvd[8];
394};
395
396struct mlx5_cmd_layout {
397 u8 type;
398 u8 rsvd0[3];
399 __be32 inlen;
400 __be64 in_ptr;
401 __be32 in[4];
402 __be32 out[4];
403 __be64 out_ptr;
404 __be32 outlen;
405 u8 token;
406 u8 sig;
407 u8 rsvd1;
408 u8 status_own;
409};
410
411
412struct health_buffer {
413 __be32 assert_var[5];
414 __be32 rsvd0[3];
415 __be32 assert_exit_ptr;
416 __be32 assert_callra;
417 __be32 rsvd1[2];
418 __be32 fw_ver;
419 __be32 hw_id;
420 __be32 rsvd2;
421 u8 irisc_index;
422 u8 synd;
423 __be16 ext_sync;
424};
425
426struct mlx5_init_seg {
427 __be32 fw_rev;
428 __be32 cmdif_rev_fw_sub;
429 __be32 rsvd0[2];
430 __be32 cmdq_addr_h;
431 __be32 cmdq_addr_l_sz;
432 __be32 cmd_dbell;
433 __be32 rsvd1[121];
434 struct health_buffer health;
435 __be32 rsvd2[884];
436 __be32 health_counter;
437 __be32 rsvd3[1019];
438 __be64 ieee1588_clk;
439 __be32 ieee1588_clk_type;
440 __be32 clr_intx;
441};
442
443struct mlx5_eqe_comp {
444 __be32 reserved[6];
445 __be32 cqn;
446};
447
448struct mlx5_eqe_qp_srq {
449 __be32 reserved[6];
450 __be32 qp_srq_n;
451};
452
453struct mlx5_eqe_cq_err {
454 __be32 cqn;
455 u8 reserved1[7];
456 u8 syndrome;
457};
458
459struct mlx5_eqe_dropped_packet {
460};
461
462struct mlx5_eqe_port_state {
463 u8 reserved0[8];
464 u8 port;
465};
466
467struct mlx5_eqe_gpio {
468 __be32 reserved0[2];
469 __be64 gpio_event;
470};
471
472struct mlx5_eqe_congestion {
473 u8 type;
474 u8 rsvd0;
475 u8 congestion_level;
476};
477
478struct mlx5_eqe_stall_vl {
479 u8 rsvd0[3];
480 u8 port_vl;
481};
482
483struct mlx5_eqe_cmd {
484 __be32 vector;
485 __be32 rsvd[6];
486};
487
488struct mlx5_eqe_page_req {
489 u8 rsvd0[2];
490 __be16 func_id;
491 __be32 num_pages;
492 __be32 rsvd1[5];
493};
494
495union ev_data {
496 __be32 raw[7];
497 struct mlx5_eqe_cmd cmd;
498 struct mlx5_eqe_comp comp;
499 struct mlx5_eqe_qp_srq qp_srq;
500 struct mlx5_eqe_cq_err cq_err;
501 struct mlx5_eqe_dropped_packet dp;
502 struct mlx5_eqe_port_state port;
503 struct mlx5_eqe_gpio gpio;
504 struct mlx5_eqe_congestion cong;
505 struct mlx5_eqe_stall_vl stall_vl;
506 struct mlx5_eqe_page_req req_pages;
507} __packed;
508
509struct mlx5_eqe {
510 u8 rsvd0;
511 u8 type;
512 u8 rsvd1;
513 u8 sub_type;
514 __be32 rsvd2[7];
515 union ev_data data;
516 __be16 rsvd3;
517 u8 signature;
518 u8 owner;
519} __packed;
520
521struct mlx5_cmd_prot_block {
522 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
523 u8 rsvd0[48];
524 __be64 next;
525 __be32 block_num;
526 u8 rsvd1;
527 u8 token;
528 u8 ctrl_sig;
529 u8 sig;
530};
531
532struct mlx5_err_cqe {
533 u8 rsvd0[32];
534 __be32 srqn;
535 u8 rsvd1[18];
536 u8 vendor_err_synd;
537 u8 syndrome;
538 __be32 s_wqe_opcode_qpn;
539 __be16 wqe_counter;
540 u8 signature;
541 u8 op_own;
542};
543
544struct mlx5_cqe64 {
545 u8 rsvd0[17];
546 u8 ml_path;
547 u8 rsvd20[4];
548 __be16 slid;
549 __be32 flags_rqpn;
550 u8 rsvd28[4];
551 __be32 srqn;
552 __be32 imm_inval_pkey;
553 u8 rsvd40[4];
554 __be32 byte_cnt;
555 __be64 timestamp;
556 __be32 sop_drop_qpn;
557 __be16 wqe_counter;
558 u8 signature;
559 u8 op_own;
560};
561
562struct mlx5_sig_err_cqe {
563 u8 rsvd0[16];
564 __be32 expected_trans_sig;
565 __be32 actual_trans_sig;
566 __be32 expected_reftag;
567 __be32 actual_reftag;
568 __be16 syndrome;
569 u8 rsvd22[2];
570 __be32 mkey;
571 __be64 err_offset;
572 u8 rsvd30[8];
573 __be32 qpn;
574 u8 rsvd38[2];
575 u8 signature;
576 u8 op_own;
577};
578
579struct mlx5_wqe_srq_next_seg {
580 u8 rsvd0[2];
581 __be16 next_wqe_index;
582 u8 signature;
583 u8 rsvd1[11];
584};
585
586union mlx5_ext_cqe {
587 struct ib_grh grh;
588 u8 inl[64];
589};
590
591struct mlx5_cqe128 {
592 union mlx5_ext_cqe inl_grh;
593 struct mlx5_cqe64 cqe64;
594};
595
596struct mlx5_srq_ctx {
597 u8 state_log_sz;
598 u8 rsvd0[3];
599 __be32 flags_xrcd;
600 __be32 pgoff_cqn;
601 u8 rsvd1[4];
602 u8 log_pg_sz;
603 u8 rsvd2[7];
604 __be32 pd;
605 __be16 lwm;
606 __be16 wqe_cnt;
607 u8 rsvd3[8];
608 __be64 db_record;
609};
610
611struct mlx5_create_srq_mbox_in {
612 struct mlx5_inbox_hdr hdr;
613 __be32 input_srqn;
614 u8 rsvd0[4];
615 struct mlx5_srq_ctx ctx;
616 u8 rsvd1[208];
617 __be64 pas[0];
618};
619
620struct mlx5_create_srq_mbox_out {
621 struct mlx5_outbox_hdr hdr;
622 __be32 srqn;
623 u8 rsvd[4];
624};
625
626struct mlx5_destroy_srq_mbox_in {
627 struct mlx5_inbox_hdr hdr;
628 __be32 srqn;
629 u8 rsvd[4];
630};
631
632struct mlx5_destroy_srq_mbox_out {
633 struct mlx5_outbox_hdr hdr;
634 u8 rsvd[8];
635};
636
637struct mlx5_query_srq_mbox_in {
638 struct mlx5_inbox_hdr hdr;
639 __be32 srqn;
640 u8 rsvd0[4];
641};
642
643struct mlx5_query_srq_mbox_out {
644 struct mlx5_outbox_hdr hdr;
645 u8 rsvd0[8];
646 struct mlx5_srq_ctx ctx;
647 u8 rsvd1[32];
648 __be64 pas[0];
649};
650
651struct mlx5_arm_srq_mbox_in {
652 struct mlx5_inbox_hdr hdr;
653 __be32 srqn;
654 __be16 rsvd;
655 __be16 lwm;
656};
657
658struct mlx5_arm_srq_mbox_out {
659 struct mlx5_outbox_hdr hdr;
660 u8 rsvd[8];
661};
662
663struct mlx5_cq_context {
664 u8 status;
665 u8 cqe_sz_flags;
666 u8 st;
667 u8 rsvd3;
668 u8 rsvd4[6];
669 __be16 page_offset;
670 __be32 log_sz_usr_page;
671 __be16 cq_period;
672 __be16 cq_max_count;
673 __be16 rsvd20;
674 __be16 c_eqn;
675 u8 log_pg_sz;
676 u8 rsvd25[7];
677 __be32 last_notified_index;
678 __be32 solicit_producer_index;
679 __be32 consumer_counter;
680 __be32 producer_counter;
681 u8 rsvd48[8];
682 __be64 db_record_addr;
683};
684
685struct mlx5_create_cq_mbox_in {
686 struct mlx5_inbox_hdr hdr;
687 __be32 input_cqn;
688 u8 rsvdx[4];
689 struct mlx5_cq_context ctx;
690 u8 rsvd6[192];
691 __be64 pas[0];
692};
693
694struct mlx5_create_cq_mbox_out {
695 struct mlx5_outbox_hdr hdr;
696 __be32 cqn;
697 u8 rsvd0[4];
698};
699
700struct mlx5_destroy_cq_mbox_in {
701 struct mlx5_inbox_hdr hdr;
702 __be32 cqn;
703 u8 rsvd0[4];
704};
705
706struct mlx5_destroy_cq_mbox_out {
707 struct mlx5_outbox_hdr hdr;
708 u8 rsvd0[8];
709};
710
711struct mlx5_query_cq_mbox_in {
712 struct mlx5_inbox_hdr hdr;
713 __be32 cqn;
714 u8 rsvd0[4];
715};
716
717struct mlx5_query_cq_mbox_out {
718 struct mlx5_outbox_hdr hdr;
719 u8 rsvd0[8];
720 struct mlx5_cq_context ctx;
721 u8 rsvd6[16];
722 __be64 pas[0];
723};
724
725struct mlx5_modify_cq_mbox_in {
726 struct mlx5_inbox_hdr hdr;
727 __be32 cqn;
728 __be32 field_select;
729 struct mlx5_cq_context ctx;
730 u8 rsvd[192];
731 __be64 pas[0];
732};
733
734struct mlx5_modify_cq_mbox_out {
735 struct mlx5_outbox_hdr hdr;
736 u8 rsvd[8];
737};
738
739struct mlx5_enable_hca_mbox_in {
740 struct mlx5_inbox_hdr hdr;
741 u8 rsvd[8];
742};
743
744struct mlx5_enable_hca_mbox_out {
745 struct mlx5_outbox_hdr hdr;
746 u8 rsvd[8];
747};
748
749struct mlx5_disable_hca_mbox_in {
750 struct mlx5_inbox_hdr hdr;
751 u8 rsvd[8];
752};
753
754struct mlx5_disable_hca_mbox_out {
755 struct mlx5_outbox_hdr hdr;
756 u8 rsvd[8];
757};
758
759struct mlx5_eq_context {
760 u8 status;
761 u8 ec_oi;
762 u8 st;
763 u8 rsvd2[7];
764 __be16 page_pffset;
765 __be32 log_sz_usr_page;
766 u8 rsvd3[7];
767 u8 intr;
768 u8 log_page_size;
769 u8 rsvd4[15];
770 __be32 consumer_counter;
771 __be32 produser_counter;
772 u8 rsvd5[16];
773};
774
775struct mlx5_create_eq_mbox_in {
776 struct mlx5_inbox_hdr hdr;
777 u8 rsvd0[3];
778 u8 input_eqn;
779 u8 rsvd1[4];
780 struct mlx5_eq_context ctx;
781 u8 rsvd2[8];
782 __be64 events_mask;
783 u8 rsvd3[176];
784 __be64 pas[0];
785};
786
787struct mlx5_create_eq_mbox_out {
788 struct mlx5_outbox_hdr hdr;
789 u8 rsvd0[3];
790 u8 eq_number;
791 u8 rsvd1[4];
792};
793
794struct mlx5_destroy_eq_mbox_in {
795 struct mlx5_inbox_hdr hdr;
796 u8 rsvd0[3];
797 u8 eqn;
798 u8 rsvd1[4];
799};
800
801struct mlx5_destroy_eq_mbox_out {
802 struct mlx5_outbox_hdr hdr;
803 u8 rsvd[8];
804};
805
806struct mlx5_map_eq_mbox_in {
807 struct mlx5_inbox_hdr hdr;
808 __be64 mask;
809 u8 mu;
810 u8 rsvd0[2];
811 u8 eqn;
812 u8 rsvd1[24];
813};
814
815struct mlx5_map_eq_mbox_out {
816 struct mlx5_outbox_hdr hdr;
817 u8 rsvd[8];
818};
819
820struct mlx5_query_eq_mbox_in {
821 struct mlx5_inbox_hdr hdr;
822 u8 rsvd0[3];
823 u8 eqn;
824 u8 rsvd1[4];
825};
826
827struct mlx5_query_eq_mbox_out {
828 struct mlx5_outbox_hdr hdr;
829 u8 rsvd[8];
830 struct mlx5_eq_context ctx;
831};
832
833struct mlx5_mkey_seg {
834 /* This is a two bit field occupying bits 31-30.
835 * bit 31 is always 0,
836 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
837 */
838 u8 status;
839 u8 pcie_control;
840 u8 flags;
841 u8 version;
842 __be32 qpn_mkey7_0;
843 u8 rsvd1[4];
844 __be32 flags_pd;
845 __be64 start_addr;
846 __be64 len;
847 __be32 bsfs_octo_size;
848 u8 rsvd2[16];
849 __be32 xlt_oct_size;
850 u8 rsvd3[3];
851 u8 log2_page_size;
852 u8 rsvd4[4];
853};
854
855struct mlx5_query_special_ctxs_mbox_in {
856 struct mlx5_inbox_hdr hdr;
857 u8 rsvd[8];
858};
859
860struct mlx5_query_special_ctxs_mbox_out {
861 struct mlx5_outbox_hdr hdr;
862 __be32 dump_fill_mkey;
863 __be32 reserved_lkey;
864};
865
866struct mlx5_create_mkey_mbox_in {
867 struct mlx5_inbox_hdr hdr;
868 __be32 input_mkey_index;
869 u8 rsvd0[4];
870 struct mlx5_mkey_seg seg;
871 u8 rsvd1[16];
872 __be32 xlat_oct_act_size;
873 __be32 rsvd2;
874 u8 rsvd3[168];
875 __be64 pas[0];
876};
877
878struct mlx5_create_mkey_mbox_out {
879 struct mlx5_outbox_hdr hdr;
880 __be32 mkey;
881 u8 rsvd[4];
882};
883
884struct mlx5_destroy_mkey_mbox_in {
885 struct mlx5_inbox_hdr hdr;
886 __be32 mkey;
887 u8 rsvd[4];
888};
889
890struct mlx5_destroy_mkey_mbox_out {
891 struct mlx5_outbox_hdr hdr;
892 u8 rsvd[8];
893};
894
895struct mlx5_query_mkey_mbox_in {
896 struct mlx5_inbox_hdr hdr;
897 __be32 mkey;
898};
899
900struct mlx5_query_mkey_mbox_out {
901 struct mlx5_outbox_hdr hdr;
902 __be64 pas[0];
903};
904
905struct mlx5_modify_mkey_mbox_in {
906 struct mlx5_inbox_hdr hdr;
907 __be32 mkey;
908 __be64 pas[0];
909};
910
911struct mlx5_modify_mkey_mbox_out {
912 struct mlx5_outbox_hdr hdr;
913 u8 rsvd[8];
914};
915
916struct mlx5_dump_mkey_mbox_in {
917 struct mlx5_inbox_hdr hdr;
918};
919
920struct mlx5_dump_mkey_mbox_out {
921 struct mlx5_outbox_hdr hdr;
922 __be32 mkey;
923};
924
925struct mlx5_mad_ifc_mbox_in {
926 struct mlx5_inbox_hdr hdr;
927 __be16 remote_lid;
928 u8 rsvd0;
929 u8 port;
930 u8 rsvd1[4];
931 u8 data[256];
932};
933
934struct mlx5_mad_ifc_mbox_out {
935 struct mlx5_outbox_hdr hdr;
936 u8 rsvd[8];
937 u8 data[256];
938};
939
940struct mlx5_access_reg_mbox_in {
941 struct mlx5_inbox_hdr hdr;
942 u8 rsvd0[2];
943 __be16 register_id;
944 __be32 arg;
945 __be32 data[0];
946};
947
948struct mlx5_access_reg_mbox_out {
949 struct mlx5_outbox_hdr hdr;
950 u8 rsvd[8];
951 __be32 data[0];
952};
953
954#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
955
956enum {
957 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
958};
959
960struct mlx5_allocate_psv_in {
961 struct mlx5_inbox_hdr hdr;
962 __be32 npsv_pd;
963 __be32 rsvd_psv0;
964};
965
966struct mlx5_allocate_psv_out {
967 struct mlx5_outbox_hdr hdr;
968 u8 rsvd[8];
969 __be32 psv_idx[4];
970};
971
972struct mlx5_destroy_psv_in {
973 struct mlx5_inbox_hdr hdr;
974 __be32 psv_number;
975 u8 rsvd[4];
976};
977
978struct mlx5_destroy_psv_out {
979 struct mlx5_outbox_hdr hdr;
980 u8 rsvd[8];
981};
982
983#endif /* MLX5_DEVICE_H */