tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*----- < smil.h> ----------------------------------------------------*/
2#ifndef SMIL_INCD
3#define SMIL_INCD
4
5/***************************************************************************
6Define Definition
7***************************************************************************/
8#define K_BYTE 1024 /* Kilo Byte */
9#define SECTSIZE 512 /* Sector buffer size */
10#define REDTSIZE 16 /* Redundant buffer size */
11
12/***************************************************************************/
13#define DUMMY_DATA 0xFF /* No Assign Sector Read Data */
14
15/***************************************************************************
16Max Zone/Block/Sectors Data Definition
17***************************************************************************/
18#define MAX_ZONENUM 128 /* Max Zone Numbers in a SmartMedia */
19#define MAX_BLOCKNUM 0x0400 /* Max Block Numbers in a Zone */
20#define MAX_SECTNUM 0x20 /* Max Sector Numbers in a Block */
21#define MAX_LOGBLOCK 1000 /* Max Logical Block Numbers in a Zone */
22
23/***************************************************************************/
24#define CIS_SEARCH_SECT 0x08 /* Max CIS Search Sector Number */
25
26/***************************************************************************
27Logical to Physical Block Table Data Definition
28***************************************************************************/
29#define NO_ASSIGN 0xFFFF /* No Assign Logical Block Address */
30
31/***************************************************************************
32'SectCopyMode' Data
33***************************************************************************/
34#define COMPLETED 0 /* Sector Copy Completed */
35#define REQ_ERASE 1 /* Request Read Block Erase */
36#define REQ_FAIL 2 /* Request Read Block Failed */
37
38/***************************************************************************
39Retry Counter Definition
40***************************************************************************/
41#define RDERR_REASSIGN 1 /* Reassign with Read Error */
42#define L2P_ERR_ERASE 1 /* BlockErase for Contradicted L2P Table */
43
44/***************************************************************************
45Hardware ECC Definition
46***************************************************************************/
47#define HW_ECC_SUPPORTED 1 /* Hardware ECC Supported */
48/* No definition for Software ECC */
49
50/***************************************************************************
51SmartMedia Command & Status Definition
52***************************************************************************/
53/* SmartMedia Command */
54#define WRDATA 0x80
55/* #define READ 0x00 */
56#define READ_REDT 0x50
57/* #define WRITE 0x10 */
58#define RDSTATUS 0x70
59
60#define READ1 0x00 /* NO */
61#define READ2 0x01 /* NO */
62#define READ3 0x50 /* NO */
63#define RST_CHIP 0xFF
64#define ERASE1 0x60
65#define ERASE2 0xD0
66#define READ_ID_1 0x90
67#define READ_ID_2 0x91
68#define READ_ID_3 0x9A
69
70/* 712 SmartMedia Command */
71#define SM_CMD_RESET 0x00 /* 0xFF */
72#define SM_CMD_READ_ID_1 0x10 /* 0x90 */
73#define SM_CMD_READ_ID_2 0x20 /* 0x91 */
74#define SM_CMD_READ_STAT 0x30 /* 0x70 */
75#define SM_CMD_RDMULTPL_STAT 0x40 /* 0x71 */
76#define SM_CMD_READ_1 0x50 /* 0x00 */
77#define SM_CMD_READ_2 0x60 /* 0x01 */
78#define SM_CMD_READ_3 0x70 /* 0x50 */
79#define SM_CMD_PAGPRGM_TRUE 0x80 /* {0x80, 0x10} */
80#define SM_CMD_PAGPRGM_DUMY 0x90 /* {0x80, 0x11} */
81#define SM_CMD_PAGPRGM_MBLK 0xA0 /* {0x80, 0x15} */
82#define SM_CMD_BLKERASE 0xB0 /* {0x60, 0xD0} */
83#define SM_CMD_BLKERASE_MULTPL 0xC0 /* {0x60-0x60, 0xD0} */
84
85#define SM_CRADDTCT_DEBNCETIMER_EN 0x02
86#define SM_CMD_START_BIT 0x01
87
88#define SM_WaitCmdDone { while (!SM_CmdDone); }
89#define SM_WaitDmaDone { while (!SM_DmaDone); }
90
91/* SmartMedia Status */
92#define WR_FAIL 0x01 /* 0:Pass, 1:Fail */
93#define SUSPENDED 0x20 /* 0:Not Suspended, 1:Suspended */
94#define READY 0x40 /* 0:Busy, 1:Ready */
95#define WR_PRTCT 0x80 /* 0:Protect, 1:Not Protect */
96
97/* SmartMedia Busy Time (1bit:0.1ms) */
98#define BUSY_PROG 200 /* tPROG : 20ms ----- Program Time old : 200 */
99#define BUSY_ERASE 4000 /* tBERASE : 400ms ----- Block Erase Time old : 4000 */
100
101/*for 712 Test */
102/* #define BUSY_READ 1 *//* tR : 100us ----- Data transfer Time old : 1 */
103/* #define BUSY_READ 10 *//* tR : 100us ----- Data transfer Time old : 1 */
104
105#define BUSY_READ 200 /* tR : 20ms ----- Data transfer Time old : 1 */
106
107/* #define BUSY_RESET 60 *//* tRST : 6ms ----- Device Resetting Time old : 60 */
108
109#define BUSY_RESET 600 /* tRST : 60ms ----- Device Resetting Time old : 60 */
110
111/* Hardware Timer (1bit:0.1ms) */
112#define TIME_PON 3000 /* 300ms ------ Power On Wait Time */
113#define TIME_CDCHK 200 /* 20ms ------ Card Check Interval Timer */
114#define TIME_WPCHK 50 /* 5ms ------ WP Check Interval Timer */
115#define TIME_5VCHK 10 /* 1ms ------ 5V Check Interval Timer */
116
117/***************************************************************************
118Redundant Data
119***************************************************************************/
120#define REDT_DATA 0x04
121#define REDT_BLOCK 0x05
122#define REDT_ADDR1H 0x06
123#define REDT_ADDR1L 0x07
124#define REDT_ADDR2H 0x0B
125#define REDT_ADDR2L 0x0C
126#define REDT_ECC10 0x0D
127#define REDT_ECC11 0x0E
128#define REDT_ECC12 0x0F
129#define REDT_ECC20 0x08
130#define REDT_ECC21 0x09
131#define REDT_ECC22 0x0A
132
133/***************************************************************************
134SmartMedia Model & Attribute
135***************************************************************************/
136/* SmartMedia Attribute */
137#define NOWP 0x00 /* 0... .... No Write Protect */
138#define WP 0x80 /* 1... .... Write Protected */
139#define MASK 0x00 /* .00. .... NAND MASK ROM Model */
140#define FLASH 0x20 /* .01. .... NAND Flash ROM Model */
141#define AD3CYC 0x00 /* ...0 .... Address 3-cycle */
142#define AD4CYC 0x10 /* ...1 .... Address 4-cycle */
143#define BS16 0x00 /* .... 00.. 16page/block */
144#define BS32 0x04 /* .... 01.. 32page/block */
145#define PS256 0x00 /* .... ..00 256byte/page */
146#define PS512 0x01 /* .... ..01 512byte/page */
147#define MWP 0x80 /* WriteProtect mask */
148#define MFLASH 0x60 /* Flash Rom mask */
149#define MADC 0x10 /* Address Cycle */
150#define MBS 0x0C /* BlockSize mask */
151#define MPS 0x03 /* PageSize mask */
152
153/* SmartMedia Model */
154#define NOSSFDC 0x00 /* NO SmartMedia */
155#define SSFDC1MB 0x01 /* 1MB SmartMedia */
156#define SSFDC2MB 0x02 /* 2MB SmartMedia */
157#define SSFDC4MB 0x03 /* 4MB SmartMedia */
158#define SSFDC8MB 0x04 /* 8MB SmartMedia */
159#define SSFDC16MB 0x05 /* 16MB SmartMedia */
160#define SSFDC32MB 0x06 /* 32MB SmartMedia */
161#define SSFDC64MB 0x07 /* 64MB SmartMedia */
162#define SSFDC128MB 0x08 /*128MB SmartMedia */
163#define SSFDC256MB 0x09
164#define SSFDC512MB 0x0A
165#define SSFDC1GB 0x0B
166#define SSFDC2GB 0x0C
167
168/***************************************************************************
169Struct Definition
170***************************************************************************/
171struct keucr_media_info {
172 u8 Model;
173 u8 Attribute;
174 u8 MaxZones;
175 u8 MaxSectors;
176 u16 MaxBlocks;
177 u16 MaxLogBlocks;
178};
179
180struct keucr_media_address {
181 u8 Zone; /* Zone Number */
182 u8 Sector; /* Sector(512byte) Number on Block */
183 u16 PhyBlock; /* Physical Block Number on Zone */
184 u16 LogBlock; /* Logical Block Number of Zone */
185};
186
187struct keucr_media_area {
188 u8 Sector; /* Sector(512byte) Number on Block */
189 u16 PhyBlock; /* Physical Block Number on Zone 0 */
190};
191
192extern u16 ReadBlock;
193extern u16 WriteBlock;
194extern u32 MediaChange;
195
196extern struct keucr_media_info Ssfdc;
197extern struct keucr_media_address Media;
198extern struct keucr_media_area CisArea;
199
200/*
201 * SMILMain.c
202 */
203/******************************************/
204int Init_D_SmartMedia(void);
205int Pwoff_D_SmartMedia(void);
206int Check_D_SmartMedia(void);
207int Check_D_MediaFmt(struct us_data *);
208int Check_D_Parameter(struct us_data *, u16 *, u8 *, u8 *);
209int Media_D_ReadSector(struct us_data *, u32, u16, u8 *);
210int Media_D_WriteSector(struct us_data *, u32, u16, u8 *);
211int Media_D_CopySector(struct us_data *, u32, u16, u8 *);
212int Media_D_EraseBlock(struct us_data *, u32, u16);
213int Media_D_EraseAll(struct us_data *);
214/******************************************/
215int Media_D_OneSectWriteStart(struct us_data *, u32, u8 *);
216int Media_D_OneSectWriteNext(struct us_data *, u8 *);
217int Media_D_OneSectWriteFlush(struct us_data *);
218
219/******************************************/
220extern int SM_FreeMem(void); /* ENE SM function */
221void SM_EnableLED(struct us_data *, bool);
222void Led_D_TernOn(void);
223void Led_D_TernOff(void);
224
225int Media_D_EraseAllRedtData(u32 Index, bool CheckBlock);
226/*DWORD Media_D_GetMediaInfo(struct us_data * fdoExt,
227 PIOCTL_MEDIA_INFO_IN pParamIn, PIOCTL_MEDIA_INFO_OUT pParamOut); */
228
229/*
230 * SMILSub.c
231 */
232/******************************************/
233int Check_D_DataBlank(u8 *);
234int Check_D_FailBlock(u8 *);
235int Check_D_DataStatus(u8 *);
236int Load_D_LogBlockAddr(u8 *);
237void Clr_D_RedundantData(u8 *);
238void Set_D_LogBlockAddr(u8 *);
239void Set_D_FailBlock(u8 *);
240void Set_D_DataStaus(u8 *);
241
242/******************************************/
243void Ssfdc_D_Reset(struct us_data *);
244int Ssfdc_D_ReadCisSect(struct us_data *, u8 *, u8 *);
245void Ssfdc_D_WriteRedtMode(void);
246void Ssfdc_D_ReadID(u8 *, u8);
247int Ssfdc_D_ReadSect(struct us_data *, u8 *, u8 *);
248int Ssfdc_D_ReadBlock(struct us_data *, u16, u8 *, u8 *);
249int Ssfdc_D_WriteSect(struct us_data *, u8 *, u8 *);
250int Ssfdc_D_WriteBlock(struct us_data *, u16, u8 *, u8 *);
251int Ssfdc_D_CopyBlock(struct us_data *, u16, u8 *, u8 *);
252int Ssfdc_D_WriteSectForCopy(struct us_data *, u8 *, u8 *);
253int Ssfdc_D_EraseBlock(struct us_data *);
254int Ssfdc_D_ReadRedtData(struct us_data *, u8 *);
255int Ssfdc_D_WriteRedtData(struct us_data *, u8 *);
256int Ssfdc_D_CheckStatus(void);
257int Set_D_SsfdcModel(u8);
258void Cnt_D_Reset(void);
259int Cnt_D_PowerOn(void);
260void Cnt_D_PowerOff(void);
261void Cnt_D_LedOn(void);
262void Cnt_D_LedOff(void);
263int Check_D_CntPower(void);
264int Check_D_CardExist(void);
265int Check_D_CardStsChg(void);
266int Check_D_SsfdcWP(void);
267int SM_ReadBlock(struct us_data *, u8 *, u8 *);
268
269int Ssfdc_D_ReadSect_DMA(struct us_data *, u8 *, u8 *);
270int Ssfdc_D_ReadSect_PIO(struct us_data *, u8 *, u8 *);
271int Ssfdc_D_WriteSect_DMA(struct us_data *, u8 *, u8 *);
272int Ssfdc_D_WriteSect_PIO(struct us_data *, u8 *, u8 *);
273
274/******************************************/
275int Check_D_ReadError(u8 *);
276int Check_D_Correct(u8 *, u8 *);
277int Check_D_CISdata(u8 *, u8 *);
278void Set_D_RightECC(u8 *);
279
280/*
281 * SMILECC.c
282 */
283void calculate_ecc(u8 *, u8 *, u8 *, u8 *, u8 *);
284u8 correct_data(u8 *, u8 *, u8, u8, u8);
285int _Correct_D_SwECC(u8 *, u8 *, u8 *);
286void _Calculate_D_SwECC(u8 *, u8 *);
287
288#endif /* already included */