tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14
15#include "skeleton.dtsi"
16
17/ {
18 aliases {
19 ethernet0 = &fec;
20 can0 = &can1;
21 can1 = &can2;
22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
29 i2c0 = &i2c1;
30 i2c1 = &i2c2;
31 i2c2 = &i2c3;
32 mmc0 = &usdhc1;
33 mmc1 = &usdhc2;
34 mmc2 = &usdhc3;
35 mmc3 = &usdhc4;
36 serial0 = &uart1;
37 serial1 = &uart2;
38 serial2 = &uart3;
39 serial3 = &uart4;
40 serial4 = &uart5;
41 spi0 = &ecspi1;
42 spi1 = &ecspi2;
43 spi2 = &ecspi3;
44 spi3 = &ecspi4;
45 usbphy0 = &usbphy1;
46 usbphy1 = &usbphy2;
47 };
48
49 intc: interrupt-controller@00a01000 {
50 compatible = "arm,cortex-a9-gic";
51 #interrupt-cells = <3>;
52 interrupt-controller;
53 reg = <0x00a01000 0x1000>,
54 <0x00a00100 0x100>;
55 };
56
57 clocks {
58 #address-cells = <1>;
59 #size-cells = <0>;
60
61 ckil {
62 compatible = "fsl,imx-ckil", "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <32768>;
65 };
66
67 ckih1 {
68 compatible = "fsl,imx-ckih1", "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <0>;
71 };
72
73 osc {
74 compatible = "fsl,imx-osc", "fixed-clock";
75 #clock-cells = <0>;
76 clock-frequency = <24000000>;
77 };
78 };
79
80 soc {
81 #address-cells = <1>;
82 #size-cells = <1>;
83 compatible = "simple-bus";
84 interrupt-parent = <&intc>;
85 ranges;
86
87 dma_apbh: dma-apbh@00110000 {
88 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
89 reg = <0x00110000 0x2000>;
90 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
91 <0 13 IRQ_TYPE_LEVEL_HIGH>,
92 <0 13 IRQ_TYPE_LEVEL_HIGH>,
93 <0 13 IRQ_TYPE_LEVEL_HIGH>;
94 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
95 #dma-cells = <1>;
96 dma-channels = <4>;
97 clocks = <&clks 106>;
98 };
99
100 gpmi: gpmi-nand@00112000 {
101 compatible = "fsl,imx6q-gpmi-nand";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
105 reg-names = "gpmi-nand", "bch";
106 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
107 interrupt-names = "bch";
108 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
109 <&clks 150>, <&clks 149>;
110 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
111 "gpmi_bch_apb", "per1_bch";
112 dmas = <&dma_apbh 0>;
113 dma-names = "rx-tx";
114 status = "disabled";
115 };
116
117 timer@00a00600 {
118 compatible = "arm,cortex-a9-twd-timer";
119 reg = <0x00a00600 0x20>;
120 interrupts = <1 13 0xf01>;
121 clocks = <&clks 15>;
122 };
123
124 L2: l2-cache@00a02000 {
125 compatible = "arm,pl310-cache";
126 reg = <0x00a02000 0x1000>;
127 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
128 cache-unified;
129 cache-level = <2>;
130 arm,tag-latency = <4 2 3>;
131 arm,data-latency = <4 2 3>;
132 };
133
134 pcie: pcie@0x01000000 {
135 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
136 reg = <0x01ffc000 0x4000>; /* DBI */
137 #address-cells = <3>;
138 #size-cells = <2>;
139 device_type = "pci";
140 ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
141 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
142 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
143 num-lanes = <1>;
144 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
145 interrupt-names = "msi";
146 #interrupt-cells = <1>;
147 interrupt-map-mask = <0 0 0 0x7>;
148 interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
149 <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
150 <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
151 <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&clks 144>, <&clks 206>, <&clks 189>;
153 clock-names = "pcie", "pcie_bus", "pcie_phy";
154 status = "disabled";
155 };
156
157 pmu {
158 compatible = "arm,cortex-a9-pmu";
159 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
160 };
161
162 aips-bus@02000000 { /* AIPS1 */
163 compatible = "fsl,aips-bus", "simple-bus";
164 #address-cells = <1>;
165 #size-cells = <1>;
166 reg = <0x02000000 0x100000>;
167 ranges;
168
169 spba-bus@02000000 {
170 compatible = "fsl,spba-bus", "simple-bus";
171 #address-cells = <1>;
172 #size-cells = <1>;
173 reg = <0x02000000 0x40000>;
174 ranges;
175
176 spdif: spdif@02004000 {
177 compatible = "fsl,imx35-spdif";
178 reg = <0x02004000 0x4000>;
179 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
180 dmas = <&sdma 14 18 0>,
181 <&sdma 15 18 0>;
182 dma-names = "rx", "tx";
183 clocks = <&clks 197>, <&clks 3>,
184 <&clks 197>, <&clks 107>,
185 <&clks 0>, <&clks 118>,
186 <&clks 0>, <&clks 139>,
187 <&clks 0>;
188 clock-names = "core", "rxtx0",
189 "rxtx1", "rxtx2",
190 "rxtx3", "rxtx4",
191 "rxtx5", "rxtx6",
192 "rxtx7";
193 status = "disabled";
194 };
195
196 ecspi1: ecspi@02008000 {
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
200 reg = <0x02008000 0x4000>;
201 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&clks 112>, <&clks 112>;
203 clock-names = "ipg", "per";
204 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
205 dma-names = "rx", "tx";
206 status = "disabled";
207 };
208
209 ecspi2: ecspi@0200c000 {
210 #address-cells = <1>;
211 #size-cells = <0>;
212 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
213 reg = <0x0200c000 0x4000>;
214 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&clks 113>, <&clks 113>;
216 clock-names = "ipg", "per";
217 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
218 dma-names = "rx", "tx";
219 status = "disabled";
220 };
221
222 ecspi3: ecspi@02010000 {
223 #address-cells = <1>;
224 #size-cells = <0>;
225 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
226 reg = <0x02010000 0x4000>;
227 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&clks 114>, <&clks 114>;
229 clock-names = "ipg", "per";
230 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
231 dma-names = "rx", "tx";
232 status = "disabled";
233 };
234
235 ecspi4: ecspi@02014000 {
236 #address-cells = <1>;
237 #size-cells = <0>;
238 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
239 reg = <0x02014000 0x4000>;
240 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&clks 115>, <&clks 115>;
242 clock-names = "ipg", "per";
243 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
244 dma-names = "rx", "tx";
245 status = "disabled";
246 };
247
248 uart1: serial@02020000 {
249 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
250 reg = <0x02020000 0x4000>;
251 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&clks 160>, <&clks 161>;
253 clock-names = "ipg", "per";
254 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
255 dma-names = "rx", "tx";
256 status = "disabled";
257 };
258
259 esai: esai@02024000 {
260 reg = <0x02024000 0x4000>;
261 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
262 };
263
264 ssi1: ssi@02028000 {
265 compatible = "fsl,imx6q-ssi",
266 "fsl,imx51-ssi",
267 "fsl,imx21-ssi";
268 reg = <0x02028000 0x4000>;
269 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&clks 178>;
271 dmas = <&sdma 37 1 0>,
272 <&sdma 38 1 0>;
273 dma-names = "rx", "tx";
274 fsl,fifo-depth = <15>;
275 fsl,ssi-dma-events = <38 37>;
276 status = "disabled";
277 };
278
279 ssi2: ssi@0202c000 {
280 compatible = "fsl,imx6q-ssi",
281 "fsl,imx51-ssi",
282 "fsl,imx21-ssi";
283 reg = <0x0202c000 0x4000>;
284 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&clks 179>;
286 dmas = <&sdma 41 1 0>,
287 <&sdma 42 1 0>;
288 dma-names = "rx", "tx";
289 fsl,fifo-depth = <15>;
290 fsl,ssi-dma-events = <42 41>;
291 status = "disabled";
292 };
293
294 ssi3: ssi@02030000 {
295 compatible = "fsl,imx6q-ssi",
296 "fsl,imx51-ssi",
297 "fsl,imx21-ssi";
298 reg = <0x02030000 0x4000>;
299 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&clks 180>;
301 dmas = <&sdma 45 1 0>,
302 <&sdma 46 1 0>;
303 dma-names = "rx", "tx";
304 fsl,fifo-depth = <15>;
305 fsl,ssi-dma-events = <46 45>;
306 status = "disabled";
307 };
308
309 asrc: asrc@02034000 {
310 reg = <0x02034000 0x4000>;
311 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
312 };
313
314 spba@0203c000 {
315 reg = <0x0203c000 0x4000>;
316 };
317 };
318
319 vpu: vpu@02040000 {
320 reg = <0x02040000 0x3c000>;
321 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
322 <0 12 IRQ_TYPE_LEVEL_HIGH>;
323 };
324
325 aipstz@0207c000 { /* AIPSTZ1 */
326 reg = <0x0207c000 0x4000>;
327 };
328
329 pwm1: pwm@02080000 {
330 #pwm-cells = <2>;
331 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
332 reg = <0x02080000 0x4000>;
333 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&clks 62>, <&clks 145>;
335 clock-names = "ipg", "per";
336 };
337
338 pwm2: pwm@02084000 {
339 #pwm-cells = <2>;
340 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
341 reg = <0x02084000 0x4000>;
342 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&clks 62>, <&clks 146>;
344 clock-names = "ipg", "per";
345 };
346
347 pwm3: pwm@02088000 {
348 #pwm-cells = <2>;
349 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
350 reg = <0x02088000 0x4000>;
351 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&clks 62>, <&clks 147>;
353 clock-names = "ipg", "per";
354 };
355
356 pwm4: pwm@0208c000 {
357 #pwm-cells = <2>;
358 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
359 reg = <0x0208c000 0x4000>;
360 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&clks 62>, <&clks 148>;
362 clock-names = "ipg", "per";
363 };
364
365 can1: flexcan@02090000 {
366 compatible = "fsl,imx6q-flexcan";
367 reg = <0x02090000 0x4000>;
368 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&clks 108>, <&clks 109>;
370 clock-names = "ipg", "per";
371 status = "disabled";
372 };
373
374 can2: flexcan@02094000 {
375 compatible = "fsl,imx6q-flexcan";
376 reg = <0x02094000 0x4000>;
377 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&clks 110>, <&clks 111>;
379 clock-names = "ipg", "per";
380 status = "disabled";
381 };
382
383 gpt: gpt@02098000 {
384 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
385 reg = <0x02098000 0x4000>;
386 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&clks 119>, <&clks 120>;
388 clock-names = "ipg", "per";
389 };
390
391 gpio1: gpio@0209c000 {
392 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
393 reg = <0x0209c000 0x4000>;
394 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
395 <0 67 IRQ_TYPE_LEVEL_HIGH>;
396 gpio-controller;
397 #gpio-cells = <2>;
398 interrupt-controller;
399 #interrupt-cells = <2>;
400 };
401
402 gpio2: gpio@020a0000 {
403 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
404 reg = <0x020a0000 0x4000>;
405 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
406 <0 69 IRQ_TYPE_LEVEL_HIGH>;
407 gpio-controller;
408 #gpio-cells = <2>;
409 interrupt-controller;
410 #interrupt-cells = <2>;
411 };
412
413 gpio3: gpio@020a4000 {
414 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
415 reg = <0x020a4000 0x4000>;
416 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
417 <0 71 IRQ_TYPE_LEVEL_HIGH>;
418 gpio-controller;
419 #gpio-cells = <2>;
420 interrupt-controller;
421 #interrupt-cells = <2>;
422 };
423
424 gpio4: gpio@020a8000 {
425 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
426 reg = <0x020a8000 0x4000>;
427 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
428 <0 73 IRQ_TYPE_LEVEL_HIGH>;
429 gpio-controller;
430 #gpio-cells = <2>;
431 interrupt-controller;
432 #interrupt-cells = <2>;
433 };
434
435 gpio5: gpio@020ac000 {
436 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
437 reg = <0x020ac000 0x4000>;
438 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
439 <0 75 IRQ_TYPE_LEVEL_HIGH>;
440 gpio-controller;
441 #gpio-cells = <2>;
442 interrupt-controller;
443 #interrupt-cells = <2>;
444 };
445
446 gpio6: gpio@020b0000 {
447 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
448 reg = <0x020b0000 0x4000>;
449 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
450 <0 77 IRQ_TYPE_LEVEL_HIGH>;
451 gpio-controller;
452 #gpio-cells = <2>;
453 interrupt-controller;
454 #interrupt-cells = <2>;
455 };
456
457 gpio7: gpio@020b4000 {
458 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
459 reg = <0x020b4000 0x4000>;
460 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
461 <0 79 IRQ_TYPE_LEVEL_HIGH>;
462 gpio-controller;
463 #gpio-cells = <2>;
464 interrupt-controller;
465 #interrupt-cells = <2>;
466 };
467
468 kpp: kpp@020b8000 {
469 reg = <0x020b8000 0x4000>;
470 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
471 };
472
473 wdog1: wdog@020bc000 {
474 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
475 reg = <0x020bc000 0x4000>;
476 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&clks 0>;
478 };
479
480 wdog2: wdog@020c0000 {
481 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
482 reg = <0x020c0000 0x4000>;
483 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&clks 0>;
485 status = "disabled";
486 };
487
488 clks: ccm@020c4000 {
489 compatible = "fsl,imx6q-ccm";
490 reg = <0x020c4000 0x4000>;
491 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
492 <0 88 IRQ_TYPE_LEVEL_HIGH>;
493 #clock-cells = <1>;
494 };
495
496 anatop: anatop@020c8000 {
497 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
498 reg = <0x020c8000 0x1000>;
499 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
500 <0 54 IRQ_TYPE_LEVEL_HIGH>,
501 <0 127 IRQ_TYPE_LEVEL_HIGH>;
502
503 regulator-1p1@110 {
504 compatible = "fsl,anatop-regulator";
505 regulator-name = "vdd1p1";
506 regulator-min-microvolt = <800000>;
507 regulator-max-microvolt = <1375000>;
508 regulator-always-on;
509 anatop-reg-offset = <0x110>;
510 anatop-vol-bit-shift = <8>;
511 anatop-vol-bit-width = <5>;
512 anatop-min-bit-val = <4>;
513 anatop-min-voltage = <800000>;
514 anatop-max-voltage = <1375000>;
515 };
516
517 regulator-3p0@120 {
518 compatible = "fsl,anatop-regulator";
519 regulator-name = "vdd3p0";
520 regulator-min-microvolt = <2800000>;
521 regulator-max-microvolt = <3150000>;
522 regulator-always-on;
523 anatop-reg-offset = <0x120>;
524 anatop-vol-bit-shift = <8>;
525 anatop-vol-bit-width = <5>;
526 anatop-min-bit-val = <0>;
527 anatop-min-voltage = <2625000>;
528 anatop-max-voltage = <3400000>;
529 };
530
531 regulator-2p5@130 {
532 compatible = "fsl,anatop-regulator";
533 regulator-name = "vdd2p5";
534 regulator-min-microvolt = <2000000>;
535 regulator-max-microvolt = <2750000>;
536 regulator-always-on;
537 anatop-reg-offset = <0x130>;
538 anatop-vol-bit-shift = <8>;
539 anatop-vol-bit-width = <5>;
540 anatop-min-bit-val = <0>;
541 anatop-min-voltage = <2000000>;
542 anatop-max-voltage = <2750000>;
543 };
544
545 reg_arm: regulator-vddcore@140 {
546 compatible = "fsl,anatop-regulator";
547 regulator-name = "vddarm";
548 regulator-min-microvolt = <725000>;
549 regulator-max-microvolt = <1450000>;
550 regulator-always-on;
551 anatop-reg-offset = <0x140>;
552 anatop-vol-bit-shift = <0>;
553 anatop-vol-bit-width = <5>;
554 anatop-delay-reg-offset = <0x170>;
555 anatop-delay-bit-shift = <24>;
556 anatop-delay-bit-width = <2>;
557 anatop-min-bit-val = <1>;
558 anatop-min-voltage = <725000>;
559 anatop-max-voltage = <1450000>;
560 };
561
562 reg_pu: regulator-vddpu@140 {
563 compatible = "fsl,anatop-regulator";
564 regulator-name = "vddpu";
565 regulator-min-microvolt = <725000>;
566 regulator-max-microvolt = <1450000>;
567 regulator-always-on;
568 anatop-reg-offset = <0x140>;
569 anatop-vol-bit-shift = <9>;
570 anatop-vol-bit-width = <5>;
571 anatop-delay-reg-offset = <0x170>;
572 anatop-delay-bit-shift = <26>;
573 anatop-delay-bit-width = <2>;
574 anatop-min-bit-val = <1>;
575 anatop-min-voltage = <725000>;
576 anatop-max-voltage = <1450000>;
577 };
578
579 reg_soc: regulator-vddsoc@140 {
580 compatible = "fsl,anatop-regulator";
581 regulator-name = "vddsoc";
582 regulator-min-microvolt = <725000>;
583 regulator-max-microvolt = <1450000>;
584 regulator-always-on;
585 anatop-reg-offset = <0x140>;
586 anatop-vol-bit-shift = <18>;
587 anatop-vol-bit-width = <5>;
588 anatop-delay-reg-offset = <0x170>;
589 anatop-delay-bit-shift = <28>;
590 anatop-delay-bit-width = <2>;
591 anatop-min-bit-val = <1>;
592 anatop-min-voltage = <725000>;
593 anatop-max-voltage = <1450000>;
594 };
595 };
596
597 tempmon: tempmon {
598 compatible = "fsl,imx6q-tempmon";
599 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
600 fsl,tempmon = <&anatop>;
601 fsl,tempmon-data = <&ocotp>;
602 clocks = <&clks 172>;
603 };
604
605 usbphy1: usbphy@020c9000 {
606 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
607 reg = <0x020c9000 0x1000>;
608 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
609 clocks = <&clks 182>;
610 fsl,anatop = <&anatop>;
611 };
612
613 usbphy2: usbphy@020ca000 {
614 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
615 reg = <0x020ca000 0x1000>;
616 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&clks 183>;
618 fsl,anatop = <&anatop>;
619 };
620
621 snvs@020cc000 {
622 compatible = "fsl,sec-v4.0-mon", "simple-bus";
623 #address-cells = <1>;
624 #size-cells = <1>;
625 ranges = <0 0x020cc000 0x4000>;
626
627 snvs-rtc-lp@34 {
628 compatible = "fsl,sec-v4.0-mon-rtc-lp";
629 reg = <0x34 0x58>;
630 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
631 <0 20 IRQ_TYPE_LEVEL_HIGH>;
632 };
633 };
634
635 epit1: epit@020d0000 { /* EPIT1 */
636 reg = <0x020d0000 0x4000>;
637 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
638 };
639
640 epit2: epit@020d4000 { /* EPIT2 */
641 reg = <0x020d4000 0x4000>;
642 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
643 };
644
645 src: src@020d8000 {
646 compatible = "fsl,imx6q-src", "fsl,imx51-src";
647 reg = <0x020d8000 0x4000>;
648 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
649 <0 96 IRQ_TYPE_LEVEL_HIGH>;
650 #reset-cells = <1>;
651 };
652
653 gpc: gpc@020dc000 {
654 compatible = "fsl,imx6q-gpc";
655 reg = <0x020dc000 0x4000>;
656 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
657 <0 90 IRQ_TYPE_LEVEL_HIGH>;
658 };
659
660 gpr: iomuxc-gpr@020e0000 {
661 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
662 reg = <0x020e0000 0x38>;
663 };
664
665 iomuxc: iomuxc@020e0000 {
666 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
667 reg = <0x020e0000 0x4000>;
668 };
669
670 ldb: ldb@020e0008 {
671 #address-cells = <1>;
672 #size-cells = <0>;
673 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
674 gpr = <&gpr>;
675 status = "disabled";
676
677 lvds-channel@0 {
678 #address-cells = <1>;
679 #size-cells = <0>;
680 reg = <0>;
681 status = "disabled";
682
683 port@0 {
684 reg = <0>;
685
686 lvds0_mux_0: endpoint {
687 remote-endpoint = <&ipu1_di0_lvds0>;
688 };
689 };
690
691 port@1 {
692 reg = <1>;
693
694 lvds0_mux_1: endpoint {
695 remote-endpoint = <&ipu1_di1_lvds0>;
696 };
697 };
698 };
699
700 lvds-channel@1 {
701 #address-cells = <1>;
702 #size-cells = <0>;
703 reg = <1>;
704 status = "disabled";
705
706 port@0 {
707 reg = <0>;
708
709 lvds1_mux_0: endpoint {
710 remote-endpoint = <&ipu1_di0_lvds1>;
711 };
712 };
713
714 port@1 {
715 reg = <1>;
716
717 lvds1_mux_1: endpoint {
718 remote-endpoint = <&ipu1_di1_lvds1>;
719 };
720 };
721 };
722 };
723
724 hdmi: hdmi@0120000 {
725 #address-cells = <1>;
726 #size-cells = <0>;
727 reg = <0x00120000 0x9000>;
728 interrupts = <0 115 0x04>;
729 gpr = <&gpr>;
730 clocks = <&clks 123>, <&clks 124>;
731 clock-names = "iahb", "isfr";
732 status = "disabled";
733
734 port@0 {
735 reg = <0>;
736
737 hdmi_mux_0: endpoint {
738 remote-endpoint = <&ipu1_di0_hdmi>;
739 };
740 };
741
742 port@1 {
743 reg = <1>;
744
745 hdmi_mux_1: endpoint {
746 remote-endpoint = <&ipu1_di1_hdmi>;
747 };
748 };
749 };
750
751 dcic1: dcic@020e4000 {
752 reg = <0x020e4000 0x4000>;
753 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
754 };
755
756 dcic2: dcic@020e8000 {
757 reg = <0x020e8000 0x4000>;
758 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
759 };
760
761 sdma: sdma@020ec000 {
762 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
763 reg = <0x020ec000 0x4000>;
764 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&clks 155>, <&clks 155>;
766 clock-names = "ipg", "ahb";
767 #dma-cells = <3>;
768 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
769 };
770 };
771
772 aips-bus@02100000 { /* AIPS2 */
773 compatible = "fsl,aips-bus", "simple-bus";
774 #address-cells = <1>;
775 #size-cells = <1>;
776 reg = <0x02100000 0x100000>;
777 ranges;
778
779 caam@02100000 {
780 reg = <0x02100000 0x40000>;
781 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
782 <0 106 IRQ_TYPE_LEVEL_HIGH>;
783 };
784
785 aipstz@0217c000 { /* AIPSTZ2 */
786 reg = <0x0217c000 0x4000>;
787 };
788
789 usbotg: usb@02184000 {
790 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
791 reg = <0x02184000 0x200>;
792 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&clks 162>;
794 fsl,usbphy = <&usbphy1>;
795 fsl,usbmisc = <&usbmisc 0>;
796 status = "disabled";
797 };
798
799 usbh1: usb@02184200 {
800 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
801 reg = <0x02184200 0x200>;
802 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
803 clocks = <&clks 162>;
804 fsl,usbphy = <&usbphy2>;
805 fsl,usbmisc = <&usbmisc 1>;
806 status = "disabled";
807 };
808
809 usbh2: usb@02184400 {
810 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
811 reg = <0x02184400 0x200>;
812 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
813 clocks = <&clks 162>;
814 fsl,usbmisc = <&usbmisc 2>;
815 status = "disabled";
816 };
817
818 usbh3: usb@02184600 {
819 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
820 reg = <0x02184600 0x200>;
821 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
822 clocks = <&clks 162>;
823 fsl,usbmisc = <&usbmisc 3>;
824 status = "disabled";
825 };
826
827 usbmisc: usbmisc@02184800 {
828 #index-cells = <1>;
829 compatible = "fsl,imx6q-usbmisc";
830 reg = <0x02184800 0x200>;
831 clocks = <&clks 162>;
832 };
833
834 fec: ethernet@02188000 {
835 compatible = "fsl,imx6q-fec";
836 reg = <0x02188000 0x4000>;
837 interrupts-extended =
838 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
839 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
840 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
841 clock-names = "ipg", "ahb", "ptp";
842 status = "disabled";
843 };
844
845 mlb@0218c000 {
846 reg = <0x0218c000 0x4000>;
847 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
848 <0 117 IRQ_TYPE_LEVEL_HIGH>,
849 <0 126 IRQ_TYPE_LEVEL_HIGH>;
850 };
851
852 usdhc1: usdhc@02190000 {
853 compatible = "fsl,imx6q-usdhc";
854 reg = <0x02190000 0x4000>;
855 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
856 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
857 clock-names = "ipg", "ahb", "per";
858 bus-width = <4>;
859 status = "disabled";
860 };
861
862 usdhc2: usdhc@02194000 {
863 compatible = "fsl,imx6q-usdhc";
864 reg = <0x02194000 0x4000>;
865 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
867 clock-names = "ipg", "ahb", "per";
868 bus-width = <4>;
869 status = "disabled";
870 };
871
872 usdhc3: usdhc@02198000 {
873 compatible = "fsl,imx6q-usdhc";
874 reg = <0x02198000 0x4000>;
875 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
876 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
877 clock-names = "ipg", "ahb", "per";
878 bus-width = <4>;
879 status = "disabled";
880 };
881
882 usdhc4: usdhc@0219c000 {
883 compatible = "fsl,imx6q-usdhc";
884 reg = <0x0219c000 0x4000>;
885 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
886 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
887 clock-names = "ipg", "ahb", "per";
888 bus-width = <4>;
889 status = "disabled";
890 };
891
892 i2c1: i2c@021a0000 {
893 #address-cells = <1>;
894 #size-cells = <0>;
895 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
896 reg = <0x021a0000 0x4000>;
897 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&clks 125>;
899 status = "disabled";
900 };
901
902 i2c2: i2c@021a4000 {
903 #address-cells = <1>;
904 #size-cells = <0>;
905 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
906 reg = <0x021a4000 0x4000>;
907 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
908 clocks = <&clks 126>;
909 status = "disabled";
910 };
911
912 i2c3: i2c@021a8000 {
913 #address-cells = <1>;
914 #size-cells = <0>;
915 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
916 reg = <0x021a8000 0x4000>;
917 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
918 clocks = <&clks 127>;
919 status = "disabled";
920 };
921
922 romcp@021ac000 {
923 reg = <0x021ac000 0x4000>;
924 };
925
926 mmdc0: mmdc@021b0000 { /* MMDC0 */
927 compatible = "fsl,imx6q-mmdc";
928 reg = <0x021b0000 0x4000>;
929 };
930
931 mmdc1: mmdc@021b4000 { /* MMDC1 */
932 reg = <0x021b4000 0x4000>;
933 };
934
935 weim: weim@021b8000 {
936 compatible = "fsl,imx6q-weim";
937 reg = <0x021b8000 0x4000>;
938 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
939 clocks = <&clks 196>;
940 };
941
942 ocotp: ocotp@021bc000 {
943 compatible = "fsl,imx6q-ocotp", "syscon";
944 reg = <0x021bc000 0x4000>;
945 };
946
947 tzasc@021d0000 { /* TZASC1 */
948 reg = <0x021d0000 0x4000>;
949 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
950 };
951
952 tzasc@021d4000 { /* TZASC2 */
953 reg = <0x021d4000 0x4000>;
954 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
955 };
956
957 audmux: audmux@021d8000 {
958 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
959 reg = <0x021d8000 0x4000>;
960 status = "disabled";
961 };
962
963 mipi_csi: mipi@021dc000 {
964 reg = <0x021dc000 0x4000>;
965 };
966
967 mipi_dsi: mipi@021e0000 {
968 #address-cells = <1>;
969 #size-cells = <0>;
970 reg = <0x021e0000 0x4000>;
971 status = "disabled";
972
973 port@0 {
974 reg = <0>;
975
976 mipi_mux_0: endpoint {
977 remote-endpoint = <&ipu1_di0_mipi>;
978 };
979 };
980
981 port@1 {
982 reg = <1>;
983
984 mipi_mux_1: endpoint {
985 remote-endpoint = <&ipu1_di1_mipi>;
986 };
987 };
988 };
989
990 vdoa@021e4000 {
991 reg = <0x021e4000 0x4000>;
992 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
993 };
994
995 uart2: serial@021e8000 {
996 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
997 reg = <0x021e8000 0x4000>;
998 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
999 clocks = <&clks 160>, <&clks 161>;
1000 clock-names = "ipg", "per";
1001 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1002 dma-names = "rx", "tx";
1003 status = "disabled";
1004 };
1005
1006 uart3: serial@021ec000 {
1007 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1008 reg = <0x021ec000 0x4000>;
1009 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1010 clocks = <&clks 160>, <&clks 161>;
1011 clock-names = "ipg", "per";
1012 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1013 dma-names = "rx", "tx";
1014 status = "disabled";
1015 };
1016
1017 uart4: serial@021f0000 {
1018 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1019 reg = <0x021f0000 0x4000>;
1020 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1021 clocks = <&clks 160>, <&clks 161>;
1022 clock-names = "ipg", "per";
1023 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1024 dma-names = "rx", "tx";
1025 status = "disabled";
1026 };
1027
1028 uart5: serial@021f4000 {
1029 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1030 reg = <0x021f4000 0x4000>;
1031 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1032 clocks = <&clks 160>, <&clks 161>;
1033 clock-names = "ipg", "per";
1034 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1035 dma-names = "rx", "tx";
1036 status = "disabled";
1037 };
1038 };
1039
1040 ipu1: ipu@02400000 {
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1043 compatible = "fsl,imx6q-ipu";
1044 reg = <0x02400000 0x400000>;
1045 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1046 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1047 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1048 clock-names = "bus", "di0", "di1";
1049 resets = <&src 2>;
1050
1051 ipu1_di0: port@2 {
1052 #address-cells = <1>;
1053 #size-cells = <0>;
1054 reg = <2>;
1055
1056 ipu1_di0_disp0: endpoint@0 {
1057 };
1058
1059 ipu1_di0_hdmi: endpoint@1 {
1060 remote-endpoint = <&hdmi_mux_0>;
1061 };
1062
1063 ipu1_di0_mipi: endpoint@2 {
1064 remote-endpoint = <&mipi_mux_0>;
1065 };
1066
1067 ipu1_di0_lvds0: endpoint@3 {
1068 remote-endpoint = <&lvds0_mux_0>;
1069 };
1070
1071 ipu1_di0_lvds1: endpoint@4 {
1072 remote-endpoint = <&lvds1_mux_0>;
1073 };
1074 };
1075
1076 ipu1_di1: port@3 {
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1079 reg = <3>;
1080
1081 ipu1_di0_disp1: endpoint@0 {
1082 };
1083
1084 ipu1_di1_hdmi: endpoint@1 {
1085 remote-endpoint = <&hdmi_mux_1>;
1086 };
1087
1088 ipu1_di1_mipi: endpoint@2 {
1089 remote-endpoint = <&mipi_mux_1>;
1090 };
1091
1092 ipu1_di1_lvds0: endpoint@3 {
1093 remote-endpoint = <&lvds0_mux_1>;
1094 };
1095
1096 ipu1_di1_lvds1: endpoint@4 {
1097 remote-endpoint = <&lvds1_mux_1>;
1098 };
1099 };
1100 };
1101 };
1102};