tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
41#include <linux/dma-mapping.h>
42#include <linux/device.h>
43#include <linux/dmi.h>
44#include <linux/gfp.h>
45#include <scsi/scsi_host.h>
46#include <scsi/scsi_cmnd.h>
47#include <linux/libata.h>
48#include "ahci.h"
49
50#define DRV_NAME "ahci"
51#define DRV_VERSION "3.0"
52
53enum {
54 AHCI_PCI_BAR_STA2X11 = 0,
55 AHCI_PCI_BAR_ENMOTUS = 2,
56 AHCI_PCI_BAR_STANDARD = 5,
57};
58
59enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
63 board_ahci_noncq,
64 board_ahci_nosntf,
65 board_ahci_yes_fbs,
66
67 /* board IDs for specific chipsets in alphabetical order */
68 board_ahci_mcp65,
69 board_ahci_mcp77,
70 board_ahci_mcp89,
71 board_ahci_mv,
72 board_ahci_sb600,
73 board_ahci_sb700, /* for SB700 and SB800 */
74 board_ahci_vt8251,
75
76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
80 board_ahci_mcp79 = board_ahci_mcp77,
81};
82
83static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
84static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
87static bool is_mcp89_apple(struct pci_dev *pdev);
88static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90#ifdef CONFIG_PM
91static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
92static int ahci_pci_device_resume(struct pci_dev *pdev);
93#endif
94
95static struct scsi_host_template ahci_sht = {
96 AHCI_SHT("ahci"),
97};
98
99static struct ata_port_operations ahci_vt8251_ops = {
100 .inherits = &ahci_ops,
101 .hardreset = ahci_vt8251_hardreset,
102};
103
104static struct ata_port_operations ahci_p5wdh_ops = {
105 .inherits = &ahci_ops,
106 .hardreset = ahci_p5wdh_hardreset,
107};
108
109static const struct ata_port_info ahci_port_info[] = {
110 /* by features */
111 [board_ahci] = {
112 .flags = AHCI_FLAG_COMMON,
113 .pio_mask = ATA_PIO4,
114 .udma_mask = ATA_UDMA6,
115 .port_ops = &ahci_ops,
116 },
117 [board_ahci_ign_iferr] = {
118 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
119 .flags = AHCI_FLAG_COMMON,
120 .pio_mask = ATA_PIO4,
121 .udma_mask = ATA_UDMA6,
122 .port_ops = &ahci_ops,
123 },
124 [board_ahci_noncq] = {
125 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
126 .flags = AHCI_FLAG_COMMON,
127 .pio_mask = ATA_PIO4,
128 .udma_mask = ATA_UDMA6,
129 .port_ops = &ahci_ops,
130 },
131 [board_ahci_nosntf] = {
132 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
133 .flags = AHCI_FLAG_COMMON,
134 .pio_mask = ATA_PIO4,
135 .udma_mask = ATA_UDMA6,
136 .port_ops = &ahci_ops,
137 },
138 [board_ahci_yes_fbs] = {
139 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
140 .flags = AHCI_FLAG_COMMON,
141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
144 },
145 /* by chipsets */
146 [board_ahci_mcp65] = {
147 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
148 AHCI_HFLAG_YES_NCQ),
149 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
150 .pio_mask = ATA_PIO4,
151 .udma_mask = ATA_UDMA6,
152 .port_ops = &ahci_ops,
153 },
154 [board_ahci_mcp77] = {
155 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
156 .flags = AHCI_FLAG_COMMON,
157 .pio_mask = ATA_PIO4,
158 .udma_mask = ATA_UDMA6,
159 .port_ops = &ahci_ops,
160 },
161 [board_ahci_mcp89] = {
162 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
163 .flags = AHCI_FLAG_COMMON,
164 .pio_mask = ATA_PIO4,
165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_ops,
167 },
168 [board_ahci_mv] = {
169 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
170 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
171 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
172 .pio_mask = ATA_PIO4,
173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_ops,
175 },
176 [board_ahci_sb600] = {
177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
178 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
179 AHCI_HFLAG_32BIT_ONLY),
180 .flags = AHCI_FLAG_COMMON,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_pmp_retry_srst_ops,
184 },
185 [board_ahci_sb700] = { /* for SB700 and SB800 */
186 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_pmp_retry_srst_ops,
191 },
192 [board_ahci_vt8251] = {
193 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
194 .flags = AHCI_FLAG_COMMON,
195 .pio_mask = ATA_PIO4,
196 .udma_mask = ATA_UDMA6,
197 .port_ops = &ahci_vt8251_ops,
198 },
199};
200
201static const struct pci_device_id ahci_pci_tbl[] = {
202 /* Intel */
203 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
204 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
205 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
206 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
207 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
208 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
209 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
210 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
211 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
212 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
213 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
214 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
215 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
216 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
217 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
218 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
219 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
224 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
225 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
230 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
231 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
232 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
233 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
234 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
235 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
236 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
237 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
238 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
239 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
240 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
241 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
242 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
243 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
244 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
245 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
246 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
247 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
249 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
250 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
251 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
252 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
253 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
254 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
255 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
256 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
257 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
258 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
260 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
261 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
262 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
263 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
264 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
266 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
267 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
269 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
270 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
271 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
272 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
273 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
274 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
275 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
276 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
277 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
278 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
279 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
280 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
285 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
286 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
287 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
293 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
294 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
295 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
296 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
297 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
298 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
299 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
300 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
301 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
302 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
303 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
304 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
305 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
306 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
307 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
308
309 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
310 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
311 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
312 /* JMicron 362B and 362C have an AHCI function with IDE class code */
313 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
314 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
315
316 /* ATI */
317 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
318 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
319 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
320 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
321 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
322 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
323 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
324
325 /* AMD */
326 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
327 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
328 /* AMD is using RAID class only for ahci controllers */
329 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
330 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
331
332 /* VIA */
333 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
334 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
335
336 /* NVIDIA */
337 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
338 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
339 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
340 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
341 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
342 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
343 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
344 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
345 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
346 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
347 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
348 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
349 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
350 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
351 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
352 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
353 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
354 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
355 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
356 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
357 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
358 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
359 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
360 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
361 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
362 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
363 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
364 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
365 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
366 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
367 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
368 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
369 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
370 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
371 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
372 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
373 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
374 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
375 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
376 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
377 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
378 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
379 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
380 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
381 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
382 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
383 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
384 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
385 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
386 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
387 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
388 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
389 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
390 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
391 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
392 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
393 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
394 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
395 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
396 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
397 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
398 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
399 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
400 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
401 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
402 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
403 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
404 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
405 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
406 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
407 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
408 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
409 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
410 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
411 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
412 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
413 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
414 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
415 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
416 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
417 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
418 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
419 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
420 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
421
422 /* SiS */
423 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
424 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
425 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
426
427 /* ST Microelectronics */
428 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
429
430 /* Marvell */
431 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
432 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
433 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
434 .class = PCI_CLASS_STORAGE_SATA_AHCI,
435 .class_mask = 0xffffff,
436 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
437 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
438 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
439 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
440 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
441 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
442 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
443 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
444 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
445 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
446 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
447 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
448 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
449 .driver_data = board_ahci_yes_fbs },
450 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
451 .driver_data = board_ahci_yes_fbs },
452 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
453 .driver_data = board_ahci_yes_fbs },
454 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
455 .driver_data = board_ahci_yes_fbs },
456
457 /* Promise */
458 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
459 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
460
461 /* Asmedia */
462 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
463 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
464 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
465 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
466
467 /*
468 * Samsung SSDs found on some macbooks. NCQ times out.
469 * https://bugzilla.kernel.org/show_bug.cgi?id=60731
470 */
471 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_noncq },
472
473 /* Enmotus */
474 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
475
476 /* Generic, PCI class code for AHCI */
477 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
478 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
479
480 { } /* terminate list */
481};
482
483
484static struct pci_driver ahci_pci_driver = {
485 .name = DRV_NAME,
486 .id_table = ahci_pci_tbl,
487 .probe = ahci_init_one,
488 .remove = ata_pci_remove_one,
489#ifdef CONFIG_PM
490 .suspend = ahci_pci_device_suspend,
491 .resume = ahci_pci_device_resume,
492#endif
493};
494
495#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
496static int marvell_enable;
497#else
498static int marvell_enable = 1;
499#endif
500module_param(marvell_enable, int, 0644);
501MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
502
503
504static void ahci_pci_save_initial_config(struct pci_dev *pdev,
505 struct ahci_host_priv *hpriv)
506{
507 unsigned int force_port_map = 0;
508 unsigned int mask_port_map = 0;
509
510 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
511 dev_info(&pdev->dev, "JMB361 has only one port\n");
512 force_port_map = 1;
513 }
514
515 /*
516 * Temporary Marvell 6145 hack: PATA port presence
517 * is asserted through the standard AHCI port
518 * presence register, as bit 4 (counting from 0)
519 */
520 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
521 if (pdev->device == 0x6121)
522 mask_port_map = 0x3;
523 else
524 mask_port_map = 0xf;
525 dev_info(&pdev->dev,
526 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
527 }
528
529 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
530 mask_port_map);
531}
532
533static int ahci_pci_reset_controller(struct ata_host *host)
534{
535 struct pci_dev *pdev = to_pci_dev(host->dev);
536
537 ahci_reset_controller(host);
538
539 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
540 struct ahci_host_priv *hpriv = host->private_data;
541 u16 tmp16;
542
543 /* configure PCS */
544 pci_read_config_word(pdev, 0x92, &tmp16);
545 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
546 tmp16 |= hpriv->port_map;
547 pci_write_config_word(pdev, 0x92, tmp16);
548 }
549 }
550
551 return 0;
552}
553
554static void ahci_pci_init_controller(struct ata_host *host)
555{
556 struct ahci_host_priv *hpriv = host->private_data;
557 struct pci_dev *pdev = to_pci_dev(host->dev);
558 void __iomem *port_mmio;
559 u32 tmp;
560 int mv;
561
562 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
563 if (pdev->device == 0x6121)
564 mv = 2;
565 else
566 mv = 4;
567 port_mmio = __ahci_port_base(host, mv);
568
569 writel(0, port_mmio + PORT_IRQ_MASK);
570
571 /* clear port IRQ */
572 tmp = readl(port_mmio + PORT_IRQ_STAT);
573 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
574 if (tmp)
575 writel(tmp, port_mmio + PORT_IRQ_STAT);
576 }
577
578 ahci_init_controller(host);
579}
580
581static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
582 unsigned long deadline)
583{
584 struct ata_port *ap = link->ap;
585 struct ahci_host_priv *hpriv = ap->host->private_data;
586 bool online;
587 int rc;
588
589 DPRINTK("ENTER\n");
590
591 ahci_stop_engine(ap);
592
593 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
594 deadline, &online, NULL);
595
596 hpriv->start_engine(ap);
597
598 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
599
600 /* vt8251 doesn't clear BSY on signature FIS reception,
601 * request follow-up softreset.
602 */
603 return online ? -EAGAIN : rc;
604}
605
606static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
607 unsigned long deadline)
608{
609 struct ata_port *ap = link->ap;
610 struct ahci_port_priv *pp = ap->private_data;
611 struct ahci_host_priv *hpriv = ap->host->private_data;
612 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
613 struct ata_taskfile tf;
614 bool online;
615 int rc;
616
617 ahci_stop_engine(ap);
618
619 /* clear D2H reception area to properly wait for D2H FIS */
620 ata_tf_init(link->device, &tf);
621 tf.command = ATA_BUSY;
622 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
623
624 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
625 deadline, &online, NULL);
626
627 hpriv->start_engine(ap);
628
629 /* The pseudo configuration device on SIMG4726 attached to
630 * ASUS P5W-DH Deluxe doesn't send signature FIS after
631 * hardreset if no device is attached to the first downstream
632 * port && the pseudo device locks up on SRST w/ PMP==0. To
633 * work around this, wait for !BSY only briefly. If BSY isn't
634 * cleared, perform CLO and proceed to IDENTIFY (achieved by
635 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
636 *
637 * Wait for two seconds. Devices attached to downstream port
638 * which can't process the following IDENTIFY after this will
639 * have to be reset again. For most cases, this should
640 * suffice while making probing snappish enough.
641 */
642 if (online) {
643 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
644 ahci_check_ready);
645 if (rc)
646 ahci_kick_engine(ap);
647 }
648 return rc;
649}
650
651#ifdef CONFIG_PM
652static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
653{
654 struct ata_host *host = pci_get_drvdata(pdev);
655 struct ahci_host_priv *hpriv = host->private_data;
656 void __iomem *mmio = hpriv->mmio;
657 u32 ctl;
658
659 if (mesg.event & PM_EVENT_SUSPEND &&
660 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
661 dev_err(&pdev->dev,
662 "BIOS update required for suspend/resume\n");
663 return -EIO;
664 }
665
666 if (mesg.event & PM_EVENT_SLEEP) {
667 /* AHCI spec rev1.1 section 8.3.3:
668 * Software must disable interrupts prior to requesting a
669 * transition of the HBA to D3 state.
670 */
671 ctl = readl(mmio + HOST_CTL);
672 ctl &= ~HOST_IRQ_EN;
673 writel(ctl, mmio + HOST_CTL);
674 readl(mmio + HOST_CTL); /* flush */
675 }
676
677 return ata_pci_device_suspend(pdev, mesg);
678}
679
680static int ahci_pci_device_resume(struct pci_dev *pdev)
681{
682 struct ata_host *host = pci_get_drvdata(pdev);
683 int rc;
684
685 rc = ata_pci_device_do_resume(pdev);
686 if (rc)
687 return rc;
688
689 /* Apple BIOS helpfully mangles the registers on resume */
690 if (is_mcp89_apple(pdev))
691 ahci_mcp89_apple_enable(pdev);
692
693 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
694 rc = ahci_pci_reset_controller(host);
695 if (rc)
696 return rc;
697
698 ahci_pci_init_controller(host);
699 }
700
701 ata_host_resume(host);
702
703 return 0;
704}
705#endif
706
707static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
708{
709 int rc;
710
711 /*
712 * If the device fixup already set the dma_mask to some non-standard
713 * value, don't extend it here. This happens on STA2X11, for example.
714 */
715 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
716 return 0;
717
718 if (using_dac &&
719 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
720 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
721 if (rc) {
722 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
723 if (rc) {
724 dev_err(&pdev->dev,
725 "64-bit DMA enable failed\n");
726 return rc;
727 }
728 }
729 } else {
730 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
731 if (rc) {
732 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
733 return rc;
734 }
735 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
736 if (rc) {
737 dev_err(&pdev->dev,
738 "32-bit consistent DMA enable failed\n");
739 return rc;
740 }
741 }
742 return 0;
743}
744
745static void ahci_pci_print_info(struct ata_host *host)
746{
747 struct pci_dev *pdev = to_pci_dev(host->dev);
748 u16 cc;
749 const char *scc_s;
750
751 pci_read_config_word(pdev, 0x0a, &cc);
752 if (cc == PCI_CLASS_STORAGE_IDE)
753 scc_s = "IDE";
754 else if (cc == PCI_CLASS_STORAGE_SATA)
755 scc_s = "SATA";
756 else if (cc == PCI_CLASS_STORAGE_RAID)
757 scc_s = "RAID";
758 else
759 scc_s = "unknown";
760
761 ahci_print_info(host, scc_s);
762}
763
764/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
765 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
766 * support PMP and the 4726 either directly exports the device
767 * attached to the first downstream port or acts as a hardware storage
768 * controller and emulate a single ATA device (can be RAID 0/1 or some
769 * other configuration).
770 *
771 * When there's no device attached to the first downstream port of the
772 * 4726, "Config Disk" appears, which is a pseudo ATA device to
773 * configure the 4726. However, ATA emulation of the device is very
774 * lame. It doesn't send signature D2H Reg FIS after the initial
775 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
776 *
777 * The following function works around the problem by always using
778 * hardreset on the port and not depending on receiving signature FIS
779 * afterward. If signature FIS isn't received soon, ATA class is
780 * assumed without follow-up softreset.
781 */
782static void ahci_p5wdh_workaround(struct ata_host *host)
783{
784 static struct dmi_system_id sysids[] = {
785 {
786 .ident = "P5W DH Deluxe",
787 .matches = {
788 DMI_MATCH(DMI_SYS_VENDOR,
789 "ASUSTEK COMPUTER INC"),
790 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
791 },
792 },
793 { }
794 };
795 struct pci_dev *pdev = to_pci_dev(host->dev);
796
797 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
798 dmi_check_system(sysids)) {
799 struct ata_port *ap = host->ports[1];
800
801 dev_info(&pdev->dev,
802 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
803
804 ap->ops = &ahci_p5wdh_ops;
805 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
806 }
807}
808
809/*
810 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
811 * booting in BIOS compatibility mode. We restore the registers but not ID.
812 */
813static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
814{
815 u32 val;
816
817 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
818
819 pci_read_config_dword(pdev, 0xf8, &val);
820 val |= 1 << 0x1b;
821 /* the following changes the device ID, but appears not to affect function */
822 /* val = (val & ~0xf0000000) | 0x80000000; */
823 pci_write_config_dword(pdev, 0xf8, val);
824
825 pci_read_config_dword(pdev, 0x54c, &val);
826 val |= 1 << 0xc;
827 pci_write_config_dword(pdev, 0x54c, val);
828
829 pci_read_config_dword(pdev, 0x4a4, &val);
830 val &= 0xff;
831 val |= 0x01060100;
832 pci_write_config_dword(pdev, 0x4a4, val);
833
834 pci_read_config_dword(pdev, 0x54c, &val);
835 val &= ~(1 << 0xc);
836 pci_write_config_dword(pdev, 0x54c, val);
837
838 pci_read_config_dword(pdev, 0xf8, &val);
839 val &= ~(1 << 0x1b);
840 pci_write_config_dword(pdev, 0xf8, val);
841}
842
843static bool is_mcp89_apple(struct pci_dev *pdev)
844{
845 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
846 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
847 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
848 pdev->subsystem_device == 0xcb89;
849}
850
851/* only some SB600 ahci controllers can do 64bit DMA */
852static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
853{
854 static const struct dmi_system_id sysids[] = {
855 /*
856 * The oldest version known to be broken is 0901 and
857 * working is 1501 which was released on 2007-10-26.
858 * Enable 64bit DMA on 1501 and anything newer.
859 *
860 * Please read bko#9412 for more info.
861 */
862 {
863 .ident = "ASUS M2A-VM",
864 .matches = {
865 DMI_MATCH(DMI_BOARD_VENDOR,
866 "ASUSTeK Computer INC."),
867 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
868 },
869 .driver_data = "20071026", /* yyyymmdd */
870 },
871 /*
872 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
873 * support 64bit DMA.
874 *
875 * BIOS versions earlier than 1.5 had the Manufacturer DMI
876 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
877 * This spelling mistake was fixed in BIOS version 1.5, so
878 * 1.5 and later have the Manufacturer as
879 * "MICRO-STAR INTERNATIONAL CO.,LTD".
880 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
881 *
882 * BIOS versions earlier than 1.9 had a Board Product Name
883 * DMI field of "MS-7376". This was changed to be
884 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
885 * match on DMI_BOARD_NAME of "MS-7376".
886 */
887 {
888 .ident = "MSI K9A2 Platinum",
889 .matches = {
890 DMI_MATCH(DMI_BOARD_VENDOR,
891 "MICRO-STAR INTER"),
892 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
893 },
894 },
895 /*
896 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
897 * 64bit DMA.
898 *
899 * This board also had the typo mentioned above in the
900 * Manufacturer DMI field (fixed in BIOS version 1.5), so
901 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
902 */
903 {
904 .ident = "MSI K9AGM2",
905 .matches = {
906 DMI_MATCH(DMI_BOARD_VENDOR,
907 "MICRO-STAR INTER"),
908 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
909 },
910 },
911 /*
912 * All BIOS versions for the Asus M3A support 64bit DMA.
913 * (all release versions from 0301 to 1206 were tested)
914 */
915 {
916 .ident = "ASUS M3A",
917 .matches = {
918 DMI_MATCH(DMI_BOARD_VENDOR,
919 "ASUSTeK Computer INC."),
920 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
921 },
922 },
923 { }
924 };
925 const struct dmi_system_id *match;
926 int year, month, date;
927 char buf[9];
928
929 match = dmi_first_match(sysids);
930 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
931 !match)
932 return false;
933
934 if (!match->driver_data)
935 goto enable_64bit;
936
937 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
938 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
939
940 if (strcmp(buf, match->driver_data) >= 0)
941 goto enable_64bit;
942 else {
943 dev_warn(&pdev->dev,
944 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
945 match->ident);
946 return false;
947 }
948
949enable_64bit:
950 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
951 return true;
952}
953
954static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
955{
956 static const struct dmi_system_id broken_systems[] = {
957 {
958 .ident = "HP Compaq nx6310",
959 .matches = {
960 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
961 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
962 },
963 /* PCI slot number of the controller */
964 .driver_data = (void *)0x1FUL,
965 },
966 {
967 .ident = "HP Compaq 6720s",
968 .matches = {
969 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
970 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
971 },
972 /* PCI slot number of the controller */
973 .driver_data = (void *)0x1FUL,
974 },
975
976 { } /* terminate list */
977 };
978 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
979
980 if (dmi) {
981 unsigned long slot = (unsigned long)dmi->driver_data;
982 /* apply the quirk only to on-board controllers */
983 return slot == PCI_SLOT(pdev->devfn);
984 }
985
986 return false;
987}
988
989static bool ahci_broken_suspend(struct pci_dev *pdev)
990{
991 static const struct dmi_system_id sysids[] = {
992 /*
993 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
994 * to the harddisk doesn't become online after
995 * resuming from STR. Warn and fail suspend.
996 *
997 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
998 *
999 * Use dates instead of versions to match as HP is
1000 * apparently recycling both product and version
1001 * strings.
1002 *
1003 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1004 */
1005 {
1006 .ident = "dv4",
1007 .matches = {
1008 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1009 DMI_MATCH(DMI_PRODUCT_NAME,
1010 "HP Pavilion dv4 Notebook PC"),
1011 },
1012 .driver_data = "20090105", /* F.30 */
1013 },
1014 {
1015 .ident = "dv5",
1016 .matches = {
1017 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1018 DMI_MATCH(DMI_PRODUCT_NAME,
1019 "HP Pavilion dv5 Notebook PC"),
1020 },
1021 .driver_data = "20090506", /* F.16 */
1022 },
1023 {
1024 .ident = "dv6",
1025 .matches = {
1026 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1027 DMI_MATCH(DMI_PRODUCT_NAME,
1028 "HP Pavilion dv6 Notebook PC"),
1029 },
1030 .driver_data = "20090423", /* F.21 */
1031 },
1032 {
1033 .ident = "HDX18",
1034 .matches = {
1035 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1036 DMI_MATCH(DMI_PRODUCT_NAME,
1037 "HP HDX18 Notebook PC"),
1038 },
1039 .driver_data = "20090430", /* F.23 */
1040 },
1041 /*
1042 * Acer eMachines G725 has the same problem. BIOS
1043 * V1.03 is known to be broken. V3.04 is known to
1044 * work. Between, there are V1.06, V2.06 and V3.03
1045 * that we don't have much idea about. For now,
1046 * blacklist anything older than V3.04.
1047 *
1048 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1049 */
1050 {
1051 .ident = "G725",
1052 .matches = {
1053 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1054 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1055 },
1056 .driver_data = "20091216", /* V3.04 */
1057 },
1058 { } /* terminate list */
1059 };
1060 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1061 int year, month, date;
1062 char buf[9];
1063
1064 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1065 return false;
1066
1067 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1068 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1069
1070 return strcmp(buf, dmi->driver_data) < 0;
1071}
1072
1073static bool ahci_broken_online(struct pci_dev *pdev)
1074{
1075#define ENCODE_BUSDEVFN(bus, slot, func) \
1076 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1077 static const struct dmi_system_id sysids[] = {
1078 /*
1079 * There are several gigabyte boards which use
1080 * SIMG5723s configured as hardware RAID. Certain
1081 * 5723 firmware revisions shipped there keep the link
1082 * online but fail to answer properly to SRST or
1083 * IDENTIFY when no device is attached downstream
1084 * causing libata to retry quite a few times leading
1085 * to excessive detection delay.
1086 *
1087 * As these firmwares respond to the second reset try
1088 * with invalid device signature, considering unknown
1089 * sig as offline works around the problem acceptably.
1090 */
1091 {
1092 .ident = "EP45-DQ6",
1093 .matches = {
1094 DMI_MATCH(DMI_BOARD_VENDOR,
1095 "Gigabyte Technology Co., Ltd."),
1096 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1097 },
1098 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1099 },
1100 {
1101 .ident = "EP45-DS5",
1102 .matches = {
1103 DMI_MATCH(DMI_BOARD_VENDOR,
1104 "Gigabyte Technology Co., Ltd."),
1105 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1106 },
1107 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1108 },
1109 { } /* terminate list */
1110 };
1111#undef ENCODE_BUSDEVFN
1112 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1113 unsigned int val;
1114
1115 if (!dmi)
1116 return false;
1117
1118 val = (unsigned long)dmi->driver_data;
1119
1120 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1121}
1122
1123static bool ahci_broken_devslp(struct pci_dev *pdev)
1124{
1125 /* device with broken DEVSLP but still showing SDS capability */
1126 static const struct pci_device_id ids[] = {
1127 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1128 {}
1129 };
1130
1131 return pci_match_id(ids, pdev);
1132}
1133
1134#ifdef CONFIG_ATA_ACPI
1135static void ahci_gtf_filter_workaround(struct ata_host *host)
1136{
1137 static const struct dmi_system_id sysids[] = {
1138 /*
1139 * Aspire 3810T issues a bunch of SATA enable commands
1140 * via _GTF including an invalid one and one which is
1141 * rejected by the device. Among the successful ones
1142 * is FPDMA non-zero offset enable which when enabled
1143 * only on the drive side leads to NCQ command
1144 * failures. Filter it out.
1145 */
1146 {
1147 .ident = "Aspire 3810T",
1148 .matches = {
1149 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1150 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1151 },
1152 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1153 },
1154 { }
1155 };
1156 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1157 unsigned int filter;
1158 int i;
1159
1160 if (!dmi)
1161 return;
1162
1163 filter = (unsigned long)dmi->driver_data;
1164 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1165 filter, dmi->ident);
1166
1167 for (i = 0; i < host->n_ports; i++) {
1168 struct ata_port *ap = host->ports[i];
1169 struct ata_link *link;
1170 struct ata_device *dev;
1171
1172 ata_for_each_link(link, ap, EDGE)
1173 ata_for_each_dev(dev, link, ALL)
1174 dev->gtf_filter |= filter;
1175 }
1176}
1177#else
1178static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1179{}
1180#endif
1181
1182static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
1183 struct ahci_host_priv *hpriv)
1184{
1185 int rc, nvec;
1186
1187 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1188 goto intx;
1189
1190 nvec = pci_msi_vec_count(pdev);
1191 if (nvec < 0)
1192 goto intx;
1193
1194 /*
1195 * If number of MSIs is less than number of ports then Sharing Last
1196 * Message mode could be enforced. In this case assume that advantage
1197 * of multipe MSIs is negated and use single MSI mode instead.
1198 */
1199 if (nvec < n_ports)
1200 goto single_msi;
1201
1202 rc = pci_enable_msi_exact(pdev, nvec);
1203 if (rc == -ENOSPC)
1204 goto single_msi;
1205 else if (rc < 0)
1206 goto intx;
1207
1208 /* fallback to single MSI mode if the controller enforced MRSM mode */
1209 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1210 pci_disable_msi(pdev);
1211 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1212 goto single_msi;
1213 }
1214
1215 return nvec;
1216
1217single_msi:
1218 if (pci_enable_msi(pdev))
1219 goto intx;
1220 return 1;
1221
1222intx:
1223 pci_intx(pdev, 1);
1224 return 0;
1225}
1226
1227/**
1228 * ahci_host_activate - start AHCI host, request IRQs and register it
1229 * @host: target ATA host
1230 * @irq: base IRQ number to request
1231 * @n_msis: number of MSIs allocated for this host
1232 * @irq_handler: irq_handler used when requesting IRQs
1233 * @irq_flags: irq_flags used when requesting IRQs
1234 *
1235 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1236 * when multiple MSIs were allocated. That is one MSI per port, starting
1237 * from @irq.
1238 *
1239 * LOCKING:
1240 * Inherited from calling layer (may sleep).
1241 *
1242 * RETURNS:
1243 * 0 on success, -errno otherwise.
1244 */
1245int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1246{
1247 int i, rc;
1248
1249 /* Sharing Last Message among several ports is not supported */
1250 if (n_msis < host->n_ports)
1251 return -EINVAL;
1252
1253 rc = ata_host_start(host);
1254 if (rc)
1255 return rc;
1256
1257 for (i = 0; i < host->n_ports; i++) {
1258 struct ahci_port_priv *pp = host->ports[i]->private_data;
1259
1260 /* Do not receive interrupts sent by dummy ports */
1261 if (!pp) {
1262 disable_irq(irq + i);
1263 continue;
1264 }
1265
1266 rc = devm_request_threaded_irq(host->dev, irq + i,
1267 ahci_hw_interrupt,
1268 ahci_thread_fn, IRQF_SHARED,
1269 pp->irq_desc, host->ports[i]);
1270 if (rc)
1271 goto out_free_irqs;
1272 }
1273
1274 for (i = 0; i < host->n_ports; i++)
1275 ata_port_desc(host->ports[i], "irq %d", irq + i);
1276
1277 rc = ata_host_register(host, &ahci_sht);
1278 if (rc)
1279 goto out_free_all_irqs;
1280
1281 return 0;
1282
1283out_free_all_irqs:
1284 i = host->n_ports;
1285out_free_irqs:
1286 for (i--; i >= 0; i--)
1287 devm_free_irq(host->dev, irq + i, host->ports[i]);
1288
1289 return rc;
1290}
1291
1292static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1293{
1294 unsigned int board_id = ent->driver_data;
1295 struct ata_port_info pi = ahci_port_info[board_id];
1296 const struct ata_port_info *ppi[] = { &pi, NULL };
1297 struct device *dev = &pdev->dev;
1298 struct ahci_host_priv *hpriv;
1299 struct ata_host *host;
1300 int n_ports, n_msis, i, rc;
1301 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1302
1303 VPRINTK("ENTER\n");
1304
1305 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1306
1307 ata_print_version_once(&pdev->dev, DRV_VERSION);
1308
1309 /* The AHCI driver can only drive the SATA ports, the PATA driver
1310 can drive them all so if both drivers are selected make sure
1311 AHCI stays out of the way */
1312 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1313 return -ENODEV;
1314
1315 /* Apple BIOS on MCP89 prevents us using AHCI */
1316 if (is_mcp89_apple(pdev))
1317 ahci_mcp89_apple_enable(pdev);
1318
1319 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1320 * At the moment, we can only use the AHCI mode. Let the users know
1321 * that for SAS drives they're out of luck.
1322 */
1323 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1324 dev_info(&pdev->dev,
1325 "PDC42819 can only drive SATA devices with this driver\n");
1326
1327 /* Both Connext and Enmotus devices use non-standard BARs */
1328 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1329 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1330 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1331 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1332
1333 /* acquire resources */
1334 rc = pcim_enable_device(pdev);
1335 if (rc)
1336 return rc;
1337
1338 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1339 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1340 u8 map;
1341
1342 /* ICH6s share the same PCI ID for both piix and ahci
1343 * modes. Enabling ahci mode while MAP indicates
1344 * combined mode is a bad idea. Yield to ata_piix.
1345 */
1346 pci_read_config_byte(pdev, ICH_MAP, &map);
1347 if (map & 0x3) {
1348 dev_info(&pdev->dev,
1349 "controller is in combined mode, can't enable AHCI mode\n");
1350 return -ENODEV;
1351 }
1352 }
1353
1354 /* AHCI controllers often implement SFF compatible interface.
1355 * Grab all PCI BARs just in case.
1356 */
1357 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1358 if (rc == -EBUSY)
1359 pcim_pin_device(pdev);
1360 if (rc)
1361 return rc;
1362
1363 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1364 if (!hpriv)
1365 return -ENOMEM;
1366 hpriv->flags |= (unsigned long)pi.private_data;
1367
1368 /* MCP65 revision A1 and A2 can't do MSI */
1369 if (board_id == board_ahci_mcp65 &&
1370 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1371 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1372
1373 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1374 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1375 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1376
1377 /* only some SB600s can do 64bit DMA */
1378 if (ahci_sb600_enable_64bit(pdev))
1379 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1380
1381 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1382
1383 /* must set flag prior to save config in order to take effect */
1384 if (ahci_broken_devslp(pdev))
1385 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1386
1387 /* save initial config */
1388 ahci_pci_save_initial_config(pdev, hpriv);
1389
1390 /* prepare host */
1391 if (hpriv->cap & HOST_CAP_NCQ) {
1392 pi.flags |= ATA_FLAG_NCQ;
1393 /*
1394 * Auto-activate optimization is supposed to be
1395 * supported on all AHCI controllers indicating NCQ
1396 * capability, but it seems to be broken on some
1397 * chipsets including NVIDIAs.
1398 */
1399 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1400 pi.flags |= ATA_FLAG_FPDMA_AA;
1401
1402 /*
1403 * All AHCI controllers should be forward-compatible
1404 * with the new auxiliary field. This code should be
1405 * conditionalized if any buggy AHCI controllers are
1406 * encountered.
1407 */
1408 pi.flags |= ATA_FLAG_FPDMA_AUX;
1409 }
1410
1411 if (hpriv->cap & HOST_CAP_PMP)
1412 pi.flags |= ATA_FLAG_PMP;
1413
1414 ahci_set_em_messages(hpriv, &pi);
1415
1416 if (ahci_broken_system_poweroff(pdev)) {
1417 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1418 dev_info(&pdev->dev,
1419 "quirky BIOS, skipping spindown on poweroff\n");
1420 }
1421
1422 if (ahci_broken_suspend(pdev)) {
1423 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1424 dev_warn(&pdev->dev,
1425 "BIOS update required for suspend/resume\n");
1426 }
1427
1428 if (ahci_broken_online(pdev)) {
1429 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1430 dev_info(&pdev->dev,
1431 "online status unreliable, applying workaround\n");
1432 }
1433
1434 /* CAP.NP sometimes indicate the index of the last enabled
1435 * port, at other times, that of the last possible port, so
1436 * determining the maximum port number requires looking at
1437 * both CAP.NP and port_map.
1438 */
1439 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1440
1441 n_msis = ahci_init_interrupts(pdev, n_ports, hpriv);
1442 if (n_msis > 1)
1443 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1444
1445 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1446 if (!host)
1447 return -ENOMEM;
1448 host->private_data = hpriv;
1449
1450 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1451 host->flags |= ATA_HOST_PARALLEL_SCAN;
1452 else
1453 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1454
1455 if (pi.flags & ATA_FLAG_EM)
1456 ahci_reset_em(host);
1457
1458 for (i = 0; i < host->n_ports; i++) {
1459 struct ata_port *ap = host->ports[i];
1460
1461 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1462 ata_port_pbar_desc(ap, ahci_pci_bar,
1463 0x100 + ap->port_no * 0x80, "port");
1464
1465 /* set enclosure management message type */
1466 if (ap->flags & ATA_FLAG_EM)
1467 ap->em_message_type = hpriv->em_msg_type;
1468
1469
1470 /* disabled/not-implemented port */
1471 if (!(hpriv->port_map & (1 << i)))
1472 ap->ops = &ata_dummy_port_ops;
1473 }
1474
1475 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1476 ahci_p5wdh_workaround(host);
1477
1478 /* apply gtf filter quirk */
1479 ahci_gtf_filter_workaround(host);
1480
1481 /* initialize adapter */
1482 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1483 if (rc)
1484 return rc;
1485
1486 rc = ahci_pci_reset_controller(host);
1487 if (rc)
1488 return rc;
1489
1490 ahci_pci_init_controller(host);
1491 ahci_pci_print_info(host);
1492
1493 pci_set_master(pdev);
1494
1495 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1496 return ahci_host_activate(host, pdev->irq, n_msis);
1497
1498 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1499 &ahci_sht);
1500}
1501
1502module_pci_driver(ahci_pci_driver);
1503
1504MODULE_AUTHOR("Jeff Garzik");
1505MODULE_DESCRIPTION("AHCI SATA low-level driver");
1506MODULE_LICENSE("GPL");
1507MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1508MODULE_VERSION(DRV_VERSION);