tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) 2010 Google, Inc.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15#include <linux/err.h>
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/clk.h>
20#include <linux/io.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/of_gpio.h>
24#include <linux/gpio.h>
25#include <linux/mmc/card.h>
26#include <linux/mmc/host.h>
27#include <linux/mmc/slot-gpio.h>
28
29#include <asm/gpio.h>
30
31#include "sdhci-pltfm.h"
32
33/* Tegra SDHOST controller vendor register definitions */
34#define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120
35#define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8
36#define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10
37#define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20
38#define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200
39
40#define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0)
41#define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1)
42#define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2)
43#define NVQUIRK_DISABLE_SDR50 BIT(3)
44#define NVQUIRK_DISABLE_SDR104 BIT(4)
45#define NVQUIRK_DISABLE_DDR50 BIT(5)
46
47struct sdhci_tegra_soc_data {
48 const struct sdhci_pltfm_data *pdata;
49 u32 nvquirks;
50};
51
52struct sdhci_tegra {
53 const struct sdhci_tegra_soc_data *soc_data;
54 int power_gpio;
55};
56
57static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
58{
59 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
60 struct sdhci_tegra *tegra_host = pltfm_host->priv;
61 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
62
63 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
64 (reg == SDHCI_HOST_VERSION))) {
65 /* Erratum: Version register is invalid in HW. */
66 return SDHCI_SPEC_200;
67 }
68
69 return readw(host->ioaddr + reg);
70}
71
72static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
73{
74 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
75 struct sdhci_tegra *tegra_host = pltfm_host->priv;
76 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
77
78 /* Seems like we're getting spurious timeout and crc errors, so
79 * disable signalling of them. In case of real errors software
80 * timers should take care of eventually detecting them.
81 */
82 if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
83 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
84
85 writel(val, host->ioaddr + reg);
86
87 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
88 (reg == SDHCI_INT_ENABLE))) {
89 /* Erratum: Must enable block gap interrupt detection */
90 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
91 if (val & SDHCI_INT_CARD_INT)
92 gap_ctrl |= 0x8;
93 else
94 gap_ctrl &= ~0x8;
95 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
96 }
97}
98
99static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
100{
101 return mmc_gpio_get_ro(host->mmc);
102}
103
104static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
105{
106 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
107 struct sdhci_tegra *tegra_host = pltfm_host->priv;
108 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
109 u32 misc_ctrl;
110
111 sdhci_reset(host, mask);
112
113 if (!(mask & SDHCI_RESET_ALL))
114 return;
115
116 misc_ctrl = sdhci_readw(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
117 /* Erratum: Enable SDHCI spec v3.00 support */
118 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
119 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
120 /* Don't advertise UHS modes which aren't supported yet */
121 if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR50)
122 misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR50;
123 if (soc_data->nvquirks & NVQUIRK_DISABLE_DDR50)
124 misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_DDR50;
125 if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR104)
126 misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR104;
127 sdhci_writew(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
128}
129
130static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width)
131{
132 u32 ctrl;
133
134 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
135 if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) &&
136 (bus_width == MMC_BUS_WIDTH_8)) {
137 ctrl &= ~SDHCI_CTRL_4BITBUS;
138 ctrl |= SDHCI_CTRL_8BITBUS;
139 } else {
140 ctrl &= ~SDHCI_CTRL_8BITBUS;
141 if (bus_width == MMC_BUS_WIDTH_4)
142 ctrl |= SDHCI_CTRL_4BITBUS;
143 else
144 ctrl &= ~SDHCI_CTRL_4BITBUS;
145 }
146 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
147}
148
149static const struct sdhci_ops tegra_sdhci_ops = {
150 .get_ro = tegra_sdhci_get_ro,
151 .read_w = tegra_sdhci_readw,
152 .write_l = tegra_sdhci_writel,
153 .set_clock = sdhci_set_clock,
154 .set_bus_width = tegra_sdhci_set_bus_width,
155 .reset = tegra_sdhci_reset,
156 .set_uhs_signaling = sdhci_set_uhs_signaling,
157 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
158};
159
160static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
161 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
162 SDHCI_QUIRK_SINGLE_POWER_WRITE |
163 SDHCI_QUIRK_NO_HISPD_BIT |
164 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
165 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
166 .ops = &tegra_sdhci_ops,
167};
168
169static struct sdhci_tegra_soc_data soc_data_tegra20 = {
170 .pdata = &sdhci_tegra20_pdata,
171 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
172 NVQUIRK_ENABLE_BLOCK_GAP_DET,
173};
174
175static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
176 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
177 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
178 SDHCI_QUIRK_SINGLE_POWER_WRITE |
179 SDHCI_QUIRK_NO_HISPD_BIT |
180 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
181 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
182 .ops = &tegra_sdhci_ops,
183};
184
185static struct sdhci_tegra_soc_data soc_data_tegra30 = {
186 .pdata = &sdhci_tegra30_pdata,
187 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 |
188 NVQUIRK_DISABLE_SDR50 |
189 NVQUIRK_DISABLE_SDR104,
190};
191
192static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
193 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
194 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
195 SDHCI_QUIRK_SINGLE_POWER_WRITE |
196 SDHCI_QUIRK_NO_HISPD_BIT |
197 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
198 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
199 .ops = &tegra_sdhci_ops,
200};
201
202static struct sdhci_tegra_soc_data soc_data_tegra114 = {
203 .pdata = &sdhci_tegra114_pdata,
204 .nvquirks = NVQUIRK_DISABLE_SDR50 |
205 NVQUIRK_DISABLE_DDR50 |
206 NVQUIRK_DISABLE_SDR104,
207};
208
209static const struct of_device_id sdhci_tegra_dt_match[] = {
210 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra114 },
211 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
212 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
213 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
214 {}
215};
216MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);
217
218static int sdhci_tegra_parse_dt(struct device *dev)
219{
220 struct device_node *np = dev->of_node;
221 struct sdhci_host *host = dev_get_drvdata(dev);
222 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
223 struct sdhci_tegra *tegra_host = pltfm_host->priv;
224
225 tegra_host->power_gpio = of_get_named_gpio(np, "power-gpios", 0);
226 return mmc_of_parse(host->mmc);
227}
228
229static int sdhci_tegra_probe(struct platform_device *pdev)
230{
231 const struct of_device_id *match;
232 const struct sdhci_tegra_soc_data *soc_data;
233 struct sdhci_host *host;
234 struct sdhci_pltfm_host *pltfm_host;
235 struct sdhci_tegra *tegra_host;
236 struct clk *clk;
237 int rc;
238
239 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
240 if (!match)
241 return -EINVAL;
242 soc_data = match->data;
243
244 host = sdhci_pltfm_init(pdev, soc_data->pdata, 0);
245 if (IS_ERR(host))
246 return PTR_ERR(host);
247 pltfm_host = sdhci_priv(host);
248
249 tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL);
250 if (!tegra_host) {
251 dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n");
252 rc = -ENOMEM;
253 goto err_alloc_tegra_host;
254 }
255 tegra_host->soc_data = soc_data;
256 pltfm_host->priv = tegra_host;
257
258 rc = sdhci_tegra_parse_dt(&pdev->dev);
259 if (rc)
260 goto err_parse_dt;
261
262 if (gpio_is_valid(tegra_host->power_gpio)) {
263 rc = gpio_request(tegra_host->power_gpio, "sdhci_power");
264 if (rc) {
265 dev_err(mmc_dev(host->mmc),
266 "failed to allocate power gpio\n");
267 goto err_power_req;
268 }
269 gpio_direction_output(tegra_host->power_gpio, 1);
270 }
271
272 clk = clk_get(mmc_dev(host->mmc), NULL);
273 if (IS_ERR(clk)) {
274 dev_err(mmc_dev(host->mmc), "clk err\n");
275 rc = PTR_ERR(clk);
276 goto err_clk_get;
277 }
278 clk_prepare_enable(clk);
279 pltfm_host->clk = clk;
280
281 rc = sdhci_add_host(host);
282 if (rc)
283 goto err_add_host;
284
285 return 0;
286
287err_add_host:
288 clk_disable_unprepare(pltfm_host->clk);
289 clk_put(pltfm_host->clk);
290err_clk_get:
291 if (gpio_is_valid(tegra_host->power_gpio))
292 gpio_free(tegra_host->power_gpio);
293err_power_req:
294err_parse_dt:
295err_alloc_tegra_host:
296 sdhci_pltfm_free(pdev);
297 return rc;
298}
299
300static int sdhci_tegra_remove(struct platform_device *pdev)
301{
302 struct sdhci_host *host = platform_get_drvdata(pdev);
303 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
304 struct sdhci_tegra *tegra_host = pltfm_host->priv;
305 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
306
307 sdhci_remove_host(host, dead);
308
309 if (gpio_is_valid(tegra_host->power_gpio))
310 gpio_free(tegra_host->power_gpio);
311
312 clk_disable_unprepare(pltfm_host->clk);
313 clk_put(pltfm_host->clk);
314
315 sdhci_pltfm_free(pdev);
316
317 return 0;
318}
319
320static struct platform_driver sdhci_tegra_driver = {
321 .driver = {
322 .name = "sdhci-tegra",
323 .owner = THIS_MODULE,
324 .of_match_table = sdhci_tegra_dt_match,
325 .pm = SDHCI_PLTFM_PMOPS,
326 },
327 .probe = sdhci_tegra_probe,
328 .remove = sdhci_tegra_remove,
329};
330
331module_platform_driver(sdhci_tegra_driver);
332
333MODULE_DESCRIPTION("SDHCI driver for Tegra");
334MODULE_AUTHOR("Google, Inc.");
335MODULE_LICENSE("GPL v2");