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1#ifndef _EDAC_MCE_AMD_H
2#define _EDAC_MCE_AMD_H
3
4#include <linux/notifier.h>
5
6#include <asm/mce.h>
7
8#define EC(x) ((x) & 0xffff)
9#define XEC(x, mask) (((x) >> 16) & mask)
10
11#define LOW_SYNDROME(x) (((x) >> 15) & 0xff)
12#define HIGH_SYNDROME(x) (((x) >> 24) & 0xff)
13
14#define TLB_ERROR(x) (((x) & 0xFFF0) == 0x0010)
15#define MEM_ERROR(x) (((x) & 0xFF00) == 0x0100)
16#define BUS_ERROR(x) (((x) & 0xF800) == 0x0800)
17#define INT_ERROR(x) (((x) & 0xF4FF) == 0x0400)
18
19#define TT(x) (((x) >> 2) & 0x3)
20#define TT_MSG(x) tt_msgs[TT(x)]
21#define II(x) (((x) >> 2) & 0x3)
22#define II_MSG(x) ii_msgs[II(x)]
23#define LL(x) ((x) & 0x3)
24#define LL_MSG(x) ll_msgs[LL(x)]
25#define TO(x) (((x) >> 8) & 0x1)
26#define TO_MSG(x) to_msgs[TO(x)]
27#define PP(x) (((x) >> 9) & 0x3)
28#define PP_MSG(x) pp_msgs[PP(x)]
29#define UU(x) (((x) >> 8) & 0x3)
30#define UU_MSG(x) uu_msgs[UU(x)]
31
32#define R4(x) (((x) >> 4) & 0xf)
33#define R4_MSG(x) ((R4(x) < 9) ? rrrr_msgs[R4(x)] : "Wrong R4!")
34
35#define MCI_STATUS_DEFERRED BIT_64(44)
36#define MCI_STATUS_POISON BIT_64(43)
37
38extern const char * const pp_msgs[];
39
40enum tt_ids {
41 TT_INSTR = 0,
42 TT_DATA,
43 TT_GEN,
44 TT_RESV,
45};
46
47enum ll_ids {
48 LL_RESV = 0,
49 LL_L1,
50 LL_L2,
51 LL_LG,
52};
53
54enum ii_ids {
55 II_MEM = 0,
56 II_RESV,
57 II_IO,
58 II_GEN,
59};
60
61enum rrrr_ids {
62 R4_GEN = 0,
63 R4_RD,
64 R4_WR,
65 R4_DRD,
66 R4_DWR,
67 R4_IRD,
68 R4_PREF,
69 R4_EVICT,
70 R4_SNOOP,
71};
72
73/*
74 * per-family decoder ops
75 */
76struct amd_decoder_ops {
77 bool (*mc0_mce)(u16, u8);
78 bool (*mc1_mce)(u16, u8);
79 bool (*mc2_mce)(u16, u8);
80};
81
82void amd_report_gart_errors(bool);
83void amd_register_ecc_decoder(void (*f)(int, struct mce *));
84void amd_unregister_ecc_decoder(void (*f)(int, struct mce *));
85int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data);
86
87#endif /* _EDAC_MCE_AMD_H */