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1Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY
2-------------------------------------------------
3
4Required properties:
5- compatible : should be "samsung,s5pv210-mipi-video-phy";
6- reg : offset and length of the MIPI DPHY register set;
7- #phy-cells : from the generic phy bindings, must be 1;
8
9For "samsung,s5pv210-mipi-video-phy" compatible PHYs the second cell in
10the PHY specifier identifies the PHY and its meaning is as follows:
11 0 - MIPI CSIS 0,
12 1 - MIPI DSIM 0,
13 2 - MIPI CSIS 1,
14 3 - MIPI DSIM 1.
15
16Samsung EXYNOS SoC series Display Port PHY
17-------------------------------------------------
18
19Required properties:
20- compatible : should be "samsung,exynos5250-dp-video-phy";
21- reg : offset and length of the Display Port PHY register set;
22- #phy-cells : from the generic PHY bindings, must be 0;
23
24Samsung S5P/EXYNOS SoC series USB PHY
25-------------------------------------------------
26
27Required properties:
28- compatible : should be one of the listed compatibles:
29 - "samsung,exynos4210-usb2-phy"
30 - "samsung,exynos4x12-usb2-phy"
31 - "samsung,exynos5250-usb2-phy"
32- reg : a list of registers used by phy driver
33 - first and obligatory is the location of phy modules registers
34- samsung,sysreg-phandle - handle to syscon used to control the system registers
35- samsung,pmureg-phandle - handle to syscon used to control PMU registers
36- #phy-cells : from the generic phy bindings, must be 1;
37- clocks and clock-names:
38 - the "phy" clock is required by the phy module, used as a gate
39 - the "ref" clock is used to get the rate of the clock provided to the
40 PHY module
41
42The first phandle argument in the PHY specifier identifies the PHY, its
43meaning is compatible dependent. For the currently supported SoCs (Exynos 4210
44and Exynos 4212) it is as follows:
45 0 - USB device ("device"),
46 1 - USB host ("host"),
47 2 - HSIC0 ("hsic0"),
48 3 - HSIC1 ("hsic1"),
49
50Exynos 4210 and Exynos 4212 use mode switching and require that mode switch
51register is supplied.
52
53Example:
54
55For Exynos 4412 (compatible with Exynos 4212):
56
57usbphy: phy@125b0000 {
58 compatible = "samsung,exynos4x12-usb2-phy";
59 reg = <0x125b0000 0x100>;
60 clocks = <&clock 305>, <&clock 2>;
61 clock-names = "phy", "ref";
62 status = "okay";
63 #phy-cells = <1>;
64 samsung,sysreg-phandle = <&sys_reg>;
65 samsung,pmureg-phandle = <&pmu_reg>;
66};
67
68Then the PHY can be used in other nodes such as:
69
70phy-consumer@12340000 {
71 phys = <&usbphy 2>;
72 phy-names = "phy";
73};
74
75Refer to DT bindings documentation of particular PHY consumer devices for more
76information about required PHYs and the way of specification.
77
78Samsung SATA PHY Controller
79---------------------------
80
81SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
82Each SATA PHY controller should have its own node.
83
84Required properties:
85- compatible : compatible list, contains "samsung,exynos5250-sata-phy"
86- reg : offset and length of the SATA PHY register set;
87- #phy-cells : must be zero
88- clocks : must be exactly one entry
89- clock-names : must be "sata_phyctrl"
90- samsung,exynos-sataphy-i2c-phandle : a phandle to the I2C device, no arguments
91- samsung,syscon-phandle : a phandle to the PMU system controller, no arguments
92
93Example:
94 sata_phy: sata-phy@12170000 {
95 compatible = "samsung,exynos5250-sata-phy";
96 reg = <0x12170000 0x1ff>;
97 clocks = <&clock 287>;
98 clock-names = "sata_phyctrl";
99 #phy-cells = <0>;
100 samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
101 samsung,syscon-phandle = <&pmu_syscon>;
102 };
103
104Device-Tree bindings for sataphy i2c client driver
105--------------------------------------------------
106
107Required properties:
108compatible: Should be "samsung,exynos-sataphy-i2c"
109- reg: I2C address of the sataphy i2c device.
110
111Example:
112
113 sata_phy_i2c:sata-phy@38 {
114 compatible = "samsung,exynos-sataphy-i2c";
115 reg = <0x38>;
116 };
117
118Samsung Exynos5 SoC series USB DRD PHY controller
119--------------------------------------------------
120
121Required properties:
122- compatible : Should be set to one of the following supported values:
123 - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
124 - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
125- reg : Register offset and length of USB DRD PHY register set;
126- clocks: Clock IDs array as required by the controller
127- clock-names: names of clocks correseponding to IDs in the clock property;
128 Required clocks:
129 - phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),
130 used for register access.
131 - ref: PHY's reference clock (usually crystal clock), used for
132 PHY operations, associated by phy name. It is used to
133 determine bit values for clock settings register.
134 For Exynos5420 this is given as 'sclk_usbphy30' in CMU.
135- samsung,pmu-syscon: phandle for PMU system controller interface, used to
136 control pmu registers for power isolation.
137- #phy-cells : from the generic PHY bindings, must be 1;
138
139For "samsung,exynos5250-usbdrd-phy" and "samsung,exynos5420-usbdrd-phy"
140compatible PHYs, the second cell in the PHY specifier identifies the
141PHY id, which is interpreted as follows:
142 0 - UTMI+ type phy,
143 1 - PIPE3 type phy,
144
145Example:
146 usbdrd_phy: usbphy@12100000 {
147 compatible = "samsung,exynos5250-usbdrd-phy";
148 reg = <0x12100000 0x100>;
149 clocks = <&clock 286>, <&clock 1>;
150 clock-names = "phy", "ref";
151 samsung,pmu-syscon = <&pmu_system_controller>;
152 #phy-cells = <1>;
153 };
154
155- aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
156 'usbdrd_phy' nodes should have numbered alias in the aliases node,
157 in the form of usbdrdphyN, N = 0, 1... (depending on number of
158 controllers).
159Example:
160 aliases {
161 usbdrdphy0 = &usb3_phy0;
162 usbdrdphy1 = &usb3_phy1;
163 };