tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * max14577-private.h - Common API for the Maxim 14577/77836 internal sub chip
3 *
4 * Copyright (C) 2014 Samsung Electrnoics
5 * Chanwoo Choi <cw00.choi@samsung.com>
6 * Krzysztof Kozlowski <k.kozlowski@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __MAX14577_PRIVATE_H__
20#define __MAX14577_PRIVATE_H__
21
22#include <linux/i2c.h>
23#include <linux/regmap.h>
24
25#define I2C_ADDR_PMIC (0x46 >> 1)
26#define I2C_ADDR_MUIC (0x4A >> 1)
27#define I2C_ADDR_FG (0x6C >> 1)
28
29enum maxim_device_type {
30 MAXIM_DEVICE_TYPE_UNKNOWN = 0,
31 MAXIM_DEVICE_TYPE_MAX14577,
32 MAXIM_DEVICE_TYPE_MAX77836,
33
34 MAXIM_DEVICE_TYPE_NUM,
35};
36
37/* Slave addr = 0x4A: MUIC and Charger */
38enum max14577_reg {
39 MAX14577_REG_DEVICEID = 0x00,
40 MAX14577_REG_INT1 = 0x01,
41 MAX14577_REG_INT2 = 0x02,
42 MAX14577_REG_INT3 = 0x03,
43 MAX14577_REG_STATUS1 = 0x04,
44 MAX14577_REG_STATUS2 = 0x05,
45 MAX14577_REG_STATUS3 = 0x06,
46 MAX14577_REG_INTMASK1 = 0x07,
47 MAX14577_REG_INTMASK2 = 0x08,
48 MAX14577_REG_INTMASK3 = 0x09,
49 MAX14577_REG_CDETCTRL1 = 0x0A,
50 MAX14577_REG_RFU = 0x0B,
51 MAX14577_REG_CONTROL1 = 0x0C,
52 MAX14577_REG_CONTROL2 = 0x0D,
53 MAX14577_REG_CONTROL3 = 0x0E,
54 MAX14577_REG_CHGCTRL1 = 0x0F,
55 MAX14577_REG_CHGCTRL2 = 0x10,
56 MAX14577_REG_CHGCTRL3 = 0x11,
57 MAX14577_REG_CHGCTRL4 = 0x12,
58 MAX14577_REG_CHGCTRL5 = 0x13,
59 MAX14577_REG_CHGCTRL6 = 0x14,
60 MAX14577_REG_CHGCTRL7 = 0x15,
61
62 MAX14577_REG_END,
63};
64
65/* Slave addr = 0x4A: MUIC */
66enum max14577_muic_reg {
67 MAX14577_MUIC_REG_STATUS1 = 0x04,
68 MAX14577_MUIC_REG_STATUS2 = 0x05,
69 MAX14577_MUIC_REG_CONTROL1 = 0x0C,
70 MAX14577_MUIC_REG_CONTROL3 = 0x0E,
71
72 MAX14577_MUIC_REG_END,
73};
74
75enum max14577_muic_charger_type {
76 MAX14577_CHARGER_TYPE_NONE = 0,
77 MAX14577_CHARGER_TYPE_USB,
78 MAX14577_CHARGER_TYPE_DOWNSTREAM_PORT,
79 MAX14577_CHARGER_TYPE_DEDICATED_CHG,
80 MAX14577_CHARGER_TYPE_SPECIAL_500MA,
81 MAX14577_CHARGER_TYPE_SPECIAL_1A,
82 MAX14577_CHARGER_TYPE_RESERVED,
83 MAX14577_CHARGER_TYPE_DEAD_BATTERY = 7,
84};
85
86/* MAX14577 interrupts */
87#define MAX14577_INT1_ADC_MASK BIT(0)
88#define MAX14577_INT1_ADCLOW_MASK BIT(1)
89#define MAX14577_INT1_ADCERR_MASK BIT(2)
90#define MAX77836_INT1_ADC1K_MASK BIT(3)
91
92#define MAX14577_INT2_CHGTYP_MASK BIT(0)
93#define MAX14577_INT2_CHGDETRUN_MASK BIT(1)
94#define MAX14577_INT2_DCDTMR_MASK BIT(2)
95#define MAX14577_INT2_DBCHG_MASK BIT(3)
96#define MAX14577_INT2_VBVOLT_MASK BIT(4)
97#define MAX77836_INT2_VIDRM_MASK BIT(5)
98
99#define MAX14577_INT3_EOC_MASK BIT(0)
100#define MAX14577_INT3_CGMBC_MASK BIT(1)
101#define MAX14577_INT3_OVP_MASK BIT(2)
102#define MAX14577_INT3_MBCCHGERR_MASK BIT(3)
103
104/* MAX14577 DEVICE ID register */
105#define DEVID_VENDORID_SHIFT 0
106#define DEVID_DEVICEID_SHIFT 3
107#define DEVID_VENDORID_MASK (0x07 << DEVID_VENDORID_SHIFT)
108#define DEVID_DEVICEID_MASK (0x1f << DEVID_DEVICEID_SHIFT)
109
110/* MAX14577 STATUS1 register */
111#define STATUS1_ADC_SHIFT 0
112#define STATUS1_ADCLOW_SHIFT 5
113#define STATUS1_ADCERR_SHIFT 6
114#define MAX77836_STATUS1_ADC1K_SHIFT 7
115#define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
116#define STATUS1_ADCLOW_MASK BIT(STATUS1_ADCLOW_SHIFT)
117#define STATUS1_ADCERR_MASK BIT(STATUS1_ADCERR_SHIFT)
118#define MAX77836_STATUS1_ADC1K_MASK BIT(MAX77836_STATUS1_ADC1K_SHIFT)
119
120/* MAX14577 STATUS2 register */
121#define STATUS2_CHGTYP_SHIFT 0
122#define STATUS2_CHGDETRUN_SHIFT 3
123#define STATUS2_DCDTMR_SHIFT 4
124#define STATUS2_DBCHG_SHIFT 5
125#define STATUS2_VBVOLT_SHIFT 6
126#define MAX77836_STATUS2_VIDRM_SHIFT 7
127#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
128#define STATUS2_CHGDETRUN_MASK BIT(STATUS2_CHGDETRUN_SHIFT)
129#define STATUS2_DCDTMR_MASK BIT(STATUS2_DCDTMR_SHIFT)
130#define STATUS2_DBCHG_MASK BIT(STATUS2_DBCHG_SHIFT)
131#define STATUS2_VBVOLT_MASK BIT(STATUS2_VBVOLT_SHIFT)
132#define MAX77836_STATUS2_VIDRM_MASK BIT(MAX77836_STATUS2_VIDRM_SHIFT)
133
134/* MAX14577 CONTROL1 register */
135#define COMN1SW_SHIFT 0
136#define COMP2SW_SHIFT 3
137#define MICEN_SHIFT 6
138#define IDBEN_SHIFT 7
139#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
140#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
141#define MICEN_MASK BIT(MICEN_SHIFT)
142#define IDBEN_MASK BIT(IDBEN_SHIFT)
143#define CLEAR_IDBEN_MICEN_MASK (COMN1SW_MASK | COMP2SW_MASK)
144#define CTRL1_SW_USB ((1 << COMP2SW_SHIFT) \
145 | (1 << COMN1SW_SHIFT))
146#define CTRL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \
147 | (2 << COMN1SW_SHIFT))
148#define CTRL1_SW_UART ((3 << COMP2SW_SHIFT) \
149 | (3 << COMN1SW_SHIFT))
150#define CTRL1_SW_OPEN ((0 << COMP2SW_SHIFT) \
151 | (0 << COMN1SW_SHIFT))
152
153/* MAX14577 CONTROL2 register */
154#define CTRL2_LOWPWR_SHIFT (0)
155#define CTRL2_ADCEN_SHIFT (1)
156#define CTRL2_CPEN_SHIFT (2)
157#define CTRL2_SFOUTASRT_SHIFT (3)
158#define CTRL2_SFOUTORD_SHIFT (4)
159#define CTRL2_ACCDET_SHIFT (5)
160#define CTRL2_USBCPINT_SHIFT (6)
161#define CTRL2_RCPS_SHIFT (7)
162#define CTRL2_LOWPWR_MASK BIT(CTRL2_LOWPWR_SHIFT)
163#define CTRL2_ADCEN_MASK BIT(CTRL2_ADCEN_SHIFT)
164#define CTRL2_CPEN_MASK BIT(CTRL2_CPEN_SHIFT)
165#define CTRL2_SFOUTASRT_MASK BIT(CTRL2_SFOUTASRT_SHIFT)
166#define CTRL2_SFOUTORD_MASK BIT(CTRL2_SFOUTORD_SHIFT)
167#define CTRL2_ACCDET_MASK BIT(CTRL2_ACCDET_SHIFT)
168#define CTRL2_USBCPINT_MASK BIT(CTRL2_USBCPINT_SHIFT)
169#define CTRL2_RCPS_MASK BIT(CTRL2_RCPS_SHIFT)
170
171#define CTRL2_CPEN1_LOWPWR0 ((1 << CTRL2_CPEN_SHIFT) | \
172 (0 << CTRL2_LOWPWR_SHIFT))
173#define CTRL2_CPEN0_LOWPWR1 ((0 << CTRL2_CPEN_SHIFT) | \
174 (1 << CTRL2_LOWPWR_SHIFT))
175
176/* MAX14577 CONTROL3 register */
177#define CTRL3_JIGSET_SHIFT 0
178#define CTRL3_BOOTSET_SHIFT 2
179#define CTRL3_ADCDBSET_SHIFT 4
180#define CTRL3_JIGSET_MASK (0x3 << CTRL3_JIGSET_SHIFT)
181#define CTRL3_BOOTSET_MASK (0x3 << CTRL3_BOOTSET_SHIFT)
182#define CTRL3_ADCDBSET_MASK (0x3 << CTRL3_ADCDBSET_SHIFT)
183
184/* Slave addr = 0x4A: Charger */
185enum max14577_charger_reg {
186 MAX14577_CHG_REG_STATUS3 = 0x06,
187 MAX14577_CHG_REG_CHG_CTRL1 = 0x0F,
188 MAX14577_CHG_REG_CHG_CTRL2 = 0x10,
189 MAX14577_CHG_REG_CHG_CTRL3 = 0x11,
190 MAX14577_CHG_REG_CHG_CTRL4 = 0x12,
191 MAX14577_CHG_REG_CHG_CTRL5 = 0x13,
192 MAX14577_CHG_REG_CHG_CTRL6 = 0x14,
193 MAX14577_CHG_REG_CHG_CTRL7 = 0x15,
194
195 MAX14577_CHG_REG_END,
196};
197
198/* MAX14577 STATUS3 register */
199#define STATUS3_EOC_SHIFT 0
200#define STATUS3_CGMBC_SHIFT 1
201#define STATUS3_OVP_SHIFT 2
202#define STATUS3_MBCCHGERR_SHIFT 3
203#define STATUS3_EOC_MASK (0x1 << STATUS3_EOC_SHIFT)
204#define STATUS3_CGMBC_MASK (0x1 << STATUS3_CGMBC_SHIFT)
205#define STATUS3_OVP_MASK (0x1 << STATUS3_OVP_SHIFT)
206#define STATUS3_MBCCHGERR_MASK (0x1 << STATUS3_MBCCHGERR_SHIFT)
207
208/* MAX14577 CDETCTRL1 register */
209#define CDETCTRL1_CHGDETEN_SHIFT 0
210#define CDETCTRL1_CHGTYPMAN_SHIFT 1
211#define CDETCTRL1_DCDEN_SHIFT 2
212#define CDETCTRL1_DCD2SCT_SHIFT 3
213#define CDETCTRL1_DCHKTM_SHIFT 4
214#define CDETCTRL1_DBEXIT_SHIFT 5
215#define CDETCTRL1_DBIDLE_SHIFT 6
216#define CDETCTRL1_CDPDET_SHIFT 7
217#define CDETCTRL1_CHGDETEN_MASK BIT(CDETCTRL1_CHGDETEN_SHIFT)
218#define CDETCTRL1_CHGTYPMAN_MASK BIT(CDETCTRL1_CHGTYPMAN_SHIFT)
219#define CDETCTRL1_DCDEN_MASK BIT(CDETCTRL1_DCDEN_SHIFT)
220#define CDETCTRL1_DCD2SCT_MASK BIT(CDETCTRL1_DCD2SCT_SHIFT)
221#define CDETCTRL1_DCHKTM_MASK BIT(CDETCTRL1_DCHKTM_SHIFT)
222#define CDETCTRL1_DBEXIT_MASK BIT(CDETCTRL1_DBEXIT_SHIFT)
223#define CDETCTRL1_DBIDLE_MASK BIT(CDETCTRL1_DBIDLE_SHIFT)
224#define CDETCTRL1_CDPDET_MASK BIT(CDETCTRL1_CDPDET_SHIFT)
225
226/* MAX14577 CHGCTRL1 register */
227#define CHGCTRL1_TCHW_SHIFT 4
228#define CHGCTRL1_TCHW_MASK (0x7 << CHGCTRL1_TCHW_SHIFT)
229
230/* MAX14577 CHGCTRL2 register */
231#define CHGCTRL2_MBCHOSTEN_SHIFT 6
232#define CHGCTRL2_MBCHOSTEN_MASK BIT(CHGCTRL2_MBCHOSTEN_SHIFT)
233#define CHGCTRL2_VCHGR_RC_SHIFT 7
234#define CHGCTRL2_VCHGR_RC_MASK BIT(CHGCTRL2_VCHGR_RC_SHIFT)
235
236/* MAX14577 CHGCTRL3 register */
237#define CHGCTRL3_MBCCVWRC_SHIFT 0
238#define CHGCTRL3_MBCCVWRC_MASK (0xf << CHGCTRL3_MBCCVWRC_SHIFT)
239
240/* MAX14577 CHGCTRL4 register */
241#define CHGCTRL4_MBCICHWRCH_SHIFT 0
242#define CHGCTRL4_MBCICHWRCH_MASK (0xf << CHGCTRL4_MBCICHWRCH_SHIFT)
243#define CHGCTRL4_MBCICHWRCL_SHIFT 4
244#define CHGCTRL4_MBCICHWRCL_MASK BIT(CHGCTRL4_MBCICHWRCL_SHIFT)
245
246/* MAX14577 CHGCTRL5 register */
247#define CHGCTRL5_EOCS_SHIFT 0
248#define CHGCTRL5_EOCS_MASK (0xf << CHGCTRL5_EOCS_SHIFT)
249
250/* MAX14577 CHGCTRL6 register */
251#define CHGCTRL6_AUTOSTOP_SHIFT 5
252#define CHGCTRL6_AUTOSTOP_MASK BIT(CHGCTRL6_AUTOSTOP_SHIFT)
253
254/* MAX14577 CHGCTRL7 register */
255#define CHGCTRL7_OTPCGHCVS_SHIFT 0
256#define CHGCTRL7_OTPCGHCVS_MASK (0x3 << CHGCTRL7_OTPCGHCVS_SHIFT)
257
258/* MAX14577 regulator current limits (as in CHGCTRL4 register), uA */
259#define MAX14577_REGULATOR_CURRENT_LIMIT_MIN 90000
260#define MAX14577_REGULATOR_CURRENT_LIMIT_HIGH_START 200000
261#define MAX14577_REGULATOR_CURRENT_LIMIT_HIGH_STEP 50000
262#define MAX14577_REGULATOR_CURRENT_LIMIT_MAX 950000
263
264/* MAX77836 regulator current limits (as in CHGCTRL4 register), uA */
265#define MAX77836_REGULATOR_CURRENT_LIMIT_MIN 45000
266#define MAX77836_REGULATOR_CURRENT_LIMIT_HIGH_START 100000
267#define MAX77836_REGULATOR_CURRENT_LIMIT_HIGH_STEP 25000
268#define MAX77836_REGULATOR_CURRENT_LIMIT_MAX 475000
269
270/* MAX14577 regulator SFOUT LDO voltage, fixed, uV */
271#define MAX14577_REGULATOR_SAFEOUT_VOLTAGE 4900000
272
273/* MAX77836 regulator LDOx voltage, uV */
274#define MAX77836_REGULATOR_LDO_VOLTAGE_MIN 800000
275#define MAX77836_REGULATOR_LDO_VOLTAGE_MAX 3950000
276#define MAX77836_REGULATOR_LDO_VOLTAGE_STEP 50000
277#define MAX77836_REGULATOR_LDO_VOLTAGE_STEPS_NUM 64
278
279/* Slave addr = 0x46: PMIC */
280enum max77836_pmic_reg {
281 MAX77836_PMIC_REG_PMIC_ID = 0x20,
282 MAX77836_PMIC_REG_PMIC_REV = 0x21,
283 MAX77836_PMIC_REG_INTSRC = 0x22,
284 MAX77836_PMIC_REG_INTSRC_MASK = 0x23,
285 MAX77836_PMIC_REG_TOPSYS_INT = 0x24,
286 MAX77836_PMIC_REG_TOPSYS_INT_MASK = 0x26,
287 MAX77836_PMIC_REG_TOPSYS_STAT = 0x28,
288 MAX77836_PMIC_REG_MRSTB_CNTL = 0x2A,
289 MAX77836_PMIC_REG_LSCNFG = 0x2B,
290
291 MAX77836_LDO_REG_CNFG1_LDO1 = 0x51,
292 MAX77836_LDO_REG_CNFG2_LDO1 = 0x52,
293 MAX77836_LDO_REG_CNFG1_LDO2 = 0x53,
294 MAX77836_LDO_REG_CNFG2_LDO2 = 0x54,
295 MAX77836_LDO_REG_CNFG_LDO_BIAS = 0x55,
296
297 MAX77836_COMP_REG_COMP1 = 0x60,
298
299 MAX77836_PMIC_REG_END,
300};
301
302#define MAX77836_INTSRC_MASK_TOP_INT_SHIFT 1
303#define MAX77836_INTSRC_MASK_MUIC_CHG_INT_SHIFT 3
304#define MAX77836_INTSRC_MASK_TOP_INT_MASK BIT(MAX77836_INTSRC_MASK_TOP_INT_SHIFT)
305#define MAX77836_INTSRC_MASK_MUIC_CHG_INT_MASK BIT(MAX77836_INTSRC_MASK_MUIC_CHG_INT_SHIFT)
306
307/* MAX77836 PMIC interrupts */
308#define MAX77836_TOPSYS_INT_T120C_SHIFT 0
309#define MAX77836_TOPSYS_INT_T140C_SHIFT 1
310#define MAX77836_TOPSYS_INT_T120C_MASK BIT(MAX77836_TOPSYS_INT_T120C_SHIFT)
311#define MAX77836_TOPSYS_INT_T140C_MASK BIT(MAX77836_TOPSYS_INT_T140C_SHIFT)
312
313/* LDO1/LDO2 CONFIG1 register */
314#define MAX77836_CNFG1_LDO_PWRMD_SHIFT 6
315#define MAX77836_CNFG1_LDO_TV_SHIFT 0
316#define MAX77836_CNFG1_LDO_PWRMD_MASK (0x3 << MAX77836_CNFG1_LDO_PWRMD_SHIFT)
317#define MAX77836_CNFG1_LDO_TV_MASK (0x3f << MAX77836_CNFG1_LDO_TV_SHIFT)
318
319/* LDO1/LDO2 CONFIG2 register */
320#define MAX77836_CNFG2_LDO_OVCLMPEN_SHIFT 7
321#define MAX77836_CNFG2_LDO_ALPMEN_SHIFT 6
322#define MAX77836_CNFG2_LDO_COMP_SHIFT 4
323#define MAX77836_CNFG2_LDO_POK_SHIFT 3
324#define MAX77836_CNFG2_LDO_ADE_SHIFT 1
325#define MAX77836_CNFG2_LDO_SS_SHIFT 0
326#define MAX77836_CNFG2_LDO_OVCLMPEN_MASK BIT(MAX77836_CNFG2_LDO_OVCLMPEN_SHIFT)
327#define MAX77836_CNFG2_LDO_ALPMEN_MASK BIT(MAX77836_CNFG2_LDO_ALPMEN_SHIFT)
328#define MAX77836_CNFG2_LDO_COMP_MASK (0x3 << MAX77836_CNFG2_LDO_COMP_SHIFT)
329#define MAX77836_CNFG2_LDO_POK_MASK BIT(MAX77836_CNFG2_LDO_POK_SHIFT)
330#define MAX77836_CNFG2_LDO_ADE_MASK BIT(MAX77836_CNFG2_LDO_ADE_SHIFT)
331#define MAX77836_CNFG2_LDO_SS_MASK BIT(MAX77836_CNFG2_LDO_SS_SHIFT)
332
333/* Slave addr = 0x6C: Fuel-Gauge/Battery */
334enum max77836_fg_reg {
335 MAX77836_FG_REG_VCELL_MSB = 0x02,
336 MAX77836_FG_REG_VCELL_LSB = 0x03,
337 MAX77836_FG_REG_SOC_MSB = 0x04,
338 MAX77836_FG_REG_SOC_LSB = 0x05,
339 MAX77836_FG_REG_MODE_H = 0x06,
340 MAX77836_FG_REG_MODE_L = 0x07,
341 MAX77836_FG_REG_VERSION_MSB = 0x08,
342 MAX77836_FG_REG_VERSION_LSB = 0x09,
343 MAX77836_FG_REG_HIBRT_H = 0x0A,
344 MAX77836_FG_REG_HIBRT_L = 0x0B,
345 MAX77836_FG_REG_CONFIG_H = 0x0C,
346 MAX77836_FG_REG_CONFIG_L = 0x0D,
347 MAX77836_FG_REG_VALRT_MIN = 0x14,
348 MAX77836_FG_REG_VALRT_MAX = 0x15,
349 MAX77836_FG_REG_CRATE_MSB = 0x16,
350 MAX77836_FG_REG_CRATE_LSB = 0x17,
351 MAX77836_FG_REG_VRESET = 0x18,
352 MAX77836_FG_REG_FGID = 0x19,
353 MAX77836_FG_REG_STATUS_H = 0x1A,
354 MAX77836_FG_REG_STATUS_L = 0x1B,
355 /*
356 * TODO: TABLE registers
357 * TODO: CMD register
358 */
359
360 MAX77836_FG_REG_END,
361};
362
363enum max14577_irq {
364 /* INT1 */
365 MAX14577_IRQ_INT1_ADC,
366 MAX14577_IRQ_INT1_ADCLOW,
367 MAX14577_IRQ_INT1_ADCERR,
368 MAX77836_IRQ_INT1_ADC1K,
369
370 /* INT2 */
371 MAX14577_IRQ_INT2_CHGTYP,
372 MAX14577_IRQ_INT2_CHGDETRUN,
373 MAX14577_IRQ_INT2_DCDTMR,
374 MAX14577_IRQ_INT2_DBCHG,
375 MAX14577_IRQ_INT2_VBVOLT,
376 MAX77836_IRQ_INT2_VIDRM,
377
378 /* INT3 */
379 MAX14577_IRQ_INT3_EOC,
380 MAX14577_IRQ_INT3_CGMBC,
381 MAX14577_IRQ_INT3_OVP,
382 MAX14577_IRQ_INT3_MBCCHGERR,
383
384 /* TOPSYS_INT, only MAX77836 */
385 MAX77836_IRQ_TOPSYS_T140C,
386 MAX77836_IRQ_TOPSYS_T120C,
387
388 MAX14577_IRQ_NUM,
389};
390
391struct max14577 {
392 struct device *dev;
393 struct i2c_client *i2c; /* Slave addr = 0x4A */
394 struct i2c_client *i2c_pmic; /* Slave addr = 0x46 */
395 enum maxim_device_type dev_type;
396
397 struct regmap *regmap; /* For MUIC and Charger */
398 struct regmap *regmap_pmic;
399
400 struct regmap_irq_chip_data *irq_data; /* For MUIC and Charger */
401 struct regmap_irq_chip_data *irq_data_pmic;
402 int irq;
403};
404
405/* MAX14577 shared regmap API function */
406static inline int max14577_read_reg(struct regmap *map, u8 reg, u8 *dest)
407{
408 unsigned int val;
409 int ret;
410
411 ret = regmap_read(map, reg, &val);
412 *dest = val;
413
414 return ret;
415}
416
417static inline int max14577_bulk_read(struct regmap *map, u8 reg, u8 *buf,
418 int count)
419{
420 return regmap_bulk_read(map, reg, buf, count);
421}
422
423static inline int max14577_write_reg(struct regmap *map, u8 reg, u8 value)
424{
425 return regmap_write(map, reg, value);
426}
427
428static inline int max14577_bulk_write(struct regmap *map, u8 reg, u8 *buf,
429 int count)
430{
431 return regmap_bulk_write(map, reg, buf, count);
432}
433
434static inline int max14577_update_reg(struct regmap *map, u8 reg, u8 mask,
435 u8 val)
436{
437 return regmap_update_bits(map, reg, mask, val);
438}
439
440#endif /* __MAX14577_PRIVATE_H__ */