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Linux kernel mirror (for testing)
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linux
1/*
2 * Switch a MMU context.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 */
11#ifndef _ASM_MMU_CONTEXT_H
12#define _ASM_MMU_CONTEXT_H
13
14#include <linux/errno.h>
15#include <linux/sched.h>
16#include <linux/smp.h>
17#include <linux/slab.h>
18#include <asm/cacheflush.h>
19#include <asm/hazards.h>
20#include <asm/tlbflush.h>
21#include <asm-generic/mm_hooks.h>
22
23#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
24do { \
25 extern void tlbmiss_handler_setup_pgd(unsigned long); \
26 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \
27} while (0)
28
29#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
30
31#define TLBMISS_HANDLER_RESTORE() \
32 write_c0_xcontext((unsigned long) smp_processor_id() << \
33 SMP_CPUID_REGSHIFT)
34
35#define TLBMISS_HANDLER_SETUP() \
36 do { \
37 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \
38 TLBMISS_HANDLER_RESTORE(); \
39 } while (0)
40
41#else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
42
43/*
44 * For the fast tlb miss handlers, we keep a per cpu array of pointers
45 * to the current pgd for each processor. Also, the proc. id is stuffed
46 * into the context register.
47 */
48extern unsigned long pgd_current[];
49
50#define TLBMISS_HANDLER_RESTORE() \
51 write_c0_context((unsigned long) smp_processor_id() << \
52 SMP_CPUID_REGSHIFT)
53
54#define TLBMISS_HANDLER_SETUP() \
55 TLBMISS_HANDLER_RESTORE(); \
56 back_to_back_c0_hazard(); \
57 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
58#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
59#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
60
61#define ASID_INC 0x40
62#define ASID_MASK 0xfc0
63
64#elif defined(CONFIG_CPU_R8000)
65
66#define ASID_INC 0x10
67#define ASID_MASK 0xff0
68
69#else /* FIXME: not correct for R6000 */
70
71#define ASID_INC 0x1
72#define ASID_MASK 0xff
73
74#endif
75
76#define cpu_context(cpu, mm) ((mm)->context.asid[cpu])
77#define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK)
78#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
79
80static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
81{
82}
83
84/*
85 * All unused by hardware upper bits will be considered
86 * as a software asid extension.
87 */
88#define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
89#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
90
91/* Normal, classic MIPS get_new_mmu_context */
92static inline void
93get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
94{
95 extern void kvm_local_flush_tlb_all(void);
96 unsigned long asid = asid_cache(cpu);
97
98 if (! ((asid += ASID_INC) & ASID_MASK) ) {
99 if (cpu_has_vtag_icache)
100 flush_icache_all();
101#ifdef CONFIG_KVM
102 kvm_local_flush_tlb_all(); /* start new asid cycle */
103#else
104 local_flush_tlb_all(); /* start new asid cycle */
105#endif
106 if (!asid) /* fix version if needed */
107 asid = ASID_FIRST_VERSION;
108 }
109
110 cpu_context(cpu, mm) = asid_cache(cpu) = asid;
111}
112
113/*
114 * Initialize the context related info for a new mm_struct
115 * instance.
116 */
117static inline int
118init_new_context(struct task_struct *tsk, struct mm_struct *mm)
119{
120 int i;
121
122 for_each_possible_cpu(i)
123 cpu_context(i, mm) = 0;
124
125 return 0;
126}
127
128static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
129 struct task_struct *tsk)
130{
131 unsigned int cpu = smp_processor_id();
132 unsigned long flags;
133 local_irq_save(flags);
134
135 /* Check if our ASID is of an older version and thus invalid */
136 if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK)
137 get_new_mmu_context(next, cpu);
138 write_c0_entryhi(cpu_asid(cpu, next));
139 TLBMISS_HANDLER_SETUP_PGD(next->pgd);
140
141 /*
142 * Mark current->active_mm as not "active" anymore.
143 * We don't want to mislead possible IPI tlb flush routines.
144 */
145 cpumask_clear_cpu(cpu, mm_cpumask(prev));
146 cpumask_set_cpu(cpu, mm_cpumask(next));
147
148 local_irq_restore(flags);
149}
150
151/*
152 * Destroy context related info for an mm_struct that is about
153 * to be put to rest.
154 */
155static inline void destroy_context(struct mm_struct *mm)
156{
157}
158
159#define deactivate_mm(tsk, mm) do { } while (0)
160
161/*
162 * After we have set current->mm to a new value, this activates
163 * the context for the new mm so we see the new mappings.
164 */
165static inline void
166activate_mm(struct mm_struct *prev, struct mm_struct *next)
167{
168 unsigned long flags;
169 unsigned int cpu = smp_processor_id();
170
171 local_irq_save(flags);
172
173 /* Unconditionally get a new ASID. */
174 get_new_mmu_context(next, cpu);
175
176 write_c0_entryhi(cpu_asid(cpu, next));
177 TLBMISS_HANDLER_SETUP_PGD(next->pgd);
178
179 /* mark mmu ownership change */
180 cpumask_clear_cpu(cpu, mm_cpumask(prev));
181 cpumask_set_cpu(cpu, mm_cpumask(next));
182
183 local_irq_restore(flags);
184}
185
186/*
187 * If mm is currently active_mm, we can't really drop it. Instead,
188 * we will get a new one for it.
189 */
190static inline void
191drop_mmu_context(struct mm_struct *mm, unsigned cpu)
192{
193 unsigned long flags;
194
195 local_irq_save(flags);
196
197 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) {
198 get_new_mmu_context(mm, cpu);
199 write_c0_entryhi(cpu_asid(cpu, mm));
200 } else {
201 /* will get a new context next time */
202 cpu_context(cpu, mm) = 0;
203 }
204 local_irq_restore(flags);
205}
206
207#endif /* _ASM_MMU_CONTEXT_H */