tjh.dev
Linux kernel mirror (for testing)
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1* Renesas Electronics SH EtherMAC
2
3This file provides information on what the device node for the SH EtherMAC
4interface contains.
5
6Required properties:
7- compatible: "renesas,gether-r8a7740" if the device is a part of R8A7740 SoC.
8 "renesas,ether-r8a7778" if the device is a part of R8A7778 SoC.
9 "renesas,ether-r8a7779" if the device is a part of R8A7779 SoC.
10 "renesas,ether-r8a7790" if the device is a part of R8A7790 SoC.
11 "renesas,ether-r8a7791" if the device is a part of R8A7791 SoC.
12 "renesas,ether-r7s72100" if the device is a part of R7S72100 SoC.
13- reg: offset and length of (1) the E-DMAC/feLic register block (required),
14 (2) the TSU register block (optional).
15- interrupts: interrupt specifier for the sole interrupt.
16- phy-mode: see ethernet.txt file in the same directory.
17- phy-handle: see ethernet.txt file in the same directory.
18- #address-cells: number of address cells for the MDIO bus, must be equal to 1.
19- #size-cells: number of size cells on the MDIO bus, must be equal to 0.
20- clocks: clock phandle and specifier pair.
21- pinctrl-0: phandle, referring to a default pin configuration node.
22
23Optional properties:
24- interrupt-parent: the phandle for the interrupt controller that services
25 interrupts for this device.
26- pinctrl-names: pin configuration state name ("default").
27- renesas,no-ether-link: boolean, specify when a board does not provide a proper
28 Ether LINK signal.
29- renesas,ether-link-active-low: boolean, specify when the Ether LINK signal is
30 active-low instead of normal active-high.
31
32Example (Lager board):
33
34 ethernet@ee700000 {
35 compatible = "renesas,ether-r8a7790";
36 reg = <0 0xee700000 0 0x400>;
37 interrupt-parent = <&gic>;
38 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
39 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
40 phy-mode = "rmii";
41 phy-handle = <&phy1>;
42 pinctrl-0 = <ðer_pins>;
43 pinctrl-names = "default";
44 renesas,ether-link-active-low;
45 #address-cells = <1>;
46 #size-cells = <0>;
47
48 phy1: ethernet-phy@1 {
49 reg = <1>;
50 interrupt-parent = <&irqc0>;
51 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
52 pinctrl-0 = <&phy1_pins>;
53 pinctrl-names = "default";
54 };
55 };