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1/*
2 * Driver for the Synopsys DesignWare DMA Controller
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 * Copyright (C) 2010-2011 ST Microelectronics
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef DW_DMAC_H
12#define DW_DMAC_H
13
14#include <linux/dmaengine.h>
15
16/**
17 * struct dw_dma_slave - Controller-specific information about a slave
18 *
19 * @dma_dev: required DMA master device. Depricated.
20 * @bus_id: name of this device channel, not just a device name since
21 * devices may have more than one channel e.g. "foo_tx"
22 * @cfg_hi: Platform-specific initializer for the CFG_HI register
23 * @cfg_lo: Platform-specific initializer for the CFG_LO register
24 * @src_master: src master for transfers on allocated channel.
25 * @dst_master: dest master for transfers on allocated channel.
26 */
27struct dw_dma_slave {
28 struct device *dma_dev;
29 u32 cfg_hi;
30 u32 cfg_lo;
31 u8 src_master;
32 u8 dst_master;
33};
34
35/**
36 * struct dw_dma_platform_data - Controller configuration parameters
37 * @nr_channels: Number of channels supported by hardware (max 8)
38 * @is_private: The device channels should be marked as private and not for
39 * by the general purpose DMA channel allocator.
40 * @chan_allocation_order: Allocate channels starting from 0 or 7
41 * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
42 * @block_size: Maximum block size supported by the controller
43 * @nr_masters: Number of AHB masters supported by the controller
44 * @data_width: Maximum data width supported by hardware per AHB master
45 * (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
46 */
47struct dw_dma_platform_data {
48 unsigned int nr_channels;
49 bool is_private;
50#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
51#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
52 unsigned char chan_allocation_order;
53#define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */
54#define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */
55 unsigned char chan_priority;
56 unsigned short block_size;
57 unsigned char nr_masters;
58 unsigned char data_width[4];
59};
60
61/* bursts size */
62enum dw_dma_msize {
63 DW_DMA_MSIZE_1,
64 DW_DMA_MSIZE_4,
65 DW_DMA_MSIZE_8,
66 DW_DMA_MSIZE_16,
67 DW_DMA_MSIZE_32,
68 DW_DMA_MSIZE_64,
69 DW_DMA_MSIZE_128,
70 DW_DMA_MSIZE_256,
71};
72
73/* Platform-configurable bits in CFG_HI */
74#define DWC_CFGH_FCMODE (1 << 0)
75#define DWC_CFGH_FIFO_MODE (1 << 1)
76#define DWC_CFGH_PROTCTL(x) ((x) << 2)
77#define DWC_CFGH_SRC_PER(x) ((x) << 7)
78#define DWC_CFGH_DST_PER(x) ((x) << 11)
79
80/* Platform-configurable bits in CFG_LO */
81#define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */
82#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12)
83#define DWC_CFGL_LOCK_CH_XACT (2 << 12)
84#define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */
85#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
86#define DWC_CFGL_LOCK_BUS_XACT (2 << 14)
87#define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */
88#define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */
89#define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */
90#define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */
91
92/* DMA API extensions */
93struct dw_cyclic_desc {
94 struct dw_desc **desc;
95 unsigned long periods;
96 void (*period_callback)(void *param);
97 void *period_callback_param;
98};
99
100struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
101 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
102 enum dma_transfer_direction direction);
103void dw_dma_cyclic_free(struct dma_chan *chan);
104int dw_dma_cyclic_start(struct dma_chan *chan);
105void dw_dma_cyclic_stop(struct dma_chan *chan);
106
107dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);
108
109dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);
110
111#endif /* DW_DMAC_H */