tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1Tegra SOC USB PHY
2
3The device node for Tegra SOC USB PHY:
4
5Required properties :
6 - compatible : Should be "nvidia,tegra<chip>-usb-phy".
7 - reg : Defines the following set of registers, in the order listed:
8 - The PHY's own register set.
9 Always present.
10 - The register set of the PHY containing the UTMI pad control registers.
11 Present if-and-only-if phy_type == utmi.
12 - phy_type : Should be one of "utmi", "ulpi" or "hsic".
13 - clocks : Defines the clocks listed in the clock-names property.
14 - clock-names : The following clock names must be present:
15 - reg: The clock needed to access the PHY's own registers. This is the
16 associated EHCI controller's clock. Always present.
17 - pll_u: PLL_U. Always present.
18 - timer: The timeout clock (clk_m). Present if phy_type == utmi.
19 - utmi-pads: The clock needed to access the UTMI pad control registers.
20 Present if phy_type == utmi.
21 - ulpi-link: The clock Tegra provides to the ULPI PHY (cdev2).
22 Present if phy_type == ulpi, and ULPI link mode is in use.
23
24Required properties for phy_type == ulpi:
25 - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
26
27Required PHY timing params for utmi phy, for all chips:
28 - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before
29 start of sync launches RxActive
30 - nvidia,elastic-limit : Variable FIFO Depth of elastic input store
31 - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait
32 before declare IDLE.
33 - nvidia,term-range-adj : Range adjusment on terminations
34 - Either one of the following for HS driver output control:
35 - nvidia,xcvr-setup : integer, uses the provided value.
36 - nvidia,xcvr-setup-use-fuses : boolean, indicates that the value is read
37 from the on-chip fuses
38 If both are provided, nvidia,xcvr-setup-use-fuses takes precedence.
39 - nvidia,xcvr-lsfslew : LS falling slew rate control.
40 - nvidia,xcvr-lsrslew : LS rising slew rate control.
41
42Required PHY timing params for utmi phy, only on Tegra30 and above:
43 - nvidia,xcvr-hsslew : HS slew rate control.
44 - nvidia,hssquelch-level : HS squelch detector level.
45 - nvidia,hsdiscon-level : HS disconnect detector level.
46
47Optional properties:
48 - nvidia,has-legacy-mode : boolean indicates whether this controller can
49 operate in legacy mode (as APX 2500 / 2600). In legacy mode some
50 registers are accessed through the APB_MISC base address instead of
51 the USB controller.
52 - nvidia,is-wired : boolean. Indicates whether we can do certain kind of power
53 optimizations for the devices that are always connected. e.g. modem.
54 - dr_mode : dual role mode. Indicates the working mode for the PHY. Can be
55 "host", "peripheral", or "otg". Defaults to "host" if not defined.
56 host means this is a host controller
57 peripheral means it is device controller
58 otg means it can operate as either ("on the go")
59
60VBUS control (required for dr_mode == otg, optional for dr_mode == host):
61 - vbus-supply: regulator for VBUS