tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * max77693-irq.c - Interrupt controller support for MAX77693
3 *
4 * Copyright (C) 2012 Samsung Electronics Co.Ltd
5 * SangYoung Son <hello.son@samsung.com>
6 *
7 * This program is not provided / owned by Maxim Integrated Products.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 * This driver is based on max8997-irq.c
24 */
25
26#include <linux/err.h>
27#include <linux/irq.h>
28#include <linux/interrupt.h>
29#include <linux/module.h>
30#include <linux/irqdomain.h>
31#include <linux/mfd/max77693.h>
32#include <linux/mfd/max77693-private.h>
33
34static const u8 max77693_mask_reg[] = {
35 [LED_INT] = MAX77693_LED_REG_FLASH_INT_MASK,
36 [TOPSYS_INT] = MAX77693_PMIC_REG_TOPSYS_INT_MASK,
37 [CHG_INT] = MAX77693_CHG_REG_CHG_INT_MASK,
38 [MUIC_INT1] = MAX77693_MUIC_REG_INTMASK1,
39 [MUIC_INT2] = MAX77693_MUIC_REG_INTMASK2,
40 [MUIC_INT3] = MAX77693_MUIC_REG_INTMASK3,
41};
42
43static struct regmap *max77693_get_regmap(struct max77693_dev *max77693,
44 enum max77693_irq_source src)
45{
46 switch (src) {
47 case LED_INT ... CHG_INT:
48 return max77693->regmap;
49 case MUIC_INT1 ... MUIC_INT3:
50 return max77693->regmap_muic;
51 default:
52 return ERR_PTR(-EINVAL);
53 }
54}
55
56struct max77693_irq_data {
57 int mask;
58 enum max77693_irq_source group;
59};
60
61#define DECLARE_IRQ(idx, _group, _mask) \
62 [(idx)] = { .group = (_group), .mask = (_mask) }
63static const struct max77693_irq_data max77693_irqs[] = {
64 DECLARE_IRQ(MAX77693_LED_IRQ_FLED2_OPEN, LED_INT, 1 << 0),
65 DECLARE_IRQ(MAX77693_LED_IRQ_FLED2_SHORT, LED_INT, 1 << 1),
66 DECLARE_IRQ(MAX77693_LED_IRQ_FLED1_OPEN, LED_INT, 1 << 2),
67 DECLARE_IRQ(MAX77693_LED_IRQ_FLED1_SHORT, LED_INT, 1 << 3),
68 DECLARE_IRQ(MAX77693_LED_IRQ_MAX_FLASH, LED_INT, 1 << 4),
69
70 DECLARE_IRQ(MAX77693_TOPSYS_IRQ_T120C_INT, TOPSYS_INT, 1 << 0),
71 DECLARE_IRQ(MAX77693_TOPSYS_IRQ_T140C_INT, TOPSYS_INT, 1 << 1),
72 DECLARE_IRQ(MAX77693_TOPSYS_IRQ_LOWSYS_INT, TOPSYS_INT, 1 << 3),
73
74 DECLARE_IRQ(MAX77693_CHG_IRQ_BYP_I, CHG_INT, 1 << 0),
75 DECLARE_IRQ(MAX77693_CHG_IRQ_THM_I, CHG_INT, 1 << 2),
76 DECLARE_IRQ(MAX77693_CHG_IRQ_BAT_I, CHG_INT, 1 << 3),
77 DECLARE_IRQ(MAX77693_CHG_IRQ_CHG_I, CHG_INT, 1 << 4),
78 DECLARE_IRQ(MAX77693_CHG_IRQ_CHGIN_I, CHG_INT, 1 << 6),
79
80 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC, MUIC_INT1, 1 << 0),
81 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC_LOW, MUIC_INT1, 1 << 1),
82 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC_ERR, MUIC_INT1, 1 << 2),
83 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC1K, MUIC_INT1, 1 << 3),
84
85 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_CHGTYP, MUIC_INT2, 1 << 0),
86 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_CHGDETREUN, MUIC_INT2, 1 << 1),
87 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_DCDTMR, MUIC_INT2, 1 << 2),
88 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_DXOVP, MUIC_INT2, 1 << 3),
89 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_VBVOLT, MUIC_INT2, 1 << 4),
90 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_VIDRM, MUIC_INT2, 1 << 5),
91
92 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_EOC, MUIC_INT3, 1 << 0),
93 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_CGMBC, MUIC_INT3, 1 << 1),
94 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_OVP, MUIC_INT3, 1 << 2),
95 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR, MUIC_INT3, 1 << 3),
96 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_CHG_ENABLED, MUIC_INT3, 1 << 4),
97 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_BAT_DET, MUIC_INT3, 1 << 5),
98};
99
100static void max77693_irq_lock(struct irq_data *data)
101{
102 struct max77693_dev *max77693 = irq_get_chip_data(data->irq);
103
104 mutex_lock(&max77693->irqlock);
105}
106
107static void max77693_irq_sync_unlock(struct irq_data *data)
108{
109 struct max77693_dev *max77693 = irq_get_chip_data(data->irq);
110 int i;
111
112 for (i = 0; i < MAX77693_IRQ_GROUP_NR; i++) {
113 u8 mask_reg = max77693_mask_reg[i];
114 struct regmap *map = max77693_get_regmap(max77693, i);
115
116 if (mask_reg == MAX77693_REG_INVALID ||
117 IS_ERR_OR_NULL(map))
118 continue;
119 max77693->irq_masks_cache[i] = max77693->irq_masks_cur[i];
120
121 max77693_write_reg(map, max77693_mask_reg[i],
122 max77693->irq_masks_cur[i]);
123 }
124
125 mutex_unlock(&max77693->irqlock);
126}
127
128static const inline struct max77693_irq_data *
129irq_to_max77693_irq(struct max77693_dev *max77693, int irq)
130{
131 struct irq_data *data = irq_get_irq_data(irq);
132 return &max77693_irqs[data->hwirq];
133}
134
135static void max77693_irq_mask(struct irq_data *data)
136{
137 struct max77693_dev *max77693 = irq_get_chip_data(data->irq);
138 const struct max77693_irq_data *irq_data =
139 irq_to_max77693_irq(max77693, data->irq);
140
141 if (irq_data->group >= MAX77693_IRQ_GROUP_NR)
142 return;
143
144 if (irq_data->group >= MUIC_INT1 && irq_data->group <= MUIC_INT3)
145 max77693->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
146 else
147 max77693->irq_masks_cur[irq_data->group] |= irq_data->mask;
148}
149
150static void max77693_irq_unmask(struct irq_data *data)
151{
152 struct max77693_dev *max77693 = irq_get_chip_data(data->irq);
153 const struct max77693_irq_data *irq_data =
154 irq_to_max77693_irq(max77693, data->irq);
155
156 if (irq_data->group >= MAX77693_IRQ_GROUP_NR)
157 return;
158
159 if (irq_data->group >= MUIC_INT1 && irq_data->group <= MUIC_INT3)
160 max77693->irq_masks_cur[irq_data->group] |= irq_data->mask;
161 else
162 max77693->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
163}
164
165static struct irq_chip max77693_irq_chip = {
166 .name = "max77693",
167 .irq_bus_lock = max77693_irq_lock,
168 .irq_bus_sync_unlock = max77693_irq_sync_unlock,
169 .irq_mask = max77693_irq_mask,
170 .irq_unmask = max77693_irq_unmask,
171};
172
173#define MAX77693_IRQSRC_CHG (1 << 0)
174#define MAX77693_IRQSRC_TOP (1 << 1)
175#define MAX77693_IRQSRC_FLASH (1 << 2)
176#define MAX77693_IRQSRC_MUIC (1 << 3)
177static irqreturn_t max77693_irq_thread(int irq, void *data)
178{
179 struct max77693_dev *max77693 = data;
180 u8 irq_reg[MAX77693_IRQ_GROUP_NR] = {};
181 u8 irq_src;
182 int ret;
183 int i, cur_irq;
184
185 ret = max77693_read_reg(max77693->regmap, MAX77693_PMIC_REG_INTSRC,
186 &irq_src);
187 if (ret < 0) {
188 dev_err(max77693->dev, "Failed to read interrupt source: %d\n",
189 ret);
190 return IRQ_NONE;
191 }
192
193 if (irq_src & MAX77693_IRQSRC_CHG)
194 /* CHG_INT */
195 ret = max77693_read_reg(max77693->regmap, MAX77693_CHG_REG_CHG_INT,
196 &irq_reg[CHG_INT]);
197
198 if (irq_src & MAX77693_IRQSRC_TOP)
199 /* TOPSYS_INT */
200 ret = max77693_read_reg(max77693->regmap,
201 MAX77693_PMIC_REG_TOPSYS_INT, &irq_reg[TOPSYS_INT]);
202
203 if (irq_src & MAX77693_IRQSRC_FLASH)
204 /* LED_INT */
205 ret = max77693_read_reg(max77693->regmap,
206 MAX77693_LED_REG_FLASH_INT, &irq_reg[LED_INT]);
207
208 if (irq_src & MAX77693_IRQSRC_MUIC)
209 /* MUIC INT1 ~ INT3 */
210 max77693_bulk_read(max77693->regmap_muic, MAX77693_MUIC_REG_INT1,
211 MAX77693_NUM_IRQ_MUIC_REGS, &irq_reg[MUIC_INT1]);
212
213 /* Apply masking */
214 for (i = 0; i < MAX77693_IRQ_GROUP_NR; i++) {
215 if (i >= MUIC_INT1 && i <= MUIC_INT3)
216 irq_reg[i] &= max77693->irq_masks_cur[i];
217 else
218 irq_reg[i] &= ~max77693->irq_masks_cur[i];
219 }
220
221 /* Report */
222 for (i = 0; i < MAX77693_IRQ_NR; i++) {
223 if (irq_reg[max77693_irqs[i].group] & max77693_irqs[i].mask) {
224 cur_irq = irq_find_mapping(max77693->irq_domain, i);
225 if (cur_irq)
226 handle_nested_irq(cur_irq);
227 }
228 }
229
230 return IRQ_HANDLED;
231}
232
233int max77693_irq_resume(struct max77693_dev *max77693)
234{
235 if (max77693->irq)
236 max77693_irq_thread(0, max77693);
237
238 return 0;
239}
240
241static int max77693_irq_domain_map(struct irq_domain *d, unsigned int irq,
242 irq_hw_number_t hw)
243{
244 struct max77693_dev *max77693 = d->host_data;
245
246 irq_set_chip_data(irq, max77693);
247 irq_set_chip_and_handler(irq, &max77693_irq_chip, handle_edge_irq);
248 irq_set_nested_thread(irq, 1);
249#ifdef CONFIG_ARM
250 set_irq_flags(irq, IRQF_VALID);
251#else
252 irq_set_noprobe(irq);
253#endif
254 return 0;
255}
256
257static struct irq_domain_ops max77693_irq_domain_ops = {
258 .map = max77693_irq_domain_map,
259};
260
261int max77693_irq_init(struct max77693_dev *max77693)
262{
263 struct irq_domain *domain;
264 int i;
265 int ret = 0;
266 u8 intsrc_mask;
267
268 mutex_init(&max77693->irqlock);
269
270 /* Mask individual interrupt sources */
271 for (i = 0; i < MAX77693_IRQ_GROUP_NR; i++) {
272 struct regmap *map;
273 /* MUIC IRQ 0:MASK 1:NOT MASK */
274 /* Other IRQ 1:MASK 0:NOT MASK */
275 if (i >= MUIC_INT1 && i <= MUIC_INT3) {
276 max77693->irq_masks_cur[i] = 0x00;
277 max77693->irq_masks_cache[i] = 0x00;
278 } else {
279 max77693->irq_masks_cur[i] = 0xff;
280 max77693->irq_masks_cache[i] = 0xff;
281 }
282 map = max77693_get_regmap(max77693, i);
283
284 if (IS_ERR_OR_NULL(map))
285 continue;
286 if (max77693_mask_reg[i] == MAX77693_REG_INVALID)
287 continue;
288 if (i >= MUIC_INT1 && i <= MUIC_INT3)
289 max77693_write_reg(map, max77693_mask_reg[i], 0x00);
290 else
291 max77693_write_reg(map, max77693_mask_reg[i], 0xff);
292 }
293
294 domain = irq_domain_add_linear(NULL, MAX77693_IRQ_NR,
295 &max77693_irq_domain_ops, max77693);
296 if (!domain) {
297 dev_err(max77693->dev, "could not create irq domain\n");
298 ret = -ENODEV;
299 goto err_irq;
300 }
301 max77693->irq_domain = domain;
302
303 /* Unmask max77693 interrupt */
304 ret = max77693_read_reg(max77693->regmap,
305 MAX77693_PMIC_REG_INTSRC_MASK, &intsrc_mask);
306 if (ret < 0) {
307 dev_err(max77693->dev, "fail to read PMIC register\n");
308 goto err_irq;
309 }
310
311 intsrc_mask &= ~(MAX77693_IRQSRC_CHG);
312 intsrc_mask &= ~(MAX77693_IRQSRC_FLASH);
313 intsrc_mask &= ~(MAX77693_IRQSRC_MUIC);
314 ret = max77693_write_reg(max77693->regmap,
315 MAX77693_PMIC_REG_INTSRC_MASK, intsrc_mask);
316 if (ret < 0) {
317 dev_err(max77693->dev, "fail to write PMIC register\n");
318 goto err_irq;
319 }
320
321 ret = request_threaded_irq(max77693->irq, NULL, max77693_irq_thread,
322 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
323 "max77693-irq", max77693);
324 if (ret)
325 dev_err(max77693->dev, "Failed to request IRQ %d: %d\n",
326 max77693->irq, ret);
327
328err_irq:
329 return ret;
330}
331
332void max77693_irq_exit(struct max77693_dev *max77693)
333{
334 if (max77693->irq)
335 free_irq(max77693->irq, max77693);
336}