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1/* 2 * Blackfin On-Chip Sport Emulated UART Driver 3 * 4 * Copyright 2006-2009 Analog Devices Inc. 5 * 6 * Enter bugs at http://blackfin.uclinux.org/ 7 * 8 * Licensed under the GPL-2 or later. 9 */ 10 11/* 12 * This driver and the hardware supported are in term of EE-191 of ADI. 13 * http://www.analog.com/static/imported-files/application_notes/EE191.pdf 14 * This application note describe how to implement a UART on a Sharc DSP, 15 * but this driver is implemented on Blackfin Processor. 16 * Transmit Frame Sync is not used by this driver to transfer data out. 17 */ 18 19/* #define DEBUG */ 20 21#define DRV_NAME "bfin-sport-uart" 22#define DEVICE_NAME "ttySS" 23#define pr_fmt(fmt) DRV_NAME ": " fmt 24 25#include <linux/module.h> 26#include <linux/ioport.h> 27#include <linux/io.h> 28#include <linux/init.h> 29#include <linux/console.h> 30#include <linux/sysrq.h> 31#include <linux/slab.h> 32#include <linux/platform_device.h> 33#include <linux/tty.h> 34#include <linux/tty_flip.h> 35#include <linux/serial_core.h> 36 37#include <asm/bfin_sport.h> 38#include <asm/delay.h> 39#include <asm/portmux.h> 40 41#include "bfin_sport_uart.h" 42 43struct sport_uart_port { 44 struct uart_port port; 45 int err_irq; 46 unsigned short csize; 47 unsigned short rxmask; 48 unsigned short txmask1; 49 unsigned short txmask2; 50 unsigned char stopb; 51/* unsigned char parib; */ 52#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS 53 int cts_pin; 54 int rts_pin; 55#endif 56}; 57 58static int sport_uart_tx_chars(struct sport_uart_port *up); 59static void sport_stop_tx(struct uart_port *port); 60 61static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value) 62{ 63 pr_debug("%s value:%x, mask1=0x%x, mask2=0x%x\n", __func__, value, 64 up->txmask1, up->txmask2); 65 66 /* Place Start and Stop bits */ 67 __asm__ __volatile__ ( 68 "%[val] <<= 1;" 69 "%[val] = %[val] & %[mask1];" 70 "%[val] = %[val] | %[mask2];" 71 : [val]"+d"(value) 72 : [mask1]"d"(up->txmask1), [mask2]"d"(up->txmask2) 73 : "ASTAT" 74 ); 75 pr_debug("%s value:%x\n", __func__, value); 76 77 SPORT_PUT_TX(up, value); 78} 79 80static inline unsigned char rx_one_byte(struct sport_uart_port *up) 81{ 82 unsigned int value; 83 unsigned char extract; 84 u32 tmp_mask1, tmp_mask2, tmp_shift, tmp; 85 86 if ((up->csize + up->stopb) > 7) 87 value = SPORT_GET_RX32(up); 88 else 89 value = SPORT_GET_RX(up); 90 91 pr_debug("%s value:%x, cs=%d, mask=0x%x\n", __func__, value, 92 up->csize, up->rxmask); 93 94 /* Extract data */ 95 __asm__ __volatile__ ( 96 "%[extr] = 0;" 97 "%[mask1] = %[rxmask];" 98 "%[mask2] = 0x0200(Z);" 99 "%[shift] = 0;" 100 "LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];" 101 ".Lloop_s:" 102 "%[tmp] = extract(%[val], %[mask1].L)(Z);" 103 "%[tmp] <<= %[shift];" 104 "%[extr] = %[extr] | %[tmp];" 105 "%[mask1] = %[mask1] - %[mask2];" 106 ".Lloop_e:" 107 "%[shift] += 1;" 108 : [extr]"=&d"(extract), [shift]"=&d"(tmp_shift), [tmp]"=&d"(tmp), 109 [mask1]"=&d"(tmp_mask1), [mask2]"=&d"(tmp_mask2) 110 : [val]"d"(value), [rxmask]"d"(up->rxmask), [lc]"a"(up->csize) 111 : "ASTAT", "LB0", "LC0", "LT0" 112 ); 113 114 pr_debug(" extract:%x\n", extract); 115 return extract; 116} 117 118static int sport_uart_setup(struct sport_uart_port *up, int size, int baud_rate) 119{ 120 int tclkdiv, rclkdiv; 121 unsigned int sclk = get_sclk(); 122 123 /* Set TCR1 and TCR2, TFSR is not enabled for uart */ 124 SPORT_PUT_TCR1(up, (LATFS | ITFS | TFSR | TLSBIT | ITCLK)); 125 SPORT_PUT_TCR2(up, size + 1); 126 pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up)); 127 128 /* Set RCR1 and RCR2 */ 129 SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK)); 130 SPORT_PUT_RCR2(up, (size + 1) * 2 - 1); 131 pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up)); 132 133 tclkdiv = sclk / (2 * baud_rate) - 1; 134 /* The actual uart baud rate of devices vary between +/-2%. The sport 135 * RX sample rate should be faster than the double of the worst case, 136 * otherwise, wrong data are received. So, set sport RX clock to be 137 * 3% faster. 138 */ 139 rclkdiv = sclk / (2 * baud_rate * 2 * 97 / 100) - 1; 140 SPORT_PUT_TCLKDIV(up, tclkdiv); 141 SPORT_PUT_RCLKDIV(up, rclkdiv); 142 SSYNC(); 143 pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, rclkdiv:%d\n", 144 __func__, sclk, baud_rate, tclkdiv, rclkdiv); 145 146 return 0; 147} 148 149static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id) 150{ 151 struct sport_uart_port *up = dev_id; 152 struct tty_port *port = &up->port.state->port; 153 unsigned int ch; 154 155 spin_lock(&up->port.lock); 156 157 while (SPORT_GET_STAT(up) & RXNE) { 158 ch = rx_one_byte(up); 159 up->port.icount.rx++; 160 161 if (!uart_handle_sysrq_char(&up->port, ch)) 162 tty_insert_flip_char(port, ch, TTY_NORMAL); 163 } 164 165 spin_unlock(&up->port.lock); 166 167 /* XXX this won't deadlock with lowlat? */ 168 tty_flip_buffer_push(port); 169 170 return IRQ_HANDLED; 171} 172 173static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id) 174{ 175 struct sport_uart_port *up = dev_id; 176 177 spin_lock(&up->port.lock); 178 sport_uart_tx_chars(up); 179 spin_unlock(&up->port.lock); 180 181 return IRQ_HANDLED; 182} 183 184static irqreturn_t sport_uart_err_irq(int irq, void *dev_id) 185{ 186 struct sport_uart_port *up = dev_id; 187 unsigned int stat = SPORT_GET_STAT(up); 188 189 spin_lock(&up->port.lock); 190 191 /* Overflow in RX FIFO */ 192 if (stat & ROVF) { 193 up->port.icount.overrun++; 194 tty_insert_flip_char(&up->port.state->port, 0, TTY_OVERRUN); 195 SPORT_PUT_STAT(up, ROVF); /* Clear ROVF bit */ 196 } 197 /* These should not happen */ 198 if (stat & (TOVF | TUVF | RUVF)) { 199 pr_err("SPORT Error:%s %s %s\n", 200 (stat & TOVF) ? "TX overflow" : "", 201 (stat & TUVF) ? "TX underflow" : "", 202 (stat & RUVF) ? "RX underflow" : ""); 203 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN); 204 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN); 205 } 206 SSYNC(); 207 208 spin_unlock(&up->port.lock); 209 /* XXX we don't push the overrun bit to TTY? */ 210 211 return IRQ_HANDLED; 212} 213 214#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS 215static unsigned int sport_get_mctrl(struct uart_port *port) 216{ 217 struct sport_uart_port *up = (struct sport_uart_port *)port; 218 if (up->cts_pin < 0) 219 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 220 221 /* CTS PIN is negative assertive. */ 222 if (SPORT_UART_GET_CTS(up)) 223 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 224 else 225 return TIOCM_DSR | TIOCM_CAR; 226} 227 228static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl) 229{ 230 struct sport_uart_port *up = (struct sport_uart_port *)port; 231 if (up->rts_pin < 0) 232 return; 233 234 /* RTS PIN is negative assertive. */ 235 if (mctrl & TIOCM_RTS) 236 SPORT_UART_ENABLE_RTS(up); 237 else 238 SPORT_UART_DISABLE_RTS(up); 239} 240 241/* 242 * Handle any change of modem status signal. 243 */ 244static irqreturn_t sport_mctrl_cts_int(int irq, void *dev_id) 245{ 246 struct sport_uart_port *up = (struct sport_uart_port *)dev_id; 247 unsigned int status; 248 249 status = sport_get_mctrl(&up->port); 250 uart_handle_cts_change(&up->port, status & TIOCM_CTS); 251 252 return IRQ_HANDLED; 253} 254#else 255static unsigned int sport_get_mctrl(struct uart_port *port) 256{ 257 pr_debug("%s enter\n", __func__); 258 return TIOCM_CTS | TIOCM_CD | TIOCM_DSR; 259} 260 261static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl) 262{ 263 pr_debug("%s enter\n", __func__); 264} 265#endif 266 267/* Reqeust IRQ, Setup clock */ 268static int sport_startup(struct uart_port *port) 269{ 270 struct sport_uart_port *up = (struct sport_uart_port *)port; 271 int ret; 272 273 pr_debug("%s enter\n", __func__); 274 ret = request_irq(up->port.irq, sport_uart_rx_irq, 0, 275 "SPORT_UART_RX", up); 276 if (ret) { 277 dev_err(port->dev, "unable to request SPORT RX interrupt\n"); 278 return ret; 279 } 280 281 ret = request_irq(up->port.irq+1, sport_uart_tx_irq, 0, 282 "SPORT_UART_TX", up); 283 if (ret) { 284 dev_err(port->dev, "unable to request SPORT TX interrupt\n"); 285 goto fail1; 286 } 287 288 ret = request_irq(up->err_irq, sport_uart_err_irq, 0, 289 "SPORT_UART_STATUS", up); 290 if (ret) { 291 dev_err(port->dev, "unable to request SPORT status interrupt\n"); 292 goto fail2; 293 } 294 295#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS 296 if (up->cts_pin >= 0) { 297 if (request_irq(gpio_to_irq(up->cts_pin), 298 sport_mctrl_cts_int, 299 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | 300 0, "BFIN_SPORT_UART_CTS", up)) { 301 up->cts_pin = -1; 302 dev_info(port->dev, "Unable to attach BlackFin UART over SPORT CTS interrupt. So, disable it.\n"); 303 } 304 } 305 if (up->rts_pin >= 0) { 306 if (gpio_request(up->rts_pin, DRV_NAME)) { 307 dev_info(port->dev, "fail to request RTS PIN at GPIO_%d\n", up->rts_pin); 308 up->rts_pin = -1; 309 } else 310 gpio_direction_output(up->rts_pin, 0); 311 } 312#endif 313 314 return 0; 315 fail2: 316 free_irq(up->port.irq+1, up); 317 fail1: 318 free_irq(up->port.irq, up); 319 320 return ret; 321} 322 323/* 324 * sport_uart_tx_chars 325 * 326 * ret 1 means need to enable sport. 327 * ret 0 means do nothing. 328 */ 329static int sport_uart_tx_chars(struct sport_uart_port *up) 330{ 331 struct circ_buf *xmit = &up->port.state->xmit; 332 333 if (SPORT_GET_STAT(up) & TXF) 334 return 0; 335 336 if (up->port.x_char) { 337 tx_one_byte(up, up->port.x_char); 338 up->port.icount.tx++; 339 up->port.x_char = 0; 340 return 1; 341 } 342 343 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 344 /* The waiting loop to stop SPORT TX from TX interrupt is 345 * too long. This may block SPORT RX interrupts and cause 346 * RX FIFO overflow. So, do stop sport TX only after the last 347 * char in TX FIFO is moved into the shift register. 348 */ 349 if (SPORT_GET_STAT(up) & TXHRE) 350 sport_stop_tx(&up->port); 351 return 0; 352 } 353 354 while(!(SPORT_GET_STAT(up) & TXF) && !uart_circ_empty(xmit)) { 355 tx_one_byte(up, xmit->buf[xmit->tail]); 356 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1); 357 up->port.icount.tx++; 358 } 359 360 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 361 uart_write_wakeup(&up->port); 362 363 return 1; 364} 365 366static unsigned int sport_tx_empty(struct uart_port *port) 367{ 368 struct sport_uart_port *up = (struct sport_uart_port *)port; 369 unsigned int stat; 370 371 stat = SPORT_GET_STAT(up); 372 pr_debug("%s stat:%04x\n", __func__, stat); 373 if (stat & TXHRE) { 374 return TIOCSER_TEMT; 375 } else 376 return 0; 377} 378 379static void sport_stop_tx(struct uart_port *port) 380{ 381 struct sport_uart_port *up = (struct sport_uart_port *)port; 382 383 pr_debug("%s enter\n", __func__); 384 385 if (!(SPORT_GET_TCR1(up) & TSPEN)) 386 return; 387 388 /* Although the hold register is empty, last byte is still in shift 389 * register and not sent out yet. So, put a dummy data into TX FIFO. 390 * Then, sport tx stops when last byte is shift out and the dummy 391 * data is moved into the shift register. 392 */ 393 SPORT_PUT_TX(up, 0xffff); 394 while (!(SPORT_GET_STAT(up) & TXHRE)) 395 cpu_relax(); 396 397 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN)); 398 SSYNC(); 399 400 return; 401} 402 403static void sport_start_tx(struct uart_port *port) 404{ 405 struct sport_uart_port *up = (struct sport_uart_port *)port; 406 407 pr_debug("%s enter\n", __func__); 408 409 /* Write data into SPORT FIFO before enable SPROT to transmit */ 410 if (sport_uart_tx_chars(up)) { 411 /* Enable transmit, then an interrupt will generated */ 412 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN)); 413 SSYNC(); 414 } 415 416 pr_debug("%s exit\n", __func__); 417} 418 419static void sport_stop_rx(struct uart_port *port) 420{ 421 struct sport_uart_port *up = (struct sport_uart_port *)port; 422 423 pr_debug("%s enter\n", __func__); 424 /* Disable sport to stop rx */ 425 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN)); 426 SSYNC(); 427} 428 429static void sport_enable_ms(struct uart_port *port) 430{ 431 pr_debug("%s enter\n", __func__); 432} 433 434static void sport_break_ctl(struct uart_port *port, int break_state) 435{ 436 pr_debug("%s enter\n", __func__); 437} 438 439static void sport_shutdown(struct uart_port *port) 440{ 441 struct sport_uart_port *up = (struct sport_uart_port *)port; 442 443 dev_dbg(port->dev, "%s enter\n", __func__); 444 445 /* Disable sport */ 446 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN)); 447 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN)); 448 SSYNC(); 449 450 free_irq(up->port.irq, up); 451 free_irq(up->port.irq+1, up); 452 free_irq(up->err_irq, up); 453#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS 454 if (up->cts_pin >= 0) 455 free_irq(gpio_to_irq(up->cts_pin), up); 456 if (up->rts_pin >= 0) 457 gpio_free(up->rts_pin); 458#endif 459} 460 461static const char *sport_type(struct uart_port *port) 462{ 463 struct sport_uart_port *up = (struct sport_uart_port *)port; 464 465 pr_debug("%s enter\n", __func__); 466 return up->port.type == PORT_BFIN_SPORT ? "BFIN-SPORT-UART" : NULL; 467} 468 469static void sport_release_port(struct uart_port *port) 470{ 471 pr_debug("%s enter\n", __func__); 472} 473 474static int sport_request_port(struct uart_port *port) 475{ 476 pr_debug("%s enter\n", __func__); 477 return 0; 478} 479 480static void sport_config_port(struct uart_port *port, int flags) 481{ 482 struct sport_uart_port *up = (struct sport_uart_port *)port; 483 484 pr_debug("%s enter\n", __func__); 485 up->port.type = PORT_BFIN_SPORT; 486} 487 488static int sport_verify_port(struct uart_port *port, struct serial_struct *ser) 489{ 490 pr_debug("%s enter\n", __func__); 491 return 0; 492} 493 494static void sport_set_termios(struct uart_port *port, 495 struct ktermios *termios, struct ktermios *old) 496{ 497 struct sport_uart_port *up = (struct sport_uart_port *)port; 498 unsigned long flags; 499 int i; 500 501 pr_debug("%s enter, c_cflag:%08x\n", __func__, termios->c_cflag); 502 503 switch (termios->c_cflag & CSIZE) { 504 case CS8: 505 up->csize = 8; 506 break; 507 case CS7: 508 up->csize = 7; 509 break; 510 case CS6: 511 up->csize = 6; 512 break; 513 case CS5: 514 up->csize = 5; 515 break; 516 default: 517 pr_warning("requested word length not supported\n"); 518 } 519 520 if (termios->c_cflag & CSTOPB) { 521 up->stopb = 1; 522 } 523 if (termios->c_cflag & PARENB) { 524 pr_warning("PAREN bits is not supported yet\n"); 525 /* up->parib = 1; */ 526 } 527 528 spin_lock_irqsave(&up->port.lock, flags); 529 530 port->read_status_mask = 0; 531 532 /* 533 * Characters to ignore 534 */ 535 port->ignore_status_mask = 0; 536 537 /* RX extract mask */ 538 up->rxmask = 0x01 | (((up->csize + up->stopb) * 2 - 1) << 0x8); 539 /* TX masks, 8 bit data and 1 bit stop for example: 540 * mask1 = b#0111111110 541 * mask2 = b#1000000000 542 */ 543 for (i = 0, up->txmask1 = 0; i < up->csize; i++) 544 up->txmask1 |= (1<<i); 545 up->txmask2 = (1<<i); 546 if (up->stopb) { 547 ++i; 548 up->txmask2 |= (1<<i); 549 } 550 up->txmask1 <<= 1; 551 up->txmask2 <<= 1; 552 /* uart baud rate */ 553 port->uartclk = uart_get_baud_rate(port, termios, old, 0, get_sclk()/16); 554 555 /* Disable UART */ 556 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN); 557 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN); 558 559 sport_uart_setup(up, up->csize + up->stopb, port->uartclk); 560 561 /* driver TX line high after config, one dummy data is 562 * necessary to stop sport after shift one byte 563 */ 564 SPORT_PUT_TX(up, 0xffff); 565 SPORT_PUT_TX(up, 0xffff); 566 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN)); 567 SSYNC(); 568 while (!(SPORT_GET_STAT(up) & TXHRE)) 569 cpu_relax(); 570 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN); 571 SSYNC(); 572 573 /* Port speed changed, update the per-port timeout. */ 574 uart_update_timeout(port, termios->c_cflag, port->uartclk); 575 576 /* Enable sport rx */ 577 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) | RSPEN); 578 SSYNC(); 579 580 spin_unlock_irqrestore(&up->port.lock, flags); 581} 582 583struct uart_ops sport_uart_ops = { 584 .tx_empty = sport_tx_empty, 585 .set_mctrl = sport_set_mctrl, 586 .get_mctrl = sport_get_mctrl, 587 .stop_tx = sport_stop_tx, 588 .start_tx = sport_start_tx, 589 .stop_rx = sport_stop_rx, 590 .enable_ms = sport_enable_ms, 591 .break_ctl = sport_break_ctl, 592 .startup = sport_startup, 593 .shutdown = sport_shutdown, 594 .set_termios = sport_set_termios, 595 .type = sport_type, 596 .release_port = sport_release_port, 597 .request_port = sport_request_port, 598 .config_port = sport_config_port, 599 .verify_port = sport_verify_port, 600}; 601 602#define BFIN_SPORT_UART_MAX_PORTS 4 603 604static struct sport_uart_port *bfin_sport_uart_ports[BFIN_SPORT_UART_MAX_PORTS]; 605 606#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE 607#define CLASS_BFIN_SPORT_CONSOLE "bfin-sport-console" 608 609static int __init 610sport_uart_console_setup(struct console *co, char *options) 611{ 612 struct sport_uart_port *up; 613 int baud = 57600; 614 int bits = 8; 615 int parity = 'n'; 616# ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS 617 int flow = 'r'; 618# else 619 int flow = 'n'; 620# endif 621 622 /* Check whether an invalid uart number has been specified */ 623 if (co->index < 0 || co->index >= BFIN_SPORT_UART_MAX_PORTS) 624 return -ENODEV; 625 626 up = bfin_sport_uart_ports[co->index]; 627 if (!up) 628 return -ENODEV; 629 630 if (options) 631 uart_parse_options(options, &baud, &parity, &bits, &flow); 632 633 return uart_set_options(&up->port, co, baud, parity, bits, flow); 634} 635 636static void sport_uart_console_putchar(struct uart_port *port, int ch) 637{ 638 struct sport_uart_port *up = (struct sport_uart_port *)port; 639 640 while (SPORT_GET_STAT(up) & TXF) 641 barrier(); 642 643 tx_one_byte(up, ch); 644} 645 646/* 647 * Interrupts are disabled on entering 648 */ 649static void 650sport_uart_console_write(struct console *co, const char *s, unsigned int count) 651{ 652 struct sport_uart_port *up = bfin_sport_uart_ports[co->index]; 653 unsigned long flags; 654 655 spin_lock_irqsave(&up->port.lock, flags); 656 657 if (SPORT_GET_TCR1(up) & TSPEN) 658 uart_console_write(&up->port, s, count, sport_uart_console_putchar); 659 else { 660 /* dummy data to start sport */ 661 while (SPORT_GET_STAT(up) & TXF) 662 barrier(); 663 SPORT_PUT_TX(up, 0xffff); 664 /* Enable transmit, then an interrupt will generated */ 665 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN)); 666 SSYNC(); 667 668 uart_console_write(&up->port, s, count, sport_uart_console_putchar); 669 670 /* Although the hold register is empty, last byte is still in shift 671 * register and not sent out yet. So, put a dummy data into TX FIFO. 672 * Then, sport tx stops when last byte is shift out and the dummy 673 * data is moved into the shift register. 674 */ 675 while (SPORT_GET_STAT(up) & TXF) 676 barrier(); 677 SPORT_PUT_TX(up, 0xffff); 678 while (!(SPORT_GET_STAT(up) & TXHRE)) 679 barrier(); 680 681 /* Stop sport tx transfer */ 682 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN)); 683 SSYNC(); 684 } 685 686 spin_unlock_irqrestore(&up->port.lock, flags); 687} 688 689static struct uart_driver sport_uart_reg; 690 691static struct console sport_uart_console = { 692 .name = DEVICE_NAME, 693 .write = sport_uart_console_write, 694 .device = uart_console_device, 695 .setup = sport_uart_console_setup, 696 .flags = CON_PRINTBUFFER, 697 .index = -1, 698 .data = &sport_uart_reg, 699}; 700 701#define SPORT_UART_CONSOLE (&sport_uart_console) 702#else 703#define SPORT_UART_CONSOLE NULL 704#endif /* CONFIG_SERIAL_BFIN_SPORT_CONSOLE */ 705 706 707static struct uart_driver sport_uart_reg = { 708 .owner = THIS_MODULE, 709 .driver_name = DRV_NAME, 710 .dev_name = DEVICE_NAME, 711 .major = 204, 712 .minor = 84, 713 .nr = BFIN_SPORT_UART_MAX_PORTS, 714 .cons = SPORT_UART_CONSOLE, 715}; 716 717#ifdef CONFIG_PM 718static int sport_uart_suspend(struct device *dev) 719{ 720 struct sport_uart_port *sport = dev_get_drvdata(dev); 721 722 dev_dbg(dev, "%s enter\n", __func__); 723 if (sport) 724 uart_suspend_port(&sport_uart_reg, &sport->port); 725 726 return 0; 727} 728 729static int sport_uart_resume(struct device *dev) 730{ 731 struct sport_uart_port *sport = dev_get_drvdata(dev); 732 733 dev_dbg(dev, "%s enter\n", __func__); 734 if (sport) 735 uart_resume_port(&sport_uart_reg, &sport->port); 736 737 return 0; 738} 739 740static struct dev_pm_ops bfin_sport_uart_dev_pm_ops = { 741 .suspend = sport_uart_suspend, 742 .resume = sport_uart_resume, 743}; 744#endif 745 746static int sport_uart_probe(struct platform_device *pdev) 747{ 748 struct resource *res; 749 struct sport_uart_port *sport; 750 int ret = 0; 751 752 dev_dbg(&pdev->dev, "%s enter\n", __func__); 753 754 if (pdev->id < 0 || pdev->id >= BFIN_SPORT_UART_MAX_PORTS) { 755 dev_err(&pdev->dev, "Wrong sport uart platform device id.\n"); 756 return -ENOENT; 757 } 758 759 if (bfin_sport_uart_ports[pdev->id] == NULL) { 760 bfin_sport_uart_ports[pdev->id] = 761 kzalloc(sizeof(struct sport_uart_port), GFP_KERNEL); 762 sport = bfin_sport_uart_ports[pdev->id]; 763 if (!sport) { 764 dev_err(&pdev->dev, 765 "Fail to malloc sport_uart_port\n"); 766 return -ENOMEM; 767 } 768 769 ret = peripheral_request_list(dev_get_platdata(&pdev->dev), 770 DRV_NAME); 771 if (ret) { 772 dev_err(&pdev->dev, 773 "Fail to request SPORT peripherals\n"); 774 goto out_error_free_mem; 775 } 776 777 spin_lock_init(&sport->port.lock); 778 sport->port.fifosize = SPORT_TX_FIFO_SIZE, 779 sport->port.ops = &sport_uart_ops; 780 sport->port.line = pdev->id; 781 sport->port.iotype = UPIO_MEM; 782 sport->port.flags = UPF_BOOT_AUTOCONF; 783 784 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 785 if (res == NULL) { 786 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n"); 787 ret = -ENOENT; 788 goto out_error_free_peripherals; 789 } 790 791 sport->port.membase = ioremap(res->start, resource_size(res)); 792 if (!sport->port.membase) { 793 dev_err(&pdev->dev, "Cannot map sport IO\n"); 794 ret = -ENXIO; 795 goto out_error_free_peripherals; 796 } 797 sport->port.mapbase = res->start; 798 799 sport->port.irq = platform_get_irq(pdev, 0); 800 if ((int)sport->port.irq < 0) { 801 dev_err(&pdev->dev, "No sport RX/TX IRQ specified\n"); 802 ret = -ENOENT; 803 goto out_error_unmap; 804 } 805 806 sport->err_irq = platform_get_irq(pdev, 1); 807 if (sport->err_irq < 0) { 808 dev_err(&pdev->dev, "No sport status IRQ specified\n"); 809 ret = -ENOENT; 810 goto out_error_unmap; 811 } 812#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS 813 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 814 if (res == NULL) 815 sport->cts_pin = -1; 816 else { 817 sport->cts_pin = res->start; 818 sport->port.flags |= ASYNC_CTS_FLOW; 819 } 820 821 res = platform_get_resource(pdev, IORESOURCE_IO, 1); 822 if (res == NULL) 823 sport->rts_pin = -1; 824 else 825 sport->rts_pin = res->start; 826#endif 827 } 828 829#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE 830 if (!is_early_platform_device(pdev)) { 831#endif 832 sport = bfin_sport_uart_ports[pdev->id]; 833 sport->port.dev = &pdev->dev; 834 dev_set_drvdata(&pdev->dev, sport); 835 ret = uart_add_one_port(&sport_uart_reg, &sport->port); 836#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE 837 } 838#endif 839 if (!ret) 840 return 0; 841 842 if (sport) { 843out_error_unmap: 844 iounmap(sport->port.membase); 845out_error_free_peripherals: 846 peripheral_free_list(dev_get_platdata(&pdev->dev)); 847out_error_free_mem: 848 kfree(sport); 849 bfin_sport_uart_ports[pdev->id] = NULL; 850 } 851 852 return ret; 853} 854 855static int sport_uart_remove(struct platform_device *pdev) 856{ 857 struct sport_uart_port *sport = platform_get_drvdata(pdev); 858 859 dev_dbg(&pdev->dev, "%s enter\n", __func__); 860 dev_set_drvdata(&pdev->dev, NULL); 861 862 if (sport) { 863 uart_remove_one_port(&sport_uart_reg, &sport->port); 864 iounmap(sport->port.membase); 865 peripheral_free_list(dev_get_platdata(&pdev->dev)); 866 kfree(sport); 867 bfin_sport_uart_ports[pdev->id] = NULL; 868 } 869 870 return 0; 871} 872 873static struct platform_driver sport_uart_driver = { 874 .probe = sport_uart_probe, 875 .remove = sport_uart_remove, 876 .driver = { 877 .name = DRV_NAME, 878#ifdef CONFIG_PM 879 .pm = &bfin_sport_uart_dev_pm_ops, 880#endif 881 }, 882}; 883 884#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE 885static struct early_platform_driver early_sport_uart_driver __initdata = { 886 .class_str = CLASS_BFIN_SPORT_CONSOLE, 887 .pdrv = &sport_uart_driver, 888 .requested_id = EARLY_PLATFORM_ID_UNSET, 889}; 890 891static int __init sport_uart_rs_console_init(void) 892{ 893 early_platform_driver_register(&early_sport_uart_driver, DRV_NAME); 894 895 early_platform_driver_probe(CLASS_BFIN_SPORT_CONSOLE, 896 BFIN_SPORT_UART_MAX_PORTS, 0); 897 898 register_console(&sport_uart_console); 899 900 return 0; 901} 902console_initcall(sport_uart_rs_console_init); 903#endif 904 905static int __init sport_uart_init(void) 906{ 907 int ret; 908 909 pr_info("Blackfin uart over sport driver\n"); 910 911 ret = uart_register_driver(&sport_uart_reg); 912 if (ret) { 913 pr_err("failed to register %s:%d\n", 914 sport_uart_reg.driver_name, ret); 915 return ret; 916 } 917 918 ret = platform_driver_register(&sport_uart_driver); 919 if (ret) { 920 pr_err("failed to register sport uart driver:%d\n", ret); 921 uart_unregister_driver(&sport_uart_reg); 922 } 923 924 return ret; 925} 926module_init(sport_uart_init); 927 928static void __exit sport_uart_exit(void) 929{ 930 platform_driver_unregister(&sport_uart_driver); 931 uart_unregister_driver(&sport_uart_reg); 932} 933module_exit(sport_uart_exit); 934 935MODULE_AUTHOR("Sonic Zhang, Roy Huang"); 936MODULE_DESCRIPTION("Blackfin serial over SPORT driver"); 937MODULE_LICENSE("GPL");