tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * PCIe driver for Marvell Armada 370 and Armada XP SoCs
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#include <linux/kernel.h>
10#include <linux/pci.h>
11#include <linux/clk.h>
12#include <linux/delay.h>
13#include <linux/gpio.h>
14#include <linux/module.h>
15#include <linux/mbus.h>
16#include <linux/msi.h>
17#include <linux/slab.h>
18#include <linux/platform_device.h>
19#include <linux/of_address.h>
20#include <linux/of_irq.h>
21#include <linux/of_gpio.h>
22#include <linux/of_pci.h>
23#include <linux/of_platform.h>
24
25/*
26 * PCIe unit register offsets.
27 */
28#define PCIE_DEV_ID_OFF 0x0000
29#define PCIE_CMD_OFF 0x0004
30#define PCIE_DEV_REV_OFF 0x0008
31#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
32#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
33#define PCIE_HEADER_LOG_4_OFF 0x0128
34#define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
35#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
36#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
37#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
38#define PCIE_WIN5_CTRL_OFF 0x1880
39#define PCIE_WIN5_BASE_OFF 0x1884
40#define PCIE_WIN5_REMAP_OFF 0x188c
41#define PCIE_CONF_ADDR_OFF 0x18f8
42#define PCIE_CONF_ADDR_EN 0x80000000
43#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
44#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
45#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
46#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
47#define PCIE_CONF_ADDR(bus, devfn, where) \
48 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
49 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
50 PCIE_CONF_ADDR_EN)
51#define PCIE_CONF_DATA_OFF 0x18fc
52#define PCIE_MASK_OFF 0x1910
53#define PCIE_MASK_ENABLE_INTS 0x0f000000
54#define PCIE_CTRL_OFF 0x1a00
55#define PCIE_CTRL_X1_MODE 0x0001
56#define PCIE_STAT_OFF 0x1a04
57#define PCIE_STAT_BUS 0xff00
58#define PCIE_STAT_DEV 0x1f0000
59#define PCIE_STAT_LINK_DOWN BIT(0)
60#define PCIE_DEBUG_CTRL 0x1a60
61#define PCIE_DEBUG_SOFT_RESET BIT(20)
62
63/* PCI configuration space of a PCI-to-PCI bridge */
64struct mvebu_sw_pci_bridge {
65 u16 vendor;
66 u16 device;
67 u16 command;
68 u16 class;
69 u8 interface;
70 u8 revision;
71 u8 bist;
72 u8 header_type;
73 u8 latency_timer;
74 u8 cache_line_size;
75 u32 bar[2];
76 u8 primary_bus;
77 u8 secondary_bus;
78 u8 subordinate_bus;
79 u8 secondary_latency_timer;
80 u8 iobase;
81 u8 iolimit;
82 u16 secondary_status;
83 u16 membase;
84 u16 memlimit;
85 u16 iobaseupper;
86 u16 iolimitupper;
87 u8 cappointer;
88 u8 reserved1;
89 u16 reserved2;
90 u32 romaddr;
91 u8 intline;
92 u8 intpin;
93 u16 bridgectrl;
94};
95
96struct mvebu_pcie_port;
97
98/* Structure representing all PCIe interfaces */
99struct mvebu_pcie {
100 struct platform_device *pdev;
101 struct mvebu_pcie_port *ports;
102 struct msi_chip *msi;
103 struct resource io;
104 char io_name[30];
105 struct resource realio;
106 char mem_name[30];
107 struct resource mem;
108 struct resource busn;
109 int nports;
110};
111
112/* Structure representing one PCIe interface */
113struct mvebu_pcie_port {
114 char *name;
115 void __iomem *base;
116 spinlock_t conf_lock;
117 u32 port;
118 u32 lane;
119 int devfn;
120 unsigned int mem_target;
121 unsigned int mem_attr;
122 unsigned int io_target;
123 unsigned int io_attr;
124 struct clk *clk;
125 int reset_gpio;
126 int reset_active_low;
127 char *reset_name;
128 struct mvebu_sw_pci_bridge bridge;
129 struct device_node *dn;
130 struct mvebu_pcie *pcie;
131 phys_addr_t memwin_base;
132 size_t memwin_size;
133 phys_addr_t iowin_base;
134 size_t iowin_size;
135};
136
137static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
138{
139 writel(val, port->base + reg);
140}
141
142static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)
143{
144 return readl(port->base + reg);
145}
146
147static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port)
148{
149 return port->io_target != -1 && port->io_attr != -1;
150}
151
152static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
153{
154 return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
155}
156
157static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
158{
159 u32 stat;
160
161 stat = mvebu_readl(port, PCIE_STAT_OFF);
162 stat &= ~PCIE_STAT_BUS;
163 stat |= nr << 8;
164 mvebu_writel(port, stat, PCIE_STAT_OFF);
165}
166
167static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
168{
169 u32 stat;
170
171 stat = mvebu_readl(port, PCIE_STAT_OFF);
172 stat &= ~PCIE_STAT_DEV;
173 stat |= nr << 16;
174 mvebu_writel(port, stat, PCIE_STAT_OFF);
175}
176
177/*
178 * Setup PCIE BARs and Address Decode Wins:
179 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
180 * WIN[0-3] -> DRAM bank[0-3]
181 */
182static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
183{
184 const struct mbus_dram_target_info *dram;
185 u32 size;
186 int i;
187
188 dram = mv_mbus_dram_info();
189
190 /* First, disable and clear BARs and windows. */
191 for (i = 1; i < 3; i++) {
192 mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
193 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
194 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
195 }
196
197 for (i = 0; i < 5; i++) {
198 mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
199 mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
200 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
201 }
202
203 mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
204 mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
205 mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
206
207 /* Setup windows for DDR banks. Count total DDR size on the fly. */
208 size = 0;
209 for (i = 0; i < dram->num_cs; i++) {
210 const struct mbus_dram_window *cs = dram->cs + i;
211
212 mvebu_writel(port, cs->base & 0xffff0000,
213 PCIE_WIN04_BASE_OFF(i));
214 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
215 mvebu_writel(port,
216 ((cs->size - 1) & 0xffff0000) |
217 (cs->mbus_attr << 8) |
218 (dram->mbus_dram_target_id << 4) | 1,
219 PCIE_WIN04_CTRL_OFF(i));
220
221 size += cs->size;
222 }
223
224 /* Round up 'size' to the nearest power of two. */
225 if ((size & (size - 1)) != 0)
226 size = 1 << fls(size);
227
228 /* Setup BAR[1] to all DRAM banks. */
229 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
230 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
231 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
232 PCIE_BAR_CTRL_OFF(1));
233}
234
235static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
236{
237 u32 cmd, mask;
238
239 /* Point PCIe unit MBUS decode windows to DRAM space. */
240 mvebu_pcie_setup_wins(port);
241
242 /* Master + slave enable. */
243 cmd = mvebu_readl(port, PCIE_CMD_OFF);
244 cmd |= PCI_COMMAND_IO;
245 cmd |= PCI_COMMAND_MEMORY;
246 cmd |= PCI_COMMAND_MASTER;
247 mvebu_writel(port, cmd, PCIE_CMD_OFF);
248
249 /* Enable interrupt lines A-D. */
250 mask = mvebu_readl(port, PCIE_MASK_OFF);
251 mask |= PCIE_MASK_ENABLE_INTS;
252 mvebu_writel(port, mask, PCIE_MASK_OFF);
253}
254
255static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
256 struct pci_bus *bus,
257 u32 devfn, int where, int size, u32 *val)
258{
259 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
260 PCIE_CONF_ADDR_OFF);
261
262 *val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
263
264 if (size == 1)
265 *val = (*val >> (8 * (where & 3))) & 0xff;
266 else if (size == 2)
267 *val = (*val >> (8 * (where & 3))) & 0xffff;
268
269 return PCIBIOS_SUCCESSFUL;
270}
271
272static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
273 struct pci_bus *bus,
274 u32 devfn, int where, int size, u32 val)
275{
276 u32 _val, shift = 8 * (where & 3);
277
278 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
279 PCIE_CONF_ADDR_OFF);
280 _val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
281
282 if (size == 4)
283 _val = val;
284 else if (size == 2)
285 _val = (_val & ~(0xffff << shift)) | ((val & 0xffff) << shift);
286 else if (size == 1)
287 _val = (_val & ~(0xff << shift)) | ((val & 0xff) << shift);
288 else
289 return PCIBIOS_BAD_REGISTER_NUMBER;
290
291 mvebu_writel(port, _val, PCIE_CONF_DATA_OFF);
292
293 return PCIBIOS_SUCCESSFUL;
294}
295
296static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
297{
298 phys_addr_t iobase;
299
300 /* Are the new iobase/iolimit values invalid? */
301 if (port->bridge.iolimit < port->bridge.iobase ||
302 port->bridge.iolimitupper < port->bridge.iobaseupper ||
303 !(port->bridge.command & PCI_COMMAND_IO)) {
304
305 /* If a window was configured, remove it */
306 if (port->iowin_base) {
307 mvebu_mbus_del_window(port->iowin_base,
308 port->iowin_size);
309 port->iowin_base = 0;
310 port->iowin_size = 0;
311 }
312
313 return;
314 }
315
316 if (!mvebu_has_ioport(port)) {
317 dev_WARN(&port->pcie->pdev->dev,
318 "Attempt to set IO when IO is disabled\n");
319 return;
320 }
321
322 /*
323 * We read the PCI-to-PCI bridge emulated registers, and
324 * calculate the base address and size of the address decoding
325 * window to setup, according to the PCI-to-PCI bridge
326 * specifications. iobase is the bus address, port->iowin_base
327 * is the CPU address.
328 */
329 iobase = ((port->bridge.iobase & 0xF0) << 8) |
330 (port->bridge.iobaseupper << 16);
331 port->iowin_base = port->pcie->io.start + iobase;
332 port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
333 (port->bridge.iolimitupper << 16)) -
334 iobase);
335
336 mvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr,
337 port->iowin_base, port->iowin_size,
338 iobase);
339}
340
341static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
342{
343 /* Are the new membase/memlimit values invalid? */
344 if (port->bridge.memlimit < port->bridge.membase ||
345 !(port->bridge.command & PCI_COMMAND_MEMORY)) {
346
347 /* If a window was configured, remove it */
348 if (port->memwin_base) {
349 mvebu_mbus_del_window(port->memwin_base,
350 port->memwin_size);
351 port->memwin_base = 0;
352 port->memwin_size = 0;
353 }
354
355 return;
356 }
357
358 /*
359 * We read the PCI-to-PCI bridge emulated registers, and
360 * calculate the base address and size of the address decoding
361 * window to setup, according to the PCI-to-PCI bridge
362 * specifications.
363 */
364 port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);
365 port->memwin_size =
366 (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
367 port->memwin_base;
368
369 mvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr,
370 port->memwin_base, port->memwin_size);
371}
372
373/*
374 * Initialize the configuration space of the PCI-to-PCI bridge
375 * associated with the given PCIe interface.
376 */
377static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
378{
379 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
380
381 memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
382
383 bridge->class = PCI_CLASS_BRIDGE_PCI;
384 bridge->vendor = PCI_VENDOR_ID_MARVELL;
385 bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
386 bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
387 bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
388 bridge->cache_line_size = 0x10;
389
390 /* We support 32 bits I/O addressing */
391 bridge->iobase = PCI_IO_RANGE_TYPE_32;
392 bridge->iolimit = PCI_IO_RANGE_TYPE_32;
393}
394
395/*
396 * Read the configuration space of the PCI-to-PCI bridge associated to
397 * the given PCIe interface.
398 */
399static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
400 unsigned int where, int size, u32 *value)
401{
402 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
403
404 switch (where & ~3) {
405 case PCI_VENDOR_ID:
406 *value = bridge->device << 16 | bridge->vendor;
407 break;
408
409 case PCI_COMMAND:
410 *value = bridge->command;
411 break;
412
413 case PCI_CLASS_REVISION:
414 *value = bridge->class << 16 | bridge->interface << 8 |
415 bridge->revision;
416 break;
417
418 case PCI_CACHE_LINE_SIZE:
419 *value = bridge->bist << 24 | bridge->header_type << 16 |
420 bridge->latency_timer << 8 | bridge->cache_line_size;
421 break;
422
423 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
424 *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
425 break;
426
427 case PCI_PRIMARY_BUS:
428 *value = (bridge->secondary_latency_timer << 24 |
429 bridge->subordinate_bus << 16 |
430 bridge->secondary_bus << 8 |
431 bridge->primary_bus);
432 break;
433
434 case PCI_IO_BASE:
435 if (!mvebu_has_ioport(port))
436 *value = bridge->secondary_status << 16;
437 else
438 *value = (bridge->secondary_status << 16 |
439 bridge->iolimit << 8 |
440 bridge->iobase);
441 break;
442
443 case PCI_MEMORY_BASE:
444 *value = (bridge->memlimit << 16 | bridge->membase);
445 break;
446
447 case PCI_PREF_MEMORY_BASE:
448 *value = 0;
449 break;
450
451 case PCI_IO_BASE_UPPER16:
452 *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
453 break;
454
455 case PCI_ROM_ADDRESS1:
456 *value = 0;
457 break;
458
459 case PCI_INTERRUPT_LINE:
460 /* LINE PIN MIN_GNT MAX_LAT */
461 *value = 0;
462 break;
463
464 default:
465 *value = 0xffffffff;
466 return PCIBIOS_BAD_REGISTER_NUMBER;
467 }
468
469 if (size == 2)
470 *value = (*value >> (8 * (where & 3))) & 0xffff;
471 else if (size == 1)
472 *value = (*value >> (8 * (where & 3))) & 0xff;
473
474 return PCIBIOS_SUCCESSFUL;
475}
476
477/* Write to the PCI-to-PCI bridge configuration space */
478static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
479 unsigned int where, int size, u32 value)
480{
481 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
482 u32 mask, reg;
483 int err;
484
485 if (size == 4)
486 mask = 0x0;
487 else if (size == 2)
488 mask = ~(0xffff << ((where & 3) * 8));
489 else if (size == 1)
490 mask = ~(0xff << ((where & 3) * 8));
491 else
492 return PCIBIOS_BAD_REGISTER_NUMBER;
493
494 err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®);
495 if (err)
496 return err;
497
498 value = (reg & mask) | value << ((where & 3) * 8);
499
500 switch (where & ~3) {
501 case PCI_COMMAND:
502 {
503 u32 old = bridge->command;
504
505 if (!mvebu_has_ioport(port))
506 value &= ~PCI_COMMAND_IO;
507
508 bridge->command = value & 0xffff;
509 if ((old ^ bridge->command) & PCI_COMMAND_IO)
510 mvebu_pcie_handle_iobase_change(port);
511 if ((old ^ bridge->command) & PCI_COMMAND_MEMORY)
512 mvebu_pcie_handle_membase_change(port);
513 break;
514 }
515
516 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
517 bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
518 break;
519
520 case PCI_IO_BASE:
521 /*
522 * We also keep bit 1 set, it is a read-only bit that
523 * indicates we support 32 bits addressing for the
524 * I/O
525 */
526 bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
527 bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
528 mvebu_pcie_handle_iobase_change(port);
529 break;
530
531 case PCI_MEMORY_BASE:
532 bridge->membase = value & 0xffff;
533 bridge->memlimit = value >> 16;
534 mvebu_pcie_handle_membase_change(port);
535 break;
536
537 case PCI_IO_BASE_UPPER16:
538 bridge->iobaseupper = value & 0xffff;
539 bridge->iolimitupper = value >> 16;
540 mvebu_pcie_handle_iobase_change(port);
541 break;
542
543 case PCI_PRIMARY_BUS:
544 bridge->primary_bus = value & 0xff;
545 bridge->secondary_bus = (value >> 8) & 0xff;
546 bridge->subordinate_bus = (value >> 16) & 0xff;
547 bridge->secondary_latency_timer = (value >> 24) & 0xff;
548 mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
549 break;
550
551 default:
552 break;
553 }
554
555 return PCIBIOS_SUCCESSFUL;
556}
557
558static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
559{
560 return sys->private_data;
561}
562
563static struct mvebu_pcie_port *
564mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
565 int devfn)
566{
567 int i;
568
569 for (i = 0; i < pcie->nports; i++) {
570 struct mvebu_pcie_port *port = &pcie->ports[i];
571 if (bus->number == 0 && port->devfn == devfn)
572 return port;
573 if (bus->number != 0 &&
574 bus->number >= port->bridge.secondary_bus &&
575 bus->number <= port->bridge.subordinate_bus)
576 return port;
577 }
578
579 return NULL;
580}
581
582/* PCI configuration space write function */
583static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
584 int where, int size, u32 val)
585{
586 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
587 struct mvebu_pcie_port *port;
588 unsigned long flags;
589 int ret;
590
591 port = mvebu_pcie_find_port(pcie, bus, devfn);
592 if (!port)
593 return PCIBIOS_DEVICE_NOT_FOUND;
594
595 /* Access the emulated PCI-to-PCI bridge */
596 if (bus->number == 0)
597 return mvebu_sw_pci_bridge_write(port, where, size, val);
598
599 if (!mvebu_pcie_link_up(port))
600 return PCIBIOS_DEVICE_NOT_FOUND;
601
602 /*
603 * On the secondary bus, we don't want to expose any other
604 * device than the device physically connected in the PCIe
605 * slot, visible in slot 0. In slot 1, there's a special
606 * Marvell device that only makes sense when the Armada is
607 * used as a PCIe endpoint.
608 */
609 if (bus->number == port->bridge.secondary_bus &&
610 PCI_SLOT(devfn) != 0)
611 return PCIBIOS_DEVICE_NOT_FOUND;
612
613 /* Access the real PCIe interface */
614 spin_lock_irqsave(&port->conf_lock, flags);
615 ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
616 where, size, val);
617 spin_unlock_irqrestore(&port->conf_lock, flags);
618
619 return ret;
620}
621
622/* PCI configuration space read function */
623static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
624 int size, u32 *val)
625{
626 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
627 struct mvebu_pcie_port *port;
628 unsigned long flags;
629 int ret;
630
631 port = mvebu_pcie_find_port(pcie, bus, devfn);
632 if (!port) {
633 *val = 0xffffffff;
634 return PCIBIOS_DEVICE_NOT_FOUND;
635 }
636
637 /* Access the emulated PCI-to-PCI bridge */
638 if (bus->number == 0)
639 return mvebu_sw_pci_bridge_read(port, where, size, val);
640
641 if (!mvebu_pcie_link_up(port)) {
642 *val = 0xffffffff;
643 return PCIBIOS_DEVICE_NOT_FOUND;
644 }
645
646 /*
647 * On the secondary bus, we don't want to expose any other
648 * device than the device physically connected in the PCIe
649 * slot, visible in slot 0. In slot 1, there's a special
650 * Marvell device that only makes sense when the Armada is
651 * used as a PCIe endpoint.
652 */
653 if (bus->number == port->bridge.secondary_bus &&
654 PCI_SLOT(devfn) != 0) {
655 *val = 0xffffffff;
656 return PCIBIOS_DEVICE_NOT_FOUND;
657 }
658
659 /* Access the real PCIe interface */
660 spin_lock_irqsave(&port->conf_lock, flags);
661 ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
662 where, size, val);
663 spin_unlock_irqrestore(&port->conf_lock, flags);
664
665 return ret;
666}
667
668static struct pci_ops mvebu_pcie_ops = {
669 .read = mvebu_pcie_rd_conf,
670 .write = mvebu_pcie_wr_conf,
671};
672
673static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
674{
675 struct mvebu_pcie *pcie = sys_to_pcie(sys);
676 int i;
677 int domain = 0;
678
679#ifdef CONFIG_PCI_DOMAINS
680 domain = sys->domain;
681#endif
682
683 snprintf(pcie->mem_name, sizeof(pcie->mem_name), "PCI MEM %04x",
684 domain);
685 pcie->mem.name = pcie->mem_name;
686
687 snprintf(pcie->io_name, sizeof(pcie->io_name), "PCI I/O %04x", domain);
688 pcie->realio.name = pcie->io_name;
689
690 if (request_resource(&iomem_resource, &pcie->mem))
691 return 0;
692
693 if (resource_size(&pcie->realio) != 0) {
694 if (request_resource(&ioport_resource, &pcie->realio)) {
695 release_resource(&pcie->mem);
696 return 0;
697 }
698 pci_add_resource_offset(&sys->resources, &pcie->realio,
699 sys->io_offset);
700 }
701 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
702 pci_add_resource(&sys->resources, &pcie->busn);
703
704 for (i = 0; i < pcie->nports; i++) {
705 struct mvebu_pcie_port *port = &pcie->ports[i];
706 if (!port->base)
707 continue;
708 mvebu_pcie_setup_hw(port);
709 }
710
711 return 1;
712}
713
714static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
715{
716 struct mvebu_pcie *pcie = sys_to_pcie(sys);
717 struct pci_bus *bus;
718
719 bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
720 &mvebu_pcie_ops, sys, &sys->resources);
721 if (!bus)
722 return NULL;
723
724 pci_scan_child_bus(bus);
725
726 return bus;
727}
728
729static void mvebu_pcie_add_bus(struct pci_bus *bus)
730{
731 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
732 bus->msi = pcie->msi;
733}
734
735static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
736 const struct resource *res,
737 resource_size_t start,
738 resource_size_t size,
739 resource_size_t align)
740{
741 if (dev->bus->number != 0)
742 return start;
743
744 /*
745 * On the PCI-to-PCI bridge side, the I/O windows must have at
746 * least a 64 KB size and be aligned on their size, and the
747 * memory windows must have at least a 1 MB size and be
748 * aligned on their size
749 */
750 if (res->flags & IORESOURCE_IO)
751 return round_up(start, max_t(resource_size_t, SZ_64K, size));
752 else if (res->flags & IORESOURCE_MEM)
753 return round_up(start, max_t(resource_size_t, SZ_1M, size));
754 else
755 return start;
756}
757
758static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
759{
760 struct hw_pci hw;
761
762 memset(&hw, 0, sizeof(hw));
763
764 hw.nr_controllers = 1;
765 hw.private_data = (void **)&pcie;
766 hw.setup = mvebu_pcie_setup;
767 hw.scan = mvebu_pcie_scan_bus;
768 hw.map_irq = of_irq_parse_and_map_pci;
769 hw.ops = &mvebu_pcie_ops;
770 hw.align_resource = mvebu_pcie_align_resource;
771 hw.add_bus = mvebu_pcie_add_bus;
772
773 pci_common_init(&hw);
774}
775
776/*
777 * Looks up the list of register addresses encoded into the reg =
778 * <...> property for one that matches the given port/lane. Once
779 * found, maps it.
780 */
781static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
782 struct device_node *np, struct mvebu_pcie_port *port)
783{
784 struct resource regs;
785 int ret = 0;
786
787 ret = of_address_to_resource(np, 0, ®s);
788 if (ret)
789 return ERR_PTR(ret);
790
791 return devm_ioremap_resource(&pdev->dev, ®s);
792}
793
794#define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
795#define DT_TYPE_IO 0x1
796#define DT_TYPE_MEM32 0x2
797#define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
798#define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
799
800static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
801 unsigned long type,
802 unsigned int *tgt,
803 unsigned int *attr)
804{
805 const int na = 3, ns = 2;
806 const __be32 *range;
807 int rlen, nranges, rangesz, pna, i;
808
809 *tgt = -1;
810 *attr = -1;
811
812 range = of_get_property(np, "ranges", &rlen);
813 if (!range)
814 return -EINVAL;
815
816 pna = of_n_addr_cells(np);
817 rangesz = pna + na + ns;
818 nranges = rlen / sizeof(__be32) / rangesz;
819
820 for (i = 0; i < nranges; i++) {
821 u32 flags = of_read_number(range, 1);
822 u32 slot = of_read_number(range + 1, 1);
823 u64 cpuaddr = of_read_number(range + na, pna);
824 unsigned long rtype;
825
826 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
827 rtype = IORESOURCE_IO;
828 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
829 rtype = IORESOURCE_MEM;
830
831 if (slot == PCI_SLOT(devfn) && type == rtype) {
832 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
833 *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
834 return 0;
835 }
836
837 range += rangesz;
838 }
839
840 return -ENOENT;
841}
842
843static void mvebu_pcie_msi_enable(struct mvebu_pcie *pcie)
844{
845 struct device_node *msi_node;
846
847 msi_node = of_parse_phandle(pcie->pdev->dev.of_node,
848 "msi-parent", 0);
849 if (!msi_node)
850 return;
851
852 pcie->msi = of_pci_find_msi_chip_by_node(msi_node);
853
854 if (pcie->msi)
855 pcie->msi->dev = &pcie->pdev->dev;
856}
857
858static int mvebu_pcie_probe(struct platform_device *pdev)
859{
860 struct mvebu_pcie *pcie;
861 struct device_node *np = pdev->dev.of_node;
862 struct device_node *child;
863 int i, ret;
864
865 pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
866 GFP_KERNEL);
867 if (!pcie)
868 return -ENOMEM;
869
870 pcie->pdev = pdev;
871 platform_set_drvdata(pdev, pcie);
872
873 /* Get the PCIe memory and I/O aperture */
874 mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
875 if (resource_size(&pcie->mem) == 0) {
876 dev_err(&pdev->dev, "invalid memory aperture size\n");
877 return -EINVAL;
878 }
879
880 mvebu_mbus_get_pcie_io_aperture(&pcie->io);
881
882 if (resource_size(&pcie->io) != 0) {
883 pcie->realio.flags = pcie->io.flags;
884 pcie->realio.start = PCIBIOS_MIN_IO;
885 pcie->realio.end = min_t(resource_size_t,
886 IO_SPACE_LIMIT,
887 resource_size(&pcie->io));
888 } else
889 pcie->realio = pcie->io;
890
891 /* Get the bus range */
892 ret = of_pci_parse_bus_range(np, &pcie->busn);
893 if (ret) {
894 dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
895 ret);
896 return ret;
897 }
898
899 i = 0;
900 for_each_child_of_node(pdev->dev.of_node, child) {
901 if (!of_device_is_available(child))
902 continue;
903 i++;
904 }
905
906 pcie->ports = devm_kzalloc(&pdev->dev, i *
907 sizeof(struct mvebu_pcie_port),
908 GFP_KERNEL);
909 if (!pcie->ports)
910 return -ENOMEM;
911
912 i = 0;
913 for_each_child_of_node(pdev->dev.of_node, child) {
914 struct mvebu_pcie_port *port = &pcie->ports[i];
915 enum of_gpio_flags flags;
916
917 if (!of_device_is_available(child))
918 continue;
919
920 port->pcie = pcie;
921
922 if (of_property_read_u32(child, "marvell,pcie-port",
923 &port->port)) {
924 dev_warn(&pdev->dev,
925 "ignoring PCIe DT node, missing pcie-port property\n");
926 continue;
927 }
928
929 if (of_property_read_u32(child, "marvell,pcie-lane",
930 &port->lane))
931 port->lane = 0;
932
933 port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
934 port->port, port->lane);
935
936 port->devfn = of_pci_get_devfn(child);
937 if (port->devfn < 0)
938 continue;
939
940 ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_MEM,
941 &port->mem_target, &port->mem_attr);
942 if (ret < 0) {
943 dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for mem window\n",
944 port->port, port->lane);
945 continue;
946 }
947
948 if (resource_size(&pcie->io) != 0)
949 mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO,
950 &port->io_target, &port->io_attr);
951 else {
952 port->io_target = -1;
953 port->io_attr = -1;
954 }
955
956 port->reset_gpio = of_get_named_gpio_flags(child,
957 "reset-gpios", 0, &flags);
958 if (gpio_is_valid(port->reset_gpio)) {
959 u32 reset_udelay = 20000;
960
961 port->reset_active_low = flags & OF_GPIO_ACTIVE_LOW;
962 port->reset_name = kasprintf(GFP_KERNEL,
963 "pcie%d.%d-reset", port->port, port->lane);
964 of_property_read_u32(child, "reset-delay-us",
965 &reset_udelay);
966
967 ret = devm_gpio_request_one(&pdev->dev,
968 port->reset_gpio, GPIOF_DIR_OUT, port->reset_name);
969 if (ret) {
970 if (ret == -EPROBE_DEFER)
971 return ret;
972 continue;
973 }
974
975 gpio_set_value(port->reset_gpio,
976 (port->reset_active_low) ? 1 : 0);
977 msleep(reset_udelay/1000);
978 }
979
980 port->clk = of_clk_get_by_name(child, NULL);
981 if (IS_ERR(port->clk)) {
982 dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
983 port->port, port->lane);
984 continue;
985 }
986
987 ret = clk_prepare_enable(port->clk);
988 if (ret)
989 continue;
990
991 port->base = mvebu_pcie_map_registers(pdev, child, port);
992 if (IS_ERR(port->base)) {
993 dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
994 port->port, port->lane);
995 port->base = NULL;
996 clk_disable_unprepare(port->clk);
997 continue;
998 }
999
1000 mvebu_pcie_set_local_dev_nr(port, 1);
1001
1002 port->dn = child;
1003 spin_lock_init(&port->conf_lock);
1004 mvebu_sw_pci_bridge_init(port);
1005 i++;
1006 }
1007
1008 pcie->nports = i;
1009
1010 for (i = 0; i < (IO_SPACE_LIMIT - SZ_64K); i += SZ_64K)
1011 pci_ioremap_io(i, pcie->io.start + i);
1012
1013 mvebu_pcie_msi_enable(pcie);
1014 mvebu_pcie_enable(pcie);
1015
1016 return 0;
1017}
1018
1019static const struct of_device_id mvebu_pcie_of_match_table[] = {
1020 { .compatible = "marvell,armada-xp-pcie", },
1021 { .compatible = "marvell,armada-370-pcie", },
1022 { .compatible = "marvell,dove-pcie", },
1023 { .compatible = "marvell,kirkwood-pcie", },
1024 {},
1025};
1026MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
1027
1028static struct platform_driver mvebu_pcie_driver = {
1029 .driver = {
1030 .owner = THIS_MODULE,
1031 .name = "mvebu-pcie",
1032 .of_match_table = mvebu_pcie_of_match_table,
1033 /* driver unloading/unbinding currently not supported */
1034 .suppress_bind_attrs = true,
1035 },
1036 .probe = mvebu_pcie_probe,
1037};
1038module_platform_driver(mvebu_pcie_driver);
1039
1040MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
1041MODULE_DESCRIPTION("Marvell EBU PCIe driver");
1042MODULE_LICENSE("GPLv2");