tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35
36#include <asm/asm.h>
37#include <asm/asm-offsets.h>
38#include <asm/regdef.h>
39#include <asm/mipsregs.h>
40#include <asm/stackframe.h>
41#include <asm/asmmacro.h>
42#include <asm/addrspace.h>
43
44#include <asm/netlogic/common.h>
45
46#include <asm/netlogic/xlp-hal/iomap.h>
47#include <asm/netlogic/xlp-hal/xlp.h>
48#include <asm/netlogic/xlp-hal/sys.h>
49#include <asm/netlogic/xlp-hal/cpucontrol.h>
50
51#define CP0_EBASE $15
52
53 .set noreorder
54 .set noat
55 .set arch=xlr /* for mfcr/mtcr, XLR is sufficient */
56
57FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */
58 dmtc0 sp, $4, 2 /* SP saved in UserLocal */
59 SAVE_ALL
60 sync
61 /* find the location to which nlm_boot_siblings was relocated */
62 li t0, CKSEG1ADDR(RESET_VEC_PHYS)
63 dla t1, nlm_reset_entry
64 dla t2, nlm_boot_siblings
65 dsubu t2, t1
66 daddu t2, t0
67 /* call it */
68 jr t2
69 nop
70 /* not reached */
71
72NESTED(nlm_boot_secondary_cpus, 16, sp)
73 /* Initialize CP0 Status */
74 move t1, zero
75#ifdef CONFIG_64BIT
76 ori t1, ST0_KX
77#endif
78 mtc0 t1, CP0_STATUS
79 PTR_LA t1, nlm_next_sp
80 PTR_L sp, 0(t1)
81 PTR_LA t1, nlm_next_gp
82 PTR_L gp, 0(t1)
83
84 /* a0 has the processor id */
85 mfc0 a0, CP0_EBASE, 1
86 andi a0, 0x3ff /* a0 <- node/core */
87 PTR_LA t0, nlm_early_init_secondary
88 jalr t0
89 nop
90
91 PTR_LA t0, smp_bootstrap
92 jr t0
93 nop
94END(nlm_boot_secondary_cpus)
95
96/*
97 * In case of RMIboot bootloader which is used on XLR boards, the CPUs
98 * be already woken up and waiting in bootloader code.
99 * This will get them out of the bootloader code and into linux. Needed
100 * because the bootloader area will be taken and initialized by linux.
101 */
102NESTED(nlm_rmiboot_preboot, 16, sp)
103 mfc0 t0, $15, 1 /* read ebase */
104 andi t0, 0x1f /* t0 has the processor_id() */
105 andi t2, t0, 0x3 /* thread num */
106 sll t0, 2 /* offset in cpu array */
107
108 li t3, CKSEG1ADDR(RESET_DATA_PHYS)
109 ADDIU t1, t3, BOOT_CPU_READY
110 ADDU t1, t0
111 li t3, 1
112 sw t3, 0(t1)
113
114 bnez t2, 1f /* skip thread programming */
115 nop /* for thread id != 0 */
116
117 /*
118 * XLR MMU setup only for first thread in core
119 */
120 li t0, 0x400
121 mfcr t1, t0
122 li t2, 6 /* XLR thread mode mask */
123 nor t3, t2, zero
124 and t2, t1, t2 /* t2 - current thread mode */
125 li v0, CKSEG1ADDR(RESET_DATA_PHYS)
126 lw v1, BOOT_THREAD_MODE(v0) /* v1 - new thread mode */
127 sll v1, 1
128 beq v1, t2, 1f /* same as request value */
129 nop /* nothing to do */
130
131 and t2, t1, t3 /* mask out old thread mode */
132 or t1, t2, v1 /* put in new value */
133 mtcr t1, t0 /* update core control */
134
135 /* wait for NMI to hit */
1361: wait
137 b 1b
138 nop
139END(nlm_rmiboot_preboot)