tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
3 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18
19#ifndef __ARM_KVM_H__
20#define __ARM_KVM_H__
21
22#include <linux/types.h>
23#include <asm/ptrace.h>
24
25#define __KVM_HAVE_GUEST_DEBUG
26#define __KVM_HAVE_IRQ_LINE
27
28#define KVM_REG_SIZE(id) \
29 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
30
31/* Valid for svc_regs, abt_regs, und_regs, irq_regs in struct kvm_regs */
32#define KVM_ARM_SVC_sp svc_regs[0]
33#define KVM_ARM_SVC_lr svc_regs[1]
34#define KVM_ARM_SVC_spsr svc_regs[2]
35#define KVM_ARM_ABT_sp abt_regs[0]
36#define KVM_ARM_ABT_lr abt_regs[1]
37#define KVM_ARM_ABT_spsr abt_regs[2]
38#define KVM_ARM_UND_sp und_regs[0]
39#define KVM_ARM_UND_lr und_regs[1]
40#define KVM_ARM_UND_spsr und_regs[2]
41#define KVM_ARM_IRQ_sp irq_regs[0]
42#define KVM_ARM_IRQ_lr irq_regs[1]
43#define KVM_ARM_IRQ_spsr irq_regs[2]
44
45/* Valid only for fiq_regs in struct kvm_regs */
46#define KVM_ARM_FIQ_r8 fiq_regs[0]
47#define KVM_ARM_FIQ_r9 fiq_regs[1]
48#define KVM_ARM_FIQ_r10 fiq_regs[2]
49#define KVM_ARM_FIQ_fp fiq_regs[3]
50#define KVM_ARM_FIQ_ip fiq_regs[4]
51#define KVM_ARM_FIQ_sp fiq_regs[5]
52#define KVM_ARM_FIQ_lr fiq_regs[6]
53#define KVM_ARM_FIQ_spsr fiq_regs[7]
54
55struct kvm_regs {
56 struct pt_regs usr_regs; /* R0_usr - R14_usr, PC, CPSR */
57 unsigned long svc_regs[3]; /* SP_svc, LR_svc, SPSR_svc */
58 unsigned long abt_regs[3]; /* SP_abt, LR_abt, SPSR_abt */
59 unsigned long und_regs[3]; /* SP_und, LR_und, SPSR_und */
60 unsigned long irq_regs[3]; /* SP_irq, LR_irq, SPSR_irq */
61 unsigned long fiq_regs[8]; /* R8_fiq - R14_fiq, SPSR_fiq */
62};
63
64/* Supported Processor Types */
65#define KVM_ARM_TARGET_CORTEX_A15 0
66#define KVM_ARM_TARGET_CORTEX_A7 1
67#define KVM_ARM_NUM_TARGETS 2
68
69/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
70#define KVM_ARM_DEVICE_TYPE_SHIFT 0
71#define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
72#define KVM_ARM_DEVICE_ID_SHIFT 16
73#define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
74
75/* Supported device IDs */
76#define KVM_ARM_DEVICE_VGIC_V2 0
77
78/* Supported VGIC address types */
79#define KVM_VGIC_V2_ADDR_TYPE_DIST 0
80#define KVM_VGIC_V2_ADDR_TYPE_CPU 1
81
82#define KVM_VGIC_V2_DIST_SIZE 0x1000
83#define KVM_VGIC_V2_CPU_SIZE 0x2000
84
85#define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */
86
87struct kvm_vcpu_init {
88 __u32 target;
89 __u32 features[7];
90};
91
92struct kvm_sregs {
93};
94
95struct kvm_fpu {
96};
97
98struct kvm_guest_debug_arch {
99};
100
101struct kvm_debug_exit_arch {
102};
103
104struct kvm_sync_regs {
105};
106
107struct kvm_arch_memory_slot {
108};
109
110/* If you need to interpret the index values, here is the key: */
111#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
112#define KVM_REG_ARM_COPROC_SHIFT 16
113#define KVM_REG_ARM_32_OPC2_MASK 0x0000000000000007
114#define KVM_REG_ARM_32_OPC2_SHIFT 0
115#define KVM_REG_ARM_OPC1_MASK 0x0000000000000078
116#define KVM_REG_ARM_OPC1_SHIFT 3
117#define KVM_REG_ARM_CRM_MASK 0x0000000000000780
118#define KVM_REG_ARM_CRM_SHIFT 7
119#define KVM_REG_ARM_32_CRN_MASK 0x0000000000007800
120#define KVM_REG_ARM_32_CRN_SHIFT 11
121
122#define ARM_CP15_REG_SHIFT_MASK(x,n) \
123 (((x) << KVM_REG_ARM_ ## n ## _SHIFT) & KVM_REG_ARM_ ## n ## _MASK)
124
125#define __ARM_CP15_REG(op1,crn,crm,op2) \
126 (KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT) | \
127 ARM_CP15_REG_SHIFT_MASK(op1, OPC1) | \
128 ARM_CP15_REG_SHIFT_MASK(crn, 32_CRN) | \
129 ARM_CP15_REG_SHIFT_MASK(crm, CRM) | \
130 ARM_CP15_REG_SHIFT_MASK(op2, 32_OPC2))
131
132#define ARM_CP15_REG32(...) (__ARM_CP15_REG(__VA_ARGS__) | KVM_REG_SIZE_U32)
133
134#define __ARM_CP15_REG64(op1,crm) \
135 (__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
136#define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__)
137
138#define KVM_REG_ARM_TIMER_CTL ARM_CP15_REG32(0, 14, 3, 1)
139#define KVM_REG_ARM_TIMER_CNT ARM_CP15_REG64(1, 14)
140#define KVM_REG_ARM_TIMER_CVAL ARM_CP15_REG64(3, 14)
141
142/* Normal registers are mapped as coprocessor 16. */
143#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
144#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / 4)
145
146/* Some registers need more space to represent values. */
147#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
148#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
149#define KVM_REG_ARM_DEMUX_ID_SHIFT 8
150#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
151#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
152#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
153
154/* VFP registers: we could overload CP10 like ARM does, but that's ugly. */
155#define KVM_REG_ARM_VFP (0x0012 << KVM_REG_ARM_COPROC_SHIFT)
156#define KVM_REG_ARM_VFP_MASK 0x000000000000FFFF
157#define KVM_REG_ARM_VFP_BASE_REG 0x0
158#define KVM_REG_ARM_VFP_FPSID 0x1000
159#define KVM_REG_ARM_VFP_FPSCR 0x1001
160#define KVM_REG_ARM_VFP_MVFR1 0x1006
161#define KVM_REG_ARM_VFP_MVFR0 0x1007
162#define KVM_REG_ARM_VFP_FPEXC 0x1008
163#define KVM_REG_ARM_VFP_FPINST 0x1009
164#define KVM_REG_ARM_VFP_FPINST2 0x100A
165
166/* Device Control API: ARM VGIC */
167#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
168#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
169#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
170#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
171#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
172#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
173#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
174
175/* KVM_IRQ_LINE irq field index values */
176#define KVM_ARM_IRQ_TYPE_SHIFT 24
177#define KVM_ARM_IRQ_TYPE_MASK 0xff
178#define KVM_ARM_IRQ_VCPU_SHIFT 16
179#define KVM_ARM_IRQ_VCPU_MASK 0xff
180#define KVM_ARM_IRQ_NUM_SHIFT 0
181#define KVM_ARM_IRQ_NUM_MASK 0xffff
182
183/* irq_type field */
184#define KVM_ARM_IRQ_TYPE_CPU 0
185#define KVM_ARM_IRQ_TYPE_SPI 1
186#define KVM_ARM_IRQ_TYPE_PPI 2
187
188/* out-of-kernel GIC cpu interrupt injection irq_number field */
189#define KVM_ARM_IRQ_CPU_IRQ 0
190#define KVM_ARM_IRQ_CPU_FIQ 1
191
192/* Highest supported SPI, from VGIC_NR_IRQS */
193#define KVM_ARM_IRQ_GIC_MAX 127
194
195/* PSCI interface */
196#define KVM_PSCI_FN_BASE 0x95c1ba5e
197#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
198
199#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)
200#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1)
201#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2)
202#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3)
203
204#define KVM_PSCI_RET_SUCCESS 0
205#define KVM_PSCI_RET_NI ((unsigned long)-1)
206#define KVM_PSCI_RET_INVAL ((unsigned long)-2)
207#define KVM_PSCI_RET_DENIED ((unsigned long)-3)
208
209#endif /* __ARM_KVM_H__ */