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1/* linux/include/asm-arm/arch-msm/hsusb.h
2 *
3 * Copyright (C) 2008 Google, Inc.
4 * Author: Brian Swetland <swetland@google.com>
5 * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef __ASM_ARCH_MSM_HSUSB_H
19#define __ASM_ARCH_MSM_HSUSB_H
20
21#include <linux/types.h>
22#include <linux/usb/otg.h>
23#include <linux/clk.h>
24
25/**
26 * Supported USB modes
27 *
28 * USB_PERIPHERAL Only peripheral mode is supported.
29 * USB_HOST Only host mode is supported.
30 * USB_OTG OTG mode is supported.
31 *
32 */
33enum usb_mode_type {
34 USB_NONE = 0,
35 USB_PERIPHERAL,
36 USB_HOST,
37 USB_OTG,
38};
39
40/**
41 * OTG control
42 *
43 * OTG_NO_CONTROL Id/VBUS notifications not required. Useful in host
44 * only configuration.
45 * OTG_PHY_CONTROL Id/VBUS notifications comes form USB PHY.
46 * OTG_PMIC_CONTROL Id/VBUS notifications comes from PMIC hardware.
47 * OTG_USER_CONTROL Id/VBUS notifcations comes from User via sysfs.
48 *
49 */
50enum otg_control_type {
51 OTG_NO_CONTROL = 0,
52 OTG_PHY_CONTROL,
53 OTG_PMIC_CONTROL,
54 OTG_USER_CONTROL,
55};
56
57/**
58 * PHY used in
59 *
60 * INVALID_PHY Unsupported PHY
61 * CI_45NM_INTEGRATED_PHY Chipidea 45nm integrated PHY
62 * SNPS_28NM_INTEGRATED_PHY Synopsis 28nm integrated PHY
63 *
64 */
65enum msm_usb_phy_type {
66 INVALID_PHY = 0,
67 CI_45NM_INTEGRATED_PHY,
68 SNPS_28NM_INTEGRATED_PHY,
69};
70
71#define IDEV_CHG_MAX 1500
72#define IUNIT 100
73
74/**
75 * Different states involved in USB charger detection.
76 *
77 * USB_CHG_STATE_UNDEFINED USB charger is not connected or detection
78 * process is not yet started.
79 * USB_CHG_STATE_WAIT_FOR_DCD Waiting for Data pins contact.
80 * USB_CHG_STATE_DCD_DONE Data pin contact is detected.
81 * USB_CHG_STATE_PRIMARY_DONE Primary detection is completed (Detects
82 * between SDP and DCP/CDP).
83 * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
84 * between DCP and CDP).
85 * USB_CHG_STATE_DETECTED USB charger type is determined.
86 *
87 */
88enum usb_chg_state {
89 USB_CHG_STATE_UNDEFINED = 0,
90 USB_CHG_STATE_WAIT_FOR_DCD,
91 USB_CHG_STATE_DCD_DONE,
92 USB_CHG_STATE_PRIMARY_DONE,
93 USB_CHG_STATE_SECONDARY_DONE,
94 USB_CHG_STATE_DETECTED,
95};
96
97/**
98 * USB charger types
99 *
100 * USB_INVALID_CHARGER Invalid USB charger.
101 * USB_SDP_CHARGER Standard downstream port. Refers to a downstream port
102 * on USB2.0 compliant host/hub.
103 * USB_DCP_CHARGER Dedicated charger port (AC charger/ Wall charger).
104 * USB_CDP_CHARGER Charging downstream port. Enumeration can happen and
105 * IDEV_CHG_MAX can be drawn irrespective of USB state.
106 *
107 */
108enum usb_chg_type {
109 USB_INVALID_CHARGER = 0,
110 USB_SDP_CHARGER,
111 USB_DCP_CHARGER,
112 USB_CDP_CHARGER,
113};
114
115/**
116 * struct msm_otg_platform_data - platform device data
117 * for msm_otg driver.
118 * @phy_init_seq: PHY configuration sequence. val, reg pairs
119 * terminated by -1.
120 * @vbus_power: VBUS power on/off routine.
121 * @power_budget: VBUS power budget in mA (0 will be treated as 500mA).
122 * @mode: Supported mode (OTG/peripheral/host).
123 * @otg_control: OTG switch controlled by user/Id pin
124 * @default_mode: Default operational mode. Applicable only if
125 * OTG switch is controller by user.
126 * @pclk_src_name: pclk is derived from ebi1_usb_clk in case of 7x27 and 8k
127 * dfab_usb_hs_clk in case of 8660 and 8960.
128 */
129struct msm_otg_platform_data {
130 int *phy_init_seq;
131 void (*vbus_power)(bool on);
132 unsigned power_budget;
133 enum usb_mode_type mode;
134 enum otg_control_type otg_control;
135 enum usb_mode_type default_mode;
136 enum msm_usb_phy_type phy_type;
137 void (*setup_gpio)(enum usb_otg_state state);
138 char *pclk_src_name;
139 int (*link_clk_reset)(struct clk *link_clk, bool assert);
140 int (*phy_clk_reset)(struct clk *phy_clk);
141};
142
143/**
144 * struct msm_otg: OTG driver data. Shared by HCD and DCD.
145 * @otg: USB OTG Transceiver structure.
146 * @pdata: otg device platform data.
147 * @irq: IRQ number assigned for HSUSB controller.
148 * @clk: clock struct of usb_hs_clk.
149 * @pclk: clock struct of usb_hs_pclk.
150 * @pclk_src: pclk source for voting.
151 * @phy_reset_clk: clock struct of usb_phy_clk.
152 * @core_clk: clock struct of usb_hs_core_clk.
153 * @regs: ioremapped register base address.
154 * @inputs: OTG state machine inputs(Id, SessValid etc).
155 * @sm_work: OTG state machine work.
156 * @in_lpm: indicates low power mode (LPM) state.
157 * @async_int: Async interrupt arrived.
158 * @cur_power: The amount of mA available from downstream port.
159 * @chg_work: Charger detection work.
160 * @chg_state: The state of charger detection process.
161 * @chg_type: The type of charger attached.
162 * @dcd_retires: The retry count used to track Data contact
163 * detection process.
164 */
165struct msm_otg {
166 struct usb_phy phy;
167 struct msm_otg_platform_data *pdata;
168 int irq;
169 struct clk *clk;
170 struct clk *pclk;
171 struct clk *pclk_src;
172 struct clk *phy_reset_clk;
173 struct clk *core_clk;
174 void __iomem *regs;
175#define ID 0
176#define B_SESS_VLD 1
177 unsigned long inputs;
178 struct work_struct sm_work;
179 atomic_t in_lpm;
180 int async_int;
181 unsigned cur_power;
182 struct delayed_work chg_work;
183 enum usb_chg_state chg_state;
184 enum usb_chg_type chg_type;
185 u8 dcd_retries;
186};
187
188#endif