Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/*
2 * Copyright (c) 2010 Google, Inc
3 *
4 * Author:
5 * Colin Cross <ccross@google.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef _MACH_TEGRA_POWERGATE_H_
19#define _MACH_TEGRA_POWERGATE_H_
20
21struct clk;
22struct reset_control;
23
24#define TEGRA_POWERGATE_CPU 0
25#define TEGRA_POWERGATE_3D 1
26#define TEGRA_POWERGATE_VENC 2
27#define TEGRA_POWERGATE_PCIE 3
28#define TEGRA_POWERGATE_VDEC 4
29#define TEGRA_POWERGATE_L2 5
30#define TEGRA_POWERGATE_MPE 6
31#define TEGRA_POWERGATE_HEG 7
32#define TEGRA_POWERGATE_SATA 8
33#define TEGRA_POWERGATE_CPU1 9
34#define TEGRA_POWERGATE_CPU2 10
35#define TEGRA_POWERGATE_CPU3 11
36#define TEGRA_POWERGATE_CELP 12
37#define TEGRA_POWERGATE_3D1 13
38#define TEGRA_POWERGATE_CPU0 14
39#define TEGRA_POWERGATE_C0NC 15
40#define TEGRA_POWERGATE_C1NC 16
41#define TEGRA_POWERGATE_SOR 17
42#define TEGRA_POWERGATE_DIS 18
43#define TEGRA_POWERGATE_DISB 19
44#define TEGRA_POWERGATE_XUSBA 20
45#define TEGRA_POWERGATE_XUSBB 21
46#define TEGRA_POWERGATE_XUSBC 22
47#define TEGRA_POWERGATE_VIC 23
48#define TEGRA_POWERGATE_IRAM 24
49
50#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
51
52#define TEGRA_IO_RAIL_CSIA 0
53#define TEGRA_IO_RAIL_CSIB 1
54#define TEGRA_IO_RAIL_DSI 2
55#define TEGRA_IO_RAIL_MIPI_BIAS 3
56#define TEGRA_IO_RAIL_PEX_BIAS 4
57#define TEGRA_IO_RAIL_PEX_CLK1 5
58#define TEGRA_IO_RAIL_PEX_CLK2 6
59#define TEGRA_IO_RAIL_USB0 9
60#define TEGRA_IO_RAIL_USB1 10
61#define TEGRA_IO_RAIL_USB2 11
62#define TEGRA_IO_RAIL_USB_BIAS 12
63#define TEGRA_IO_RAIL_NAND 13
64#define TEGRA_IO_RAIL_UART 14
65#define TEGRA_IO_RAIL_BB 15
66#define TEGRA_IO_RAIL_AUDIO 17
67#define TEGRA_IO_RAIL_HSIC 19
68#define TEGRA_IO_RAIL_COMP 22
69#define TEGRA_IO_RAIL_HDMI 28
70#define TEGRA_IO_RAIL_PEX_CNTRL 32
71#define TEGRA_IO_RAIL_SDMMC1 33
72#define TEGRA_IO_RAIL_SDMMC3 34
73#define TEGRA_IO_RAIL_SDMMC4 35
74#define TEGRA_IO_RAIL_CAM 36
75#define TEGRA_IO_RAIL_RES 37
76#define TEGRA_IO_RAIL_HV 38
77#define TEGRA_IO_RAIL_DSIB 39
78#define TEGRA_IO_RAIL_DSIC 40
79#define TEGRA_IO_RAIL_DSID 41
80#define TEGRA_IO_RAIL_CSIE 44
81#define TEGRA_IO_RAIL_LVDS 57
82#define TEGRA_IO_RAIL_SYS_DDC 58
83
84#ifdef CONFIG_ARCH_TEGRA
85int tegra_powergate_is_powered(int id);
86int tegra_powergate_power_on(int id);
87int tegra_powergate_power_off(int id);
88int tegra_powergate_remove_clamping(int id);
89
90/* Must be called with clk disabled, and returns with clk enabled */
91int tegra_powergate_sequence_power_up(int id, struct clk *clk,
92 struct reset_control *rst);
93
94int tegra_io_rail_power_on(int id);
95int tegra_io_rail_power_off(int id);
96#else
97static inline int tegra_powergate_is_powered(int id)
98{
99 return -ENOSYS;
100}
101
102static inline int tegra_powergate_power_on(int id)
103{
104 return -ENOSYS;
105}
106
107static inline int tegra_powergate_power_off(int id)
108{
109 return -ENOSYS;
110}
111
112static inline int tegra_powergate_remove_clamping(int id)
113{
114 return -ENOSYS;
115}
116
117static inline int tegra_powergate_sequence_power_up(int id, struct clk *clk,
118 struct reset_control *rst)
119{
120 return -ENOSYS;
121}
122
123static inline int tegra_io_rail_power_on(int id)
124{
125 return -ENOSYS;
126}
127
128static inline int tegra_io_rail_power_off(int id)
129{
130 return -ENOSYS;
131}
132#endif
133
134#endif /* _MACH_TEGRA_POWERGATE_H_ */