Linux kernel mirror (for testing)
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linux
1/*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
17 * Copyright (C) Ashok Raj <ashok.raj@intel.com>
18 * Copyright (C) Shaohua Li <shaohua.li@intel.com>
19 */
20
21#ifndef __DMAR_H__
22#define __DMAR_H__
23
24#include <linux/acpi.h>
25#include <linux/types.h>
26#include <linux/msi.h>
27#include <linux/irqreturn.h>
28
29struct acpi_dmar_header;
30
31/* DMAR Flags */
32#define DMAR_INTR_REMAP 0x1
33#define DMAR_X2APIC_OPT_OUT 0x2
34
35struct intel_iommu;
36
37#ifdef CONFIG_DMAR_TABLE
38extern struct acpi_table_header *dmar_tbl;
39struct dmar_drhd_unit {
40 struct list_head list; /* list of drhd units */
41 struct acpi_dmar_header *hdr; /* ACPI header */
42 u64 reg_base_addr; /* register base address*/
43 struct pci_dev **devices; /* target device array */
44 int devices_cnt; /* target device count */
45 u16 segment; /* PCI domain */
46 u8 ignored:1; /* ignore drhd */
47 u8 include_all:1;
48 struct intel_iommu *iommu;
49};
50
51extern struct list_head dmar_drhd_units;
52
53#define for_each_drhd_unit(drhd) \
54 list_for_each_entry(drhd, &dmar_drhd_units, list)
55
56#define for_each_active_drhd_unit(drhd) \
57 list_for_each_entry(drhd, &dmar_drhd_units, list) \
58 if (drhd->ignored) {} else
59
60#define for_each_active_iommu(i, drhd) \
61 list_for_each_entry(drhd, &dmar_drhd_units, list) \
62 if (i=drhd->iommu, drhd->ignored) {} else
63
64#define for_each_iommu(i, drhd) \
65 list_for_each_entry(drhd, &dmar_drhd_units, list) \
66 if (i=drhd->iommu, 0) {} else
67
68extern int dmar_table_init(void);
69extern int dmar_dev_scope_init(void);
70extern int dmar_parse_dev_scope(void *start, void *end, int *cnt,
71 struct pci_dev ***devices, u16 segment);
72extern void dmar_free_dev_scope(struct pci_dev ***devices, int *cnt);
73
74/* Intel IOMMU detection */
75extern int detect_intel_iommu(void);
76extern int enable_drhd_fault_handling(void);
77#else
78static inline int detect_intel_iommu(void)
79{
80 return -ENODEV;
81}
82
83static inline int dmar_table_init(void)
84{
85 return -ENODEV;
86}
87static inline int enable_drhd_fault_handling(void)
88{
89 return -1;
90}
91#endif /* !CONFIG_DMAR_TABLE */
92
93struct irte {
94 union {
95 struct {
96 __u64 present : 1,
97 fpd : 1,
98 dst_mode : 1,
99 redir_hint : 1,
100 trigger_mode : 1,
101 dlvry_mode : 3,
102 avail : 4,
103 __reserved_1 : 4,
104 vector : 8,
105 __reserved_2 : 8,
106 dest_id : 32;
107 };
108 __u64 low;
109 };
110
111 union {
112 struct {
113 __u64 sid : 16,
114 sq : 2,
115 svt : 2,
116 __reserved_3 : 44;
117 };
118 __u64 high;
119 };
120};
121
122enum {
123 IRQ_REMAP_XAPIC_MODE,
124 IRQ_REMAP_X2APIC_MODE,
125};
126
127/* Can't use the common MSI interrupt functions
128 * since DMAR is not a pci device
129 */
130struct irq_data;
131extern void dmar_msi_unmask(struct irq_data *data);
132extern void dmar_msi_mask(struct irq_data *data);
133extern void dmar_msi_read(int irq, struct msi_msg *msg);
134extern void dmar_msi_write(int irq, struct msi_msg *msg);
135extern int dmar_set_interrupt(struct intel_iommu *iommu);
136extern irqreturn_t dmar_fault(int irq, void *dev_id);
137extern int arch_setup_dmar_msi(unsigned int irq);
138
139#ifdef CONFIG_INTEL_IOMMU
140extern int iommu_detected, no_iommu;
141extern struct list_head dmar_rmrr_units;
142struct dmar_rmrr_unit {
143 struct list_head list; /* list of rmrr units */
144 struct acpi_dmar_header *hdr; /* ACPI header */
145 u64 base_address; /* reserved base address*/
146 u64 end_address; /* reserved end address */
147 struct pci_dev **devices; /* target devices */
148 int devices_cnt; /* target device count */
149};
150
151#define for_each_rmrr_units(rmrr) \
152 list_for_each_entry(rmrr, &dmar_rmrr_units, list)
153
154struct dmar_atsr_unit {
155 struct list_head list; /* list of ATSR units */
156 struct acpi_dmar_header *hdr; /* ACPI header */
157 struct pci_dev **devices; /* target devices */
158 int devices_cnt; /* target device count */
159 u8 include_all:1; /* include all ports */
160};
161
162int dmar_parse_rmrr_atsr_dev(void);
163extern int dmar_parse_one_rmrr(struct acpi_dmar_header *header);
164extern int dmar_parse_one_atsr(struct acpi_dmar_header *header);
165extern int intel_iommu_init(void);
166#else /* !CONFIG_INTEL_IOMMU: */
167static inline int intel_iommu_init(void) { return -ENODEV; }
168static inline int dmar_parse_one_rmrr(struct acpi_dmar_header *header)
169{
170 return 0;
171}
172static inline int dmar_parse_one_atsr(struct acpi_dmar_header *header)
173{
174 return 0;
175}
176static inline int dmar_parse_rmrr_atsr_dev(void)
177{
178 return 0;
179}
180#endif /* CONFIG_INTEL_IOMMU */
181
182#endif /* __DMAR_H__ */