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1/*
2 * TI clock drivers support
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#ifndef __LINUX_CLK_TI_H__
16#define __LINUX_CLK_TI_H__
17
18#include <linux/clkdev.h>
19
20/**
21 * struct dpll_data - DPLL registers and integration data
22 * @mult_div1_reg: register containing the DPLL M and N bitfields
23 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
24 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
25 * @clk_bypass: struct clk pointer to the clock's bypass clock input
26 * @clk_ref: struct clk pointer to the clock's reference clock input
27 * @control_reg: register containing the DPLL mode bitfield
28 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
29 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
30 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
31 * @last_rounded_m4xen: cache of the last M4X result of
32 * omap4_dpll_regm4xen_round_rate()
33 * @last_rounded_lpmode: cache of the last lpmode result of
34 * omap4_dpll_lpmode_recalc()
35 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
36 * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
37 * @min_divider: minimum valid non-bypass divider value (actual)
38 * @max_divider: maximum valid non-bypass divider value (actual)
39 * @modes: possible values of @enable_mask
40 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
41 * @idlest_reg: register containing the DPLL idle status bitfield
42 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
43 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
44 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
45 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
46 * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
47 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
48 * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
49 * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
50 * @flags: DPLL type/features (see below)
51 *
52 * Possible values for @flags:
53 * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
54 *
55 * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
56 *
57 * XXX Some DPLLs have multiple bypass inputs, so it's not technically
58 * correct to only have one @clk_bypass pointer.
59 *
60 * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
61 * @last_rounded_n) should be separated from the runtime-fixed fields
62 * and placed into a different structure, so that the runtime-fixed data
63 * can be placed into read-only space.
64 */
65struct dpll_data {
66 void __iomem *mult_div1_reg;
67 u32 mult_mask;
68 u32 div1_mask;
69 struct clk *clk_bypass;
70 struct clk *clk_ref;
71 void __iomem *control_reg;
72 u32 enable_mask;
73 unsigned long last_rounded_rate;
74 u16 last_rounded_m;
75 u8 last_rounded_m4xen;
76 u8 last_rounded_lpmode;
77 u16 max_multiplier;
78 u8 last_rounded_n;
79 u8 min_divider;
80 u16 max_divider;
81 u8 modes;
82 void __iomem *autoidle_reg;
83 void __iomem *idlest_reg;
84 u32 autoidle_mask;
85 u32 freqsel_mask;
86 u32 idlest_mask;
87 u32 dco_mask;
88 u32 sddiv_mask;
89 u32 lpmode_mask;
90 u32 m4xen_mask;
91 u8 auto_recal_bit;
92 u8 recal_en_bit;
93 u8 recal_st_bit;
94 u8 flags;
95};
96
97struct clk_hw_omap_ops;
98
99/**
100 * struct clk_hw_omap - OMAP struct clk
101 * @node: list_head connecting this clock into the full clock list
102 * @enable_reg: register to write to enable the clock (see @enable_bit)
103 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
104 * @flags: see "struct clk.flags possibilities" above
105 * @clksel_reg: for clksel clks, register va containing src/divisor select
106 * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
107 * @clksel: for clksel clks, pointer to struct clksel for this clock
108 * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
109 * @clkdm_name: clockdomain name that this clock is contained in
110 * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
111 * @ops: clock ops for this clock
112 */
113struct clk_hw_omap {
114 struct clk_hw hw;
115 struct list_head node;
116 unsigned long fixed_rate;
117 u8 fixed_div;
118 void __iomem *enable_reg;
119 u8 enable_bit;
120 u8 flags;
121 void __iomem *clksel_reg;
122 u32 clksel_mask;
123 const struct clksel *clksel;
124 struct dpll_data *dpll_data;
125 const char *clkdm_name;
126 struct clockdomain *clkdm;
127 const struct clk_hw_omap_ops *ops;
128};
129
130/*
131 * struct clk_hw_omap.flags possibilities
132 *
133 * XXX document the rest of the clock flags here
134 *
135 * ENABLE_REG_32BIT: (OMAP1 only) clock control register must be accessed
136 * with 32bit ops, by default OMAP1 uses 16bit ops.
137 * CLOCK_IDLE_CONTROL: (OMAP1 only) clock has autoidle support.
138 * CLOCK_NO_IDLE_PARENT: (OMAP1 only) when clock is enabled, its parent
139 * clock is put to no-idle mode.
140 * ENABLE_ON_INIT: Clock is enabled on init.
141 * INVERT_ENABLE: By default, clock enable bit behavior is '1' enable, '0'
142 * disable. This inverts the behavior making '0' enable and '1' disable.
143 * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
144 * bits share the same register. This flag allows the
145 * omap4_dpllmx*() code to determine which GATE_CTRL bit field
146 * should be used. This is a temporary solution - a better approach
147 * would be to associate clock type-specific data with the clock,
148 * similar to the struct dpll_data approach.
149 * MEMMAP_ADDRESSING: Use memmap addressing to access clock registers.
150 */
151#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
152#define CLOCK_IDLE_CONTROL (1 << 1)
153#define CLOCK_NO_IDLE_PARENT (1 << 2)
154#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
155#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
156#define CLOCK_CLKOUTX2 (1 << 5)
157#define MEMMAP_ADDRESSING (1 << 6)
158
159/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
160#define DPLL_LOW_POWER_STOP 0x1
161#define DPLL_LOW_POWER_BYPASS 0x5
162#define DPLL_LOCKED 0x7
163
164/* DPLL Type and DCO Selection Flags */
165#define DPLL_J_TYPE 0x1
166
167/* Composite clock component types */
168enum {
169 CLK_COMPONENT_TYPE_GATE = 0,
170 CLK_COMPONENT_TYPE_DIVIDER,
171 CLK_COMPONENT_TYPE_MUX,
172 CLK_COMPONENT_TYPE_MAX,
173};
174
175/**
176 * struct ti_dt_clk - OMAP DT clock alias declarations
177 * @lk: clock lookup definition
178 * @node_name: clock DT node to map to
179 */
180struct ti_dt_clk {
181 struct clk_lookup lk;
182 char *node_name;
183};
184
185#define DT_CLK(dev, con, name) \
186 { \
187 .lk = { \
188 .dev_id = dev, \
189 .con_id = con, \
190 }, \
191 .node_name = name, \
192 }
193
194/* Maximum number of clock memmaps */
195#define CLK_MAX_MEMMAPS 4
196
197typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);
198
199/**
200 * struct clk_omap_reg - OMAP register declaration
201 * @offset: offset from the master IP module base address
202 * @index: index of the master IP module
203 */
204struct clk_omap_reg {
205 u16 offset;
206 u16 index;
207};
208
209/**
210 * struct ti_clk_ll_ops - low-level register access ops for a clock
211 * @clk_readl: pointer to register read function
212 * @clk_writel: pointer to register write function
213 *
214 * Low-level register access ops are generally used by the basic clock types
215 * (clk-gate, clk-mux, clk-divider etc.) to provide support for various
216 * low-level hardware interfaces (direct MMIO, regmap etc.), but can also be
217 * used by other hardware-specific clock drivers if needed.
218 */
219struct ti_clk_ll_ops {
220 u32 (*clk_readl)(void __iomem *reg);
221 void (*clk_writel)(u32 val, void __iomem *reg);
222};
223
224extern struct ti_clk_ll_ops *ti_clk_ll_ops;
225
226extern const struct clk_ops ti_clk_divider_ops;
227extern const struct clk_ops ti_clk_mux_ops;
228
229#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
230
231void omap2_init_clk_hw_omap_clocks(struct clk *clk);
232int omap3_noncore_dpll_enable(struct clk_hw *hw);
233void omap3_noncore_dpll_disable(struct clk_hw *hw);
234int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
235 unsigned long parent_rate);
236unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
237 unsigned long parent_rate);
238long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
239 unsigned long target_rate,
240 unsigned long *parent_rate);
241u8 omap2_init_dpll_parent(struct clk_hw *hw);
242unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
243long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
244 unsigned long *parent_rate);
245void omap2_init_clk_clkdm(struct clk_hw *clk);
246unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
247 unsigned long parent_rate);
248int omap3_clkoutx2_set_rate(struct clk_hw *hw, unsigned long rate,
249 unsigned long parent_rate);
250long omap3_clkoutx2_round_rate(struct clk_hw *hw, unsigned long rate,
251 unsigned long *prate);
252int omap2_clkops_enable_clkdm(struct clk_hw *hw);
253void omap2_clkops_disable_clkdm(struct clk_hw *hw);
254int omap2_clk_disable_autoidle_all(void);
255void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
256int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
257 unsigned long parent_rate);
258int omap2_dflt_clk_enable(struct clk_hw *hw);
259void omap2_dflt_clk_disable(struct clk_hw *hw);
260int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
261void omap3_clk_lock_dpll5(void);
262
263void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index);
264void ti_dt_clocks_register(struct ti_dt_clk *oclks);
265void ti_dt_clk_init_provider(struct device_node *np, int index);
266void ti_dt_clockdomains_setup(void);
267int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
268 ti_of_clk_init_cb_t func);
269int of_ti_clk_autoidle_setup(struct device_node *node);
270int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
271
272int omap3430_dt_clk_init(void);
273int omap3630_dt_clk_init(void);
274int am35xx_dt_clk_init(void);
275int ti81xx_dt_clk_init(void);
276int omap4xxx_dt_clk_init(void);
277int omap5xxx_dt_clk_init(void);
278int dra7xx_dt_clk_init(void);
279int am33xx_dt_clk_init(void);
280int am43xx_dt_clk_init(void);
281
282#ifdef CONFIG_OF
283void of_ti_clk_allow_autoidle_all(void);
284void of_ti_clk_deny_autoidle_all(void);
285#else
286static inline void of_ti_clk_allow_autoidle_all(void) { }
287static inline void of_ti_clk_deny_autoidle_all(void) { }
288#endif
289
290extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
291extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
292extern const struct clk_hw_omap_ops clkhwops_wait;
293extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
294extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
295extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
296extern const struct clk_hw_omap_ops clkhwops_iclk;
297extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
298extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
299extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
300extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
301
302#endif