Linux kernel mirror (for testing)
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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 2004 Ralf Baechle
7 * Copyright (C) 2004 Maciej W. Rozycki
8 */
9#ifndef __ASM_CPU_FEATURES_H
10#define __ASM_CPU_FEATURES_H
11
12#include <asm/cpu.h>
13#include <asm/cpu-info.h>
14#include <cpu-feature-overrides.h>
15
16/*
17 * SMP assumption: Options of CPU 0 are a superset of all processors.
18 * This is true for all known MIPS systems.
19 */
20#ifndef cpu_has_tlb
21#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
22#endif
23#ifndef cpu_has_tlbinv
24#define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV)
25#endif
26#ifndef cpu_has_segments
27#define cpu_has_segments (cpu_data[0].options & MIPS_CPU_SEGMENTS)
28#endif
29
30
31/*
32 * For the moment we don't consider R6000 and R8000 so we can assume that
33 * anything that doesn't support R4000-style exceptions and interrupts is
34 * R3000-like. Users should still treat these two macro definitions as
35 * opaque.
36 */
37#ifndef cpu_has_3kex
38#define cpu_has_3kex (!cpu_has_4kex)
39#endif
40#ifndef cpu_has_4kex
41#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
42#endif
43#ifndef cpu_has_3k_cache
44#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
45#endif
46#define cpu_has_6k_cache 0
47#define cpu_has_8k_cache 0
48#ifndef cpu_has_4k_cache
49#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
50#endif
51#ifndef cpu_has_tx39_cache
52#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
53#endif
54#ifndef cpu_has_octeon_cache
55#define cpu_has_octeon_cache 0
56#endif
57#ifndef cpu_has_fpu
58#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
59#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
60#else
61#define raw_cpu_has_fpu cpu_has_fpu
62#endif
63#ifndef cpu_has_32fpr
64#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
65#endif
66#ifndef cpu_has_counter
67#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
68#endif
69#ifndef cpu_has_watch
70#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
71#endif
72#ifndef cpu_has_divec
73#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
74#endif
75#ifndef cpu_has_vce
76#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
77#endif
78#ifndef cpu_has_cache_cdex_p
79#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
80#endif
81#ifndef cpu_has_cache_cdex_s
82#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
83#endif
84#ifndef cpu_has_prefetch
85#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
86#endif
87#ifndef cpu_has_mcheck
88#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
89#endif
90#ifndef cpu_has_ejtag
91#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
92#endif
93#ifndef cpu_has_llsc
94#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
95#endif
96#ifndef kernel_uses_llsc
97#define kernel_uses_llsc cpu_has_llsc
98#endif
99#ifndef cpu_has_mips16
100#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
101#endif
102#ifndef cpu_has_mdmx
103#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
104#endif
105#ifndef cpu_has_mips3d
106#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
107#endif
108#ifndef cpu_has_smartmips
109#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
110#endif
111#ifndef cpu_has_rixi
112#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
113#endif
114#ifndef cpu_has_mmips
115# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
116# define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
117# else
118# define cpu_has_mmips 0
119# endif
120#endif
121#ifndef cpu_has_vtag_icache
122#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
123#endif
124#ifndef cpu_has_dc_aliases
125#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
126#endif
127#ifndef cpu_has_ic_fills_f_dc
128#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
129#endif
130#ifndef cpu_has_pindexed_dcache
131#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
132#endif
133#ifndef cpu_has_local_ebase
134#define cpu_has_local_ebase 1
135#endif
136
137/*
138 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
139 * such as the R10000 have I-Caches that snoop local stores; the embedded ones
140 * don't. For maintaining I-cache coherency this means we need to flush the
141 * D-cache all the way back to whever the I-cache does refills from, so the
142 * I-cache has a chance to see the new data at all. Then we have to flush the
143 * I-cache also.
144 * Note we may have been rescheduled and may no longer be running on the CPU
145 * that did the store so we can't optimize this into only doing the flush on
146 * the local CPU.
147 */
148#ifndef cpu_icache_snoops_remote_store
149#ifdef CONFIG_SMP
150#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
151#else
152#define cpu_icache_snoops_remote_store 1
153#endif
154#endif
155
156#ifndef cpu_has_mips_2
157# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
158#endif
159#ifndef cpu_has_mips_3
160# define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III)
161#endif
162#ifndef cpu_has_mips_4
163# define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
164#endif
165#ifndef cpu_has_mips_5
166# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
167#endif
168#ifndef cpu_has_mips32r1
169# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
170#endif
171#ifndef cpu_has_mips32r2
172# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
173#endif
174#ifndef cpu_has_mips64r1
175# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
176#endif
177#ifndef cpu_has_mips64r2
178# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
179#endif
180
181/*
182 * Shortcuts ...
183 */
184#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2)
185#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)
186#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
187#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
188#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
189 cpu_has_mips64r1 | cpu_has_mips64r2)
190
191#ifndef cpu_has_mips_r2_exec_hazard
192#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
193#endif
194
195/*
196 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
197 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and
198 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
199 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
200 */
201#ifndef cpu_has_clo_clz
202#define cpu_has_clo_clz cpu_has_mips_r
203#endif
204
205#ifndef cpu_has_dsp
206#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
207#endif
208
209#ifndef cpu_has_dsp2
210#define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P)
211#endif
212
213#ifndef cpu_has_mipsmt
214#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
215#endif
216
217#ifndef cpu_has_userlocal
218#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
219#endif
220
221#ifdef CONFIG_32BIT
222# ifndef cpu_has_nofpuex
223# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
224# endif
225# ifndef cpu_has_64bits
226# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
227# endif
228# ifndef cpu_has_64bit_zero_reg
229# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
230# endif
231# ifndef cpu_has_64bit_gp_regs
232# define cpu_has_64bit_gp_regs 0
233# endif
234# ifndef cpu_has_64bit_addresses
235# define cpu_has_64bit_addresses 0
236# endif
237# ifndef cpu_vmbits
238# define cpu_vmbits 31
239# endif
240#endif
241
242#ifdef CONFIG_64BIT
243# ifndef cpu_has_nofpuex
244# define cpu_has_nofpuex 0
245# endif
246# ifndef cpu_has_64bits
247# define cpu_has_64bits 1
248# endif
249# ifndef cpu_has_64bit_zero_reg
250# define cpu_has_64bit_zero_reg 1
251# endif
252# ifndef cpu_has_64bit_gp_regs
253# define cpu_has_64bit_gp_regs 1
254# endif
255# ifndef cpu_has_64bit_addresses
256# define cpu_has_64bit_addresses 1
257# endif
258# ifndef cpu_vmbits
259# define cpu_vmbits cpu_data[0].vmbits
260# define __NEED_VMBITS_PROBE
261# endif
262#endif
263
264#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
265# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
266#elif !defined(cpu_has_vint)
267# define cpu_has_vint 0
268#endif
269
270#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
271# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
272#elif !defined(cpu_has_veic)
273# define cpu_has_veic 0
274#endif
275
276#ifndef cpu_has_inclusive_pcaches
277#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
278#endif
279
280#ifndef cpu_dcache_line_size
281#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
282#endif
283#ifndef cpu_icache_line_size
284#define cpu_icache_line_size() cpu_data[0].icache.linesz
285#endif
286#ifndef cpu_scache_line_size
287#define cpu_scache_line_size() cpu_data[0].scache.linesz
288#endif
289
290#ifndef cpu_hwrena_impl_bits
291#define cpu_hwrena_impl_bits 0
292#endif
293
294#ifndef cpu_has_perf_cntr_intr_bit
295#define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI)
296#endif
297
298#ifndef cpu_has_vz
299#define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ)
300#endif
301
302#endif /* __ASM_CPU_FEATURES_H */