tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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kernel / arch / arm / mach-imx / clk-imx6q.c
at v3.14 494 lines 33 kB view raw
1/* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * Copyright 2011 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13#include <linux/init.h> 14#include <linux/types.h> 15#include <linux/clk.h> 16#include <linux/clkdev.h> 17#include <linux/err.h> 18#include <linux/io.h> 19#include <linux/of.h> 20#include <linux/of_address.h> 21#include <linux/of_irq.h> 22 23#include "clk.h" 24#include "common.h" 25#include "hardware.h" 26 27static const char *step_sels[] = { "osc", "pll2_pfd2_396m", }; 28static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; 29static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; 30static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", }; 31static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; 32static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; 33static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; 34static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", }; 35static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; 36static const char *gpu_axi_sels[] = { "axi", "ahb", }; 37static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", }; 38static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", }; 39static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", }; 40static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; 41static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", }; 42static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", }; 43static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; 44static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; 45static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; 46static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; 47static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", }; 48static const char *pcie_axi_sels[] = { "axi", "ahb", }; 49static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", }; 50static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; 51static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", }; 52static const char *emi_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", }; 53static const char *emi_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", }; 54static const char *vdo_axi_sels[] = { "axi", "ahb", }; 55static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", }; 56static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", 57 "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", 58 "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", }; 59static const char *cko2_sels[] = { 60 "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1", 61 "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi", 62 "usdhc3", "dummy", "arm", "ipu1", 63 "ipu2", "vdo_axi", "osc", "gpu2d_core", 64 "gpu3d_core", "usdhc2", "ssi1", "ssi2", 65 "ssi3", "gpu3d_shader", "vpu_axi", "can_root", 66 "ldb_di0", "ldb_di1", "esai", "eim_slow", 67 "uart_serial", "spdif", "asrc", "hsi_tx", 68}; 69static const char *cko_sels[] = { "cko1", "cko2", }; 70static const char *lvds_sels[] = { 71 "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", 72 "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref", 73 "pcie_ref", "sata_ref", 74}; 75 76enum mx6q_clks { 77 dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, 78 pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m, 79 pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw, 80 periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel, 81 esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel, 82 gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel, 83 ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel, 84 ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, 85 ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel, 86 usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel, 87 emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2, 88 periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf, 89 asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root, 90 gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf, 91 ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre, 92 ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf, 93 ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf, 94 usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf, 95 emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf, 96 mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial, 97 can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet, 98 esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb, 99 hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2, 100 ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi, 101 mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch, 102 gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1, 103 ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, 104 usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, 105 pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg, 106 ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, 107 sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, 108 usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, 109 spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div, 110 lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, clk_max 111}; 112 113static struct clk *clk[clk_max]; 114static struct clk_onecell_data clk_data; 115 116static enum mx6q_clks const clks_init_on[] __initconst = { 117 mmdc_ch0_axi, rom, arm, 118}; 119 120static struct clk_div_table clk_enet_ref_table[] = { 121 { .val = 0, .div = 20, }, 122 { .val = 1, .div = 10, }, 123 { .val = 2, .div = 5, }, 124 { .val = 3, .div = 4, }, 125 { /* sentinel */ } 126}; 127 128static struct clk_div_table post_div_table[] = { 129 { .val = 2, .div = 1, }, 130 { .val = 1, .div = 2, }, 131 { .val = 0, .div = 4, }, 132 { /* sentinel */ } 133}; 134 135static struct clk_div_table video_div_table[] = { 136 { .val = 0, .div = 1, }, 137 { .val = 1, .div = 2, }, 138 { .val = 2, .div = 1, }, 139 { .val = 3, .div = 4, }, 140 { /* sentinel */ } 141}; 142 143static void __init imx6q_clocks_init(struct device_node *ccm_node) 144{ 145 struct device_node *np; 146 void __iomem *base; 147 int i, irq; 148 int ret; 149 150 clk[dummy] = imx_clk_fixed("dummy", 0); 151 clk[ckil] = imx_obtain_fixed_clock("ckil", 0); 152 clk[ckih] = imx_obtain_fixed_clock("ckih1", 0); 153 clk[osc] = imx_obtain_fixed_clock("osc", 0); 154 155 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); 156 base = of_iomap(np, 0); 157 WARN_ON(!base); 158 159 /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */ 160 if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { 161 post_div_table[1].div = 1; 162 post_div_table[2].div = 1; 163 video_div_table[1].div = 1; 164 video_div_table[2].div = 1; 165 }; 166 167 /* type name parent_name base div_mask */ 168 clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); 169 clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1); 170 clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3); 171 clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f); 172 clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); 173 clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); 174 clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3); 175 176 /* 177 * Bit 20 is the reserved and read-only bit, we do this only for: 178 * - Do nothing for usbphy clk_enable/disable 179 * - Keep refcount when do usbphy clk_enable/disable, in that case, 180 * the clk framework may need to enable/disable usbphy's parent 181 */ 182 clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); 183 clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); 184 185 /* 186 * usbphy*_gate needs to be on after system boots up, and software 187 * never needs to control it anymore. 188 */ 189 clk[usbphy1_gate] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); 190 clk[usbphy2_gate] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); 191 192 clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5); 193 clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4); 194 195 clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20); 196 clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); 197 198 clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, 199 base + 0xe0, 0, 2, 0, clk_enet_ref_table, 200 &imx_ccm_lock); 201 202 clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); 203 clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); 204 205 /* 206 * lvds1_gate and lvds2_gate are pseudo-gates. Both can be 207 * independently configured as clock inputs or outputs. We treat 208 * the "output_enable" bit as a gate, even though it's really just 209 * enabling clock output. 210 */ 211 clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10); 212 clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11); 213 214 /* name parent_name reg idx */ 215 clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); 216 clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); 217 clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); 218 clk[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); 219 clk[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); 220 clk[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); 221 clk[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); 222 223 /* name parent_name mult div */ 224 clk[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2); 225 clk[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); 226 clk[pll3_80m] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); 227 clk[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); 228 clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2); 229 230 clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); 231 clk[pll4_audio_div] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); 232 clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); 233 clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); 234 235 np = ccm_node; 236 base = of_iomap(np, 0); 237 WARN_ON(!base); 238 239 imx6q_pm_set_ccm_base(base); 240 241 /* name reg shift width parent_names num_parents */ 242 clk[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); 243 clk[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); 244 clk[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); 245 clk[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); 246 clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); 247 clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); 248 clk[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); 249 clk[esai_sel] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); 250 clk[asrc_sel] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); 251 clk[spdif_sel] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); 252 clk[gpu2d_axi] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); 253 clk[gpu3d_axi] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); 254 clk[gpu2d_core_sel] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); 255 clk[gpu3d_core_sel] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels)); 256 clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); 257 clk[ipu1_sel] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); 258 clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); 259 clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); 260 clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); 261 clk[ipu1_di0_pre_sel] = imx_clk_mux("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); 262 clk[ipu1_di1_pre_sel] = imx_clk_mux("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); 263 clk[ipu2_di0_pre_sel] = imx_clk_mux("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); 264 clk[ipu2_di1_pre_sel] = imx_clk_mux("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); 265 clk[ipu1_di0_sel] = imx_clk_mux("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels)); 266 clk[ipu1_di1_sel] = imx_clk_mux("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels)); 267 clk[ipu2_di0_sel] = imx_clk_mux("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels)); 268 clk[ipu2_di1_sel] = imx_clk_mux("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels)); 269 clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels)); 270 clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); 271 clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); 272 clk[ssi2_sel] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); 273 clk[ssi3_sel] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); 274 clk[usdhc1_sel] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 275 clk[usdhc2_sel] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 276 clk[usdhc3_sel] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 277 clk[usdhc4_sel] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 278 clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); 279 clk[emi_sel] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup); 280 clk[emi_slow_sel] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup); 281 clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); 282 clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); 283 clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); 284 clk[cko2_sel] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels)); 285 clk[cko] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels)); 286 287 /* name reg shift width busy: reg, shift parent_names num_parents */ 288 clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); 289 clk[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); 290 291 /* name parent_name reg shift width */ 292 clk[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); 293 clk[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); 294 clk[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); 295 clk[ipg_per] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup); 296 clk[esai_pred] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); 297 clk[esai_podf] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); 298 clk[asrc_pred] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3); 299 clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3); 300 clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); 301 clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); 302 clk[can_root] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6); 303 clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); 304 clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); 305 clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3); 306 clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3); 307 clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3); 308 clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3); 309 clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); 310 clk[ldb_di0_podf] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0); 311 clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); 312 clk[ldb_di1_podf] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0); 313 clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3); 314 clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3); 315 clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3); 316 clk[ipu2_di1_pre] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3); 317 clk[hsi_tx_podf] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3); 318 clk[ssi1_pred] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); 319 clk[ssi1_podf] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); 320 clk[ssi2_pred] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); 321 clk[ssi2_podf] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); 322 clk[ssi3_pred] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); 323 clk[ssi3_podf] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); 324 clk[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6); 325 clk[usdhc1_podf] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); 326 clk[usdhc2_podf] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); 327 clk[usdhc3_podf] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); 328 clk[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); 329 clk[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); 330 clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); 331 clk[emi_podf] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup); 332 clk[emi_slow_podf] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup); 333 clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); 334 clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); 335 clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3); 336 337 /* name parent_name reg shift width busy: reg, shift */ 338 clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); 339 clk[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4); 340 clk[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); 341 clk[arm] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); 342 clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); 343 344 /* name parent_name reg shift */ 345 clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); 346 clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6); 347 clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); 348 clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); 349 clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); 350 clk[can2_serial] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20); 351 clk[ecspi1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); 352 clk[ecspi2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); 353 clk[ecspi3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); 354 clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); 355 clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); 356 clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); 357 clk[esai] = imx_clk_gate2("esai", "esai_podf", base + 0x6c, 16); 358 clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); 359 clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); 360 if (cpu_is_imx6dl()) 361 /* 362 * The multiplexer and divider of imx6q clock gpu3d_shader get 363 * redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl. 364 */ 365 clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24); 366 else 367 clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); 368 clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26); 369 clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0); 370 clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4); 371 clk[i2c1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6); 372 clk[i2c2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8); 373 clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10); 374 clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12); 375 clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14); 376 clk[vdoa] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26); 377 clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0); 378 clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2); 379 clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4); 380 clk[ipu2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6); 381 clk[ipu2_di0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8); 382 clk[ldb_di0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12); 383 clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14); 384 clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); 385 clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16); 386 if (cpu_is_imx6dl()) 387 /* 388 * The multiplexer and divider of the imx6q clock gpu2d get 389 * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl. 390 */ 391 clk[mlb] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18); 392 else 393 clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18); 394 clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20); 395 clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22); 396 clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); 397 clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); 398 clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); 399 clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); 400 clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); 401 clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18); 402 clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20); 403 clk[pwm4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22); 404 clk[gpmi_bch_apb] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24); 405 clk[gpmi_bch] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26); 406 clk[gpmi_io] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28); 407 clk[gpmi_apb] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); 408 clk[rom] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); 409 clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4); 410 clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); 411 clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); 412 clk[spdif] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14); 413 clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18); 414 clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20); 415 clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22); 416 clk[uart_ipg] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); 417 clk[uart_serial] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26); 418 clk[usboh3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); 419 clk[usdhc1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); 420 clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); 421 clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); 422 clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); 423 clk[eim_slow] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10); 424 clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); 425 clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); 426 clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); 427 clk[cko2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24); 428 429 for (i = 0; i < ARRAY_SIZE(clk); i++) 430 if (IS_ERR(clk[i])) 431 pr_err("i.MX6q clk %d: register failed with %ld\n", 432 i, PTR_ERR(clk[i])); 433 434 clk_data.clks = clk; 435 clk_data.clk_num = ARRAY_SIZE(clk); 436 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 437 438 clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0"); 439 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); 440 clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL); 441 clk_register_clkdev(clk[ahb], "ahb", NULL); 442 clk_register_clkdev(clk[cko1], "cko1", NULL); 443 clk_register_clkdev(clk[arm], NULL, "cpu0"); 444 clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL); 445 clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL); 446 447 if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || 448 cpu_is_imx6dl()) { 449 clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); 450 clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]); 451 } 452 453 /* 454 * The gpmi needs 100MHz frequency in the EDO/Sync mode, 455 * We can not get the 100MHz from the pll2_pfd0_352m. 456 * So choose pll2_pfd2_396m as enfc_sel's parent. 457 */ 458 clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]); 459 460 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) 461 clk_prepare_enable(clk[clks_init_on[i]]); 462 463 if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { 464 clk_prepare_enable(clk[usbphy1_gate]); 465 clk_prepare_enable(clk[usbphy2_gate]); 466 } 467 468 /* 469 * Let's initially set up CLKO with OSC24M, since this configuration 470 * is widely used by imx6q board designs to clock audio codec. 471 */ 472 ret = clk_set_parent(clk[cko2_sel], clk[osc]); 473 if (!ret) 474 ret = clk_set_parent(clk[cko], clk[cko2]); 475 if (ret) 476 pr_warn("failed to set up CLKO: %d\n", ret); 477 478 /* Audio-related clocks configuration */ 479 clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]); 480 481 /* All existing boards with PCIe use LVDS1 */ 482 if (IS_ENABLED(CONFIG_PCI_IMX6)) 483 clk_set_parent(clk[lvds1_sel], clk[sata_ref]); 484 485 /* Set initial power mode */ 486 imx6q_set_lpm(WAIT_CLOCKED); 487 488 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"); 489 base = of_iomap(np, 0); 490 WARN_ON(!base); 491 irq = irq_of_parse_and_map(np, 0); 492 mxc_timer_init(base, irq); 493} 494CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);