tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * max14577-private.h - Common API for the Maxim 14577 internal sub chip
3 *
4 * Copyright (C) 2013 Samsung Electrnoics
5 * Chanwoo Choi <cw00.choi@samsung.com>
6 * Krzysztof Kozlowski <k.kozlowski@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __MAX14577_PRIVATE_H__
20#define __MAX14577_PRIVATE_H__
21
22#include <linux/i2c.h>
23#include <linux/regmap.h>
24
25#define MAX14577_REG_INVALID (0xff)
26
27/* Slave addr = 0x4A: Interrupt */
28enum max14577_reg {
29 MAX14577_REG_DEVICEID = 0x00,
30 MAX14577_REG_INT1 = 0x01,
31 MAX14577_REG_INT2 = 0x02,
32 MAX14577_REG_INT3 = 0x03,
33 MAX14577_REG_STATUS1 = 0x04,
34 MAX14577_REG_STATUS2 = 0x05,
35 MAX14577_REG_STATUS3 = 0x06,
36 MAX14577_REG_INTMASK1 = 0x07,
37 MAX14577_REG_INTMASK2 = 0x08,
38 MAX14577_REG_INTMASK3 = 0x09,
39 MAX14577_REG_CDETCTRL1 = 0x0A,
40 MAX14577_REG_RFU = 0x0B,
41 MAX14577_REG_CONTROL1 = 0x0C,
42 MAX14577_REG_CONTROL2 = 0x0D,
43 MAX14577_REG_CONTROL3 = 0x0E,
44 MAX14577_REG_CHGCTRL1 = 0x0F,
45 MAX14577_REG_CHGCTRL2 = 0x10,
46 MAX14577_REG_CHGCTRL3 = 0x11,
47 MAX14577_REG_CHGCTRL4 = 0x12,
48 MAX14577_REG_CHGCTRL5 = 0x13,
49 MAX14577_REG_CHGCTRL6 = 0x14,
50 MAX14577_REG_CHGCTRL7 = 0x15,
51
52 MAX14577_REG_END,
53};
54
55/* Slave addr = 0x4A: MUIC */
56enum max14577_muic_reg {
57 MAX14577_MUIC_REG_STATUS1 = 0x04,
58 MAX14577_MUIC_REG_STATUS2 = 0x05,
59 MAX14577_MUIC_REG_CONTROL1 = 0x0C,
60 MAX14577_MUIC_REG_CONTROL3 = 0x0E,
61
62 MAX14577_MUIC_REG_END,
63};
64
65enum max14577_muic_charger_type {
66 MAX14577_CHARGER_TYPE_NONE = 0,
67 MAX14577_CHARGER_TYPE_USB,
68 MAX14577_CHARGER_TYPE_DOWNSTREAM_PORT,
69 MAX14577_CHARGER_TYPE_DEDICATED_CHG,
70 MAX14577_CHARGER_TYPE_SPECIAL_500MA,
71 MAX14577_CHARGER_TYPE_SPECIAL_1A,
72 MAX14577_CHARGER_TYPE_RESERVED,
73 MAX14577_CHARGER_TYPE_DEAD_BATTERY = 7,
74};
75
76/* MAX14577 interrupts */
77#define INT1_ADC_MASK (0x1 << 0)
78#define INT1_ADCLOW_MASK (0x1 << 1)
79#define INT1_ADCERR_MASK (0x1 << 2)
80
81#define INT2_CHGTYP_MASK (0x1 << 0)
82#define INT2_CHGDETRUN_MASK (0x1 << 1)
83#define INT2_DCDTMR_MASK (0x1 << 2)
84#define INT2_DBCHG_MASK (0x1 << 3)
85#define INT2_VBVOLT_MASK (0x1 << 4)
86
87#define INT3_EOC_MASK (0x1 << 0)
88#define INT3_CGMBC_MASK (0x1 << 1)
89#define INT3_OVP_MASK (0x1 << 2)
90#define INT3_MBCCHGERR_MASK (0x1 << 3)
91
92/* MAX14577 DEVICE ID register */
93#define DEVID_VENDORID_SHIFT 0
94#define DEVID_DEVICEID_SHIFT 3
95#define DEVID_VENDORID_MASK (0x07 << DEVID_VENDORID_SHIFT)
96#define DEVID_DEVICEID_MASK (0x1f << DEVID_DEVICEID_SHIFT)
97
98/* MAX14577 STATUS1 register */
99#define STATUS1_ADC_SHIFT 0
100#define STATUS1_ADCLOW_SHIFT 5
101#define STATUS1_ADCERR_SHIFT 6
102#define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
103#define STATUS1_ADCLOW_MASK (0x1 << STATUS1_ADCLOW_SHIFT)
104#define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
105
106/* MAX14577 STATUS2 register */
107#define STATUS2_CHGTYP_SHIFT 0
108#define STATUS2_CHGDETRUN_SHIFT 3
109#define STATUS2_DCDTMR_SHIFT 4
110#define STATUS2_DBCHG_SHIFT 5
111#define STATUS2_VBVOLT_SHIFT 6
112#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
113#define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
114#define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT)
115#define STATUS2_DBCHG_MASK (0x1 << STATUS2_DBCHG_SHIFT)
116#define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
117
118/* MAX14577 CONTROL1 register */
119#define COMN1SW_SHIFT 0
120#define COMP2SW_SHIFT 3
121#define MICEN_SHIFT 6
122#define IDBEN_SHIFT 7
123#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
124#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
125#define MICEN_MASK (0x1 << MICEN_SHIFT)
126#define IDBEN_MASK (0x1 << IDBEN_SHIFT)
127#define CLEAR_IDBEN_MICEN_MASK (COMN1SW_MASK | COMP2SW_MASK)
128#define CTRL1_SW_USB ((1 << COMP2SW_SHIFT) \
129 | (1 << COMN1SW_SHIFT))
130#define CTRL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \
131 | (2 << COMN1SW_SHIFT))
132#define CTRL1_SW_UART ((3 << COMP2SW_SHIFT) \
133 | (3 << COMN1SW_SHIFT))
134#define CTRL1_SW_OPEN ((0 << COMP2SW_SHIFT) \
135 | (0 << COMN1SW_SHIFT))
136
137/* MAX14577 CONTROL2 register */
138#define CTRL2_LOWPWR_SHIFT (0)
139#define CTRL2_ADCEN_SHIFT (1)
140#define CTRL2_CPEN_SHIFT (2)
141#define CTRL2_SFOUTASRT_SHIFT (3)
142#define CTRL2_SFOUTORD_SHIFT (4)
143#define CTRL2_ACCDET_SHIFT (5)
144#define CTRL2_USBCPINT_SHIFT (6)
145#define CTRL2_RCPS_SHIFT (7)
146#define CTRL2_LOWPWR_MASK (0x1 << CTRL2_LOWPWR_SHIFT)
147#define CTRL2_ADCEN_MASK (0x1 << CTRL2_ADCEN_SHIFT)
148#define CTRL2_CPEN_MASK (0x1 << CTRL2_CPEN_SHIFT)
149#define CTRL2_SFOUTASRT_MASK (0x1 << CTRL2_SFOUTASRT_SHIFT)
150#define CTRL2_SFOUTORD_MASK (0x1 << CTRL2_SFOUTORD_SHIFT)
151#define CTRL2_ACCDET_MASK (0x1 << CTRL2_ACCDET_SHIFT)
152#define CTRL2_USBCPINT_MASK (0x1 << CTRL2_USBCPINT_SHIFT)
153#define CTRL2_RCPS_MASK (0x1 << CTR2_RCPS_SHIFT)
154
155#define CTRL2_CPEN1_LOWPWR0 ((1 << CTRL2_CPEN_SHIFT) | \
156 (0 << CTRL2_LOWPWR_SHIFT))
157#define CTRL2_CPEN0_LOWPWR1 ((0 << CTRL2_CPEN_SHIFT) | \
158 (1 << CTRL2_LOWPWR_SHIFT))
159
160/* MAX14577 CONTROL3 register */
161#define CTRL3_JIGSET_SHIFT 0
162#define CTRL3_BOOTSET_SHIFT 2
163#define CTRL3_ADCDBSET_SHIFT 4
164#define CTRL3_JIGSET_MASK (0x3 << CTRL3_JIGSET_SHIFT)
165#define CTRL3_BOOTSET_MASK (0x3 << CTRL3_BOOTSET_SHIFT)
166#define CTRL3_ADCDBSET_MASK (0x3 << CTRL3_ADCDBSET_SHIFT)
167
168/* Slave addr = 0x4A: Charger */
169enum max14577_charger_reg {
170 MAX14577_CHG_REG_STATUS3 = 0x06,
171 MAX14577_CHG_REG_CHG_CTRL1 = 0x0F,
172 MAX14577_CHG_REG_CHG_CTRL2 = 0x10,
173 MAX14577_CHG_REG_CHG_CTRL3 = 0x11,
174 MAX14577_CHG_REG_CHG_CTRL4 = 0x12,
175 MAX14577_CHG_REG_CHG_CTRL5 = 0x13,
176 MAX14577_CHG_REG_CHG_CTRL6 = 0x14,
177 MAX14577_CHG_REG_CHG_CTRL7 = 0x15,
178
179 MAX14577_CHG_REG_END,
180};
181
182/* MAX14577 STATUS3 register */
183#define STATUS3_EOC_SHIFT 0
184#define STATUS3_CGMBC_SHIFT 1
185#define STATUS3_OVP_SHIFT 2
186#define STATUS3_MBCCHGERR_SHIFT 3
187#define STATUS3_EOC_MASK (0x1 << STATUS3_EOC_SHIFT)
188#define STATUS3_CGMBC_MASK (0x1 << STATUS3_CGMBC_SHIFT)
189#define STATUS3_OVP_MASK (0x1 << STATUS3_OVP_SHIFT)
190#define STATUS3_MBCCHGERR_MASK (0x1 << STATUS3_MBCCHGERR_SHIFT)
191
192/* MAX14577 CDETCTRL1 register */
193#define CDETCTRL1_CHGDETEN_SHIFT 0
194#define CDETCTRL1_CHGTYPMAN_SHIFT 1
195#define CDETCTRL1_DCDEN_SHIFT 2
196#define CDETCTRL1_DCD2SCT_SHIFT 3
197#define CDETCTRL1_DCHKTM_SHIFT 4
198#define CDETCTRL1_DBEXIT_SHIFT 5
199#define CDETCTRL1_DBIDLE_SHIFT 6
200#define CDETCTRL1_CDPDET_SHIFT 7
201#define CDETCTRL1_CHGDETEN_MASK (0x1 << CDETCTRL1_CHGDETEN_SHIFT)
202#define CDETCTRL1_CHGTYPMAN_MASK (0x1 << CDETCTRL1_CHGTYPMAN_SHIFT)
203#define CDETCTRL1_DCDEN_MASK (0x1 << CDETCTRL1_DCDEN_SHIFT)
204#define CDETCTRL1_DCD2SCT_MASK (0x1 << CDETCTRL1_DCD2SCT_SHIFT)
205#define CDETCTRL1_DCHKTM_MASK (0x1 << CDETCTRL1_DCHKTM_SHIFT)
206#define CDETCTRL1_DBEXIT_MASK (0x1 << CDETCTRL1_DBEXIT_SHIFT)
207#define CDETCTRL1_DBIDLE_MASK (0x1 << CDETCTRL1_DBIDLE_SHIFT)
208#define CDETCTRL1_CDPDET_MASK (0x1 << CDETCTRL1_CDPDET_SHIFT)
209
210/* MAX14577 CHGCTRL1 register */
211#define CHGCTRL1_TCHW_SHIFT 4
212#define CHGCTRL1_TCHW_MASK (0x7 << CHGCTRL1_TCHW_SHIFT)
213
214/* MAX14577 CHGCTRL2 register */
215#define CHGCTRL2_MBCHOSTEN_SHIFT 6
216#define CHGCTRL2_MBCHOSTEN_MASK (0x1 << CHGCTRL2_MBCHOSTEN_SHIFT)
217#define CHGCTRL2_VCHGR_RC_SHIFT 7
218#define CHGCTRL2_VCHGR_RC_MASK (0x1 << CHGCTRL2_VCHGR_RC_SHIFT)
219
220/* MAX14577 CHGCTRL3 register */
221#define CHGCTRL3_MBCCVWRC_SHIFT 0
222#define CHGCTRL3_MBCCVWRC_MASK (0xf << CHGCTRL3_MBCCVWRC_SHIFT)
223
224/* MAX14577 CHGCTRL4 register */
225#define CHGCTRL4_MBCICHWRCH_SHIFT 0
226#define CHGCTRL4_MBCICHWRCH_MASK (0xf << CHGCTRL4_MBCICHWRCH_SHIFT)
227#define CHGCTRL4_MBCICHWRCL_SHIFT 4
228#define CHGCTRL4_MBCICHWRCL_MASK (0x1 << CHGCTRL4_MBCICHWRCL_SHIFT)
229
230/* MAX14577 CHGCTRL5 register */
231#define CHGCTRL5_EOCS_SHIFT 0
232#define CHGCTRL5_EOCS_MASK (0xf << CHGCTRL5_EOCS_SHIFT)
233
234/* MAX14577 CHGCTRL6 register */
235#define CHGCTRL6_AUTOSTOP_SHIFT 5
236#define CHGCTRL6_AUTOSTOP_MASK (0x1 << CHGCTRL6_AUTOSTOP_SHIFT)
237
238/* MAX14577 CHGCTRL7 register */
239#define CHGCTRL7_OTPCGHCVS_SHIFT 0
240#define CHGCTRL7_OTPCGHCVS_MASK (0x3 << CHGCTRL7_OTPCGHCVS_SHIFT)
241
242/* MAX14577 regulator current limits (as in CHGCTRL4 register), uA */
243#define MAX14577_REGULATOR_CURRENT_LIMIT_MIN 90000
244#define MAX14577_REGULATOR_CURRENT_LIMIT_HIGH_START 200000
245#define MAX14577_REGULATOR_CURRENT_LIMIT_HIGH_STEP 50000
246#define MAX14577_REGULATOR_CURRENT_LIMIT_MAX 950000
247
248/* MAX14577 regulator SFOUT LDO voltage, fixed, uV */
249#define MAX14577_REGULATOR_SAFEOUT_VOLTAGE 4900000
250
251enum max14577_irq_source {
252 MAX14577_IRQ_INT1 = 0,
253 MAX14577_IRQ_INT2,
254 MAX14577_IRQ_INT3,
255
256 MAX14577_IRQ_REGS_NUM,
257};
258
259enum max14577_irq {
260 /* INT1 */
261 MAX14577_IRQ_INT1_ADC,
262 MAX14577_IRQ_INT1_ADCLOW,
263 MAX14577_IRQ_INT1_ADCERR,
264
265 /* INT2 */
266 MAX14577_IRQ_INT2_CHGTYP,
267 MAX14577_IRQ_INT2_CHGDETRUN,
268 MAX14577_IRQ_INT2_DCDTMR,
269 MAX14577_IRQ_INT2_DBCHG,
270 MAX14577_IRQ_INT2_VBVOLT,
271
272 /* INT3 */
273 MAX14577_IRQ_INT3_EOC,
274 MAX14577_IRQ_INT3_CGMBC,
275 MAX14577_IRQ_INT3_OVP,
276 MAX14577_IRQ_INT3_MBCCHGERR,
277
278 MAX14577_IRQ_NUM,
279};
280
281struct max14577 {
282 struct device *dev;
283 struct i2c_client *i2c; /* Slave addr = 0x4A */
284
285 struct regmap *regmap;
286
287 struct regmap_irq_chip_data *irq_data;
288 int irq;
289
290 /* Device ID */
291 u8 vendor_id; /* Vendor Identification */
292 u8 device_id; /* Chip Version */
293};
294
295/* MAX14577 shared regmap API function */
296static inline int max14577_read_reg(struct regmap *map, u8 reg, u8 *dest)
297{
298 unsigned int val;
299 int ret;
300
301 ret = regmap_read(map, reg, &val);
302 *dest = val;
303
304 return ret;
305}
306
307static inline int max14577_bulk_read(struct regmap *map, u8 reg, u8 *buf,
308 int count)
309{
310 return regmap_bulk_read(map, reg, buf, count);
311}
312
313static inline int max14577_write_reg(struct regmap *map, u8 reg, u8 value)
314{
315 return regmap_write(map, reg, value);
316}
317
318static inline int max14577_bulk_write(struct regmap *map, u8 reg, u8 *buf,
319 int count)
320{
321 return regmap_bulk_write(map, reg, buf, count);
322}
323
324static inline int max14577_update_reg(struct regmap *map, u8 reg, u8 mask,
325 u8 val)
326{
327 return regmap_update_bits(map, reg, mask, val);
328}
329
330#endif /* __MAX14577_PRIVATE_H__ */