tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1* Rockchip Pinmux Controller
2
3The Rockchip Pinmux Controller, enables the IC
4to share one PAD to several functional blocks. The sharing is done by
5multiplexing the PAD input/output signals. For each PAD there are up to
64 muxing options with option 0 being the use as a GPIO.
7
8Please refer to pinctrl-bindings.txt in this directory for details of the
9common pinctrl bindings used by client devices, including the meaning of the
10phrase "pin configuration node".
11
12The Rockchip pin configuration node is a node of a group of pins which can be
13used for a specific device or function. This node represents both mux and
14config of the pins in that group. The 'pins' selects the function mode(also
15named pin mode) this pin can work on and the 'config' configures various pad
16settings such as pull-up, etc.
17
18The pins are grouped into up to 5 individual pin banks which need to be
19defined as gpio sub-nodes of the pinmux controller.
20
21Required properties for iomux controller:
22 - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
23 "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
24 - reg: first element is the general register space of the iomux controller
25 second element is the separate pull register space of the rk3188
26
27Required properties for gpio sub nodes:
28 - compatible: "rockchip,gpio-bank", "rockchip,rk3188-gpio-bank0"
29 - reg: register of the gpio bank (different than the iomux registerset)
30 second element: separate pull register for rk3188 bank0
31 - interrupts: base interrupt of the gpio bank in the interrupt controller
32 - clocks: clock that drives this bank
33 - gpio-controller: identifies the node as a gpio controller and pin bank.
34 - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
35 binding is used, the amount of cells must be specified as 2. See generic
36 GPIO binding documentation for description of particular cells.
37 - interrupt-controller: identifies the controller node as interrupt-parent.
38 - #interrupt-cells: the value of this property should be 2 and the interrupt
39 cells should use the standard two-cell scheme described in
40 bindings/interrupt-controller/interrupts.txt
41
42Required properties for pin configuration node:
43 - rockchip,pins: 3 integers array, represents a group of pins mux and config
44 setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
45 The MUX 0 means gpio and MUX 1 to 3 mean the specific device function.
46 The phandle of a node containing the generic pinconfig options
47 to use, as described in pinctrl-bindings.txt in this directory.
48
49Examples:
50
51#include <dt-bindings/pinctrl/rockchip.h>
52
53...
54
55pinctrl@20008000 {
56 compatible = "rockchip,rk3066a-pinctrl";
57 reg = <0x20008000 0x150>;
58 #address-cells = <1>;
59 #size-cells = <1>;
60 ranges;
61
62 gpio0: gpio0@20034000 {
63 compatible = "rockchip,gpio-bank";
64 reg = <0x20034000 0x100>;
65 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
66 clocks = <&clk_gates8 9>;
67
68 gpio-controller;
69 #gpio-cells = <2>;
70
71 interrupt-controller;
72 #interrupt-cells = <2>;
73 };
74
75 ...
76
77 pcfg_pull_default: pcfg_pull_default {
78 bias-pull-pin-default
79 };
80
81 uart2 {
82 uart2_xfer: uart2-xfer {
83 rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>,
84 <RK_GPIO1 9 1 &pcfg_pull_default>;
85 };
86 };
87};
88
89uart2: serial@20064000 {
90 compatible = "snps,dw-apb-uart";
91 reg = <0x20064000 0x400>;
92 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
93 reg-shift = <2>;
94 reg-io-width = <1>;
95 clocks = <&mux_uart2>;
96 status = "okay";
97
98 pinctrl-names = "default";
99 pinctrl-0 = <&uart2_xfer>;
100};
101
102Example for rk3188:
103
104 pinctrl@20008000 {
105 compatible = "rockchip,rk3188-pinctrl";
106 reg = <0x20008000 0xa0>,
107 <0x20008164 0x1a0>;
108 #address-cells = <1>;
109 #size-cells = <1>;
110 ranges;
111
112 gpio0: gpio0@0x2000a000 {
113 compatible = "rockchip,rk3188-gpio-bank0";
114 reg = <0x2000a000 0x100>,
115 <0x20004064 0x8>;
116 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
117 clocks = <&clk_gates8 9>;
118
119 gpio-controller;
120 #gpio-cells = <2>;
121
122 interrupt-controller;
123 #interrupt-cells = <2>;
124 };
125
126 gpio1: gpio1@0x2003c000 {
127 compatible = "rockchip,gpio-bank";
128 reg = <0x2003c000 0x100>;
129 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
130 clocks = <&clk_gates8 10>;
131
132 gpio-controller;
133 #gpio-cells = <2>;
134
135 interrupt-controller;
136 #interrupt-cells = <2>;
137 };
138
139 ...
140
141 };