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Linux kernel mirror (for testing)
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kernel
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linux
1/*
2 * include/asm-sh/cpu-sh4/mmu_context.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_MMU_CONTEXT_H
11#define __ASM_CPU_SH4_MMU_CONTEXT_H
12
13#define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */
14#define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
15#define MMU_TTB 0xFF000008 /* Translation table base register */
16#define MMU_TEA 0xFF00000C /* TLB Exception Address */
17#define MMU_PTEA 0xFF000034 /* PTE assistance register */
18#define MMU_PTEAEX 0xFF00007C /* PTE ASID extension register */
19
20#define MMUCR 0xFF000010 /* MMU Control Register */
21
22#define MMU_TLB_ENTRY_SHIFT 8
23
24#define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
25#define MMU_ITLB_ADDRESS_ARRAY2 0xF2800000
26#define MMU_ITLB_DATA_ARRAY 0xF3000000
27#define MMU_ITLB_DATA_ARRAY2 0xF3800000
28
29#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000
30#define MMU_UTLB_ADDRESS_ARRAY2 0xF6800000
31#define MMU_UTLB_DATA_ARRAY 0xF7000000
32#define MMU_UTLB_DATA_ARRAY2 0xF7800000
33#define MMU_PAGE_ASSOC_BIT 0x80
34
35#ifdef CONFIG_MMU
36#define MMUCR_AT (1 << 0)
37#else
38#define MMUCR_AT (0)
39#endif
40
41#define MMUCR_TI (1 << 2)
42
43#define MMUCR_URB 0x00FC0000
44#define MMUCR_URB_SHIFT 18
45#define MMUCR_URB_NENTRIES 64
46#define MMUCR_URC 0x0000FC00
47#define MMUCR_URC_SHIFT 10
48
49#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40)
50#define MMUCR_SE (1 << 4)
51#else
52#define MMUCR_SE (0)
53#endif
54
55#ifdef CONFIG_CPU_HAS_PTEAEX
56#define MMUCR_AEX (1 << 6)
57#else
58#define MMUCR_AEX (0)
59#endif
60
61#ifdef CONFIG_X2TLB
62#define MMUCR_ME (1 << 7)
63#else
64#define MMUCR_ME (0)
65#endif
66
67#ifdef CONFIG_SH_STORE_QUEUES
68#define MMUCR_SQMD (1 << 9)
69#else
70#define MMUCR_SQMD (0)
71#endif
72
73#define MMU_NTLB_ENTRIES 64
74#define MMU_CONTROL_INIT (MMUCR_AT | MMUCR_TI | MMUCR_SQMD | \
75 MMUCR_ME | MMUCR_SE | MMUCR_AEX)
76
77#define TRA 0xff000020
78#define EXPEVT 0xff000024
79#define INTEVT 0xff000028
80
81#endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */
82