Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DRIVER_H
34#define MLX5_DRIVER_H
35
36#include <linux/kernel.h>
37#include <linux/completion.h>
38#include <linux/pci.h>
39#include <linux/spinlock_types.h>
40#include <linux/semaphore.h>
41#include <linux/vmalloc.h>
42#include <linux/radix-tree.h>
43#include <linux/mlx5/device.h>
44#include <linux/mlx5/doorbell.h>
45
46enum {
47 MLX5_BOARD_ID_LEN = 64,
48 MLX5_MAX_NAME_LEN = 16,
49};
50
51enum {
52 /* one minute for the sake of bringup. Generally, commands must always
53 * complete and we may need to increase this timeout value
54 */
55 MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000,
56 MLX5_CMD_WQ_MAX_NAME = 32,
57};
58
59enum {
60 CMD_OWNER_SW = 0x0,
61 CMD_OWNER_HW = 0x1,
62 CMD_STATUS_SUCCESS = 0,
63};
64
65enum mlx5_sqp_t {
66 MLX5_SQP_SMI = 0,
67 MLX5_SQP_GSI = 1,
68 MLX5_SQP_IEEE_1588 = 2,
69 MLX5_SQP_SNIFFER = 3,
70 MLX5_SQP_SYNC_UMR = 4,
71};
72
73enum {
74 MLX5_MAX_PORTS = 2,
75};
76
77enum {
78 MLX5_EQ_VEC_PAGES = 0,
79 MLX5_EQ_VEC_CMD = 1,
80 MLX5_EQ_VEC_ASYNC = 2,
81 MLX5_EQ_VEC_COMP_BASE,
82};
83
84enum {
85 MLX5_MAX_EQ_NAME = 32
86};
87
88enum {
89 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
90 MLX5_ATOMIC_MODE_CX = 2 << 16,
91 MLX5_ATOMIC_MODE_8B = 3 << 16,
92 MLX5_ATOMIC_MODE_16B = 4 << 16,
93 MLX5_ATOMIC_MODE_32B = 5 << 16,
94 MLX5_ATOMIC_MODE_64B = 6 << 16,
95 MLX5_ATOMIC_MODE_128B = 7 << 16,
96 MLX5_ATOMIC_MODE_256B = 8 << 16,
97};
98
99enum {
100 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
101 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
102 MLX5_CMD_OP_INIT_HCA = 0x102,
103 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
104 MLX5_CMD_OP_ENABLE_HCA = 0x104,
105 MLX5_CMD_OP_DISABLE_HCA = 0x105,
106 MLX5_CMD_OP_QUERY_PAGES = 0x107,
107 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
108 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
109
110 MLX5_CMD_OP_CREATE_MKEY = 0x200,
111 MLX5_CMD_OP_QUERY_MKEY = 0x201,
112 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
113 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
114
115 MLX5_CMD_OP_CREATE_EQ = 0x301,
116 MLX5_CMD_OP_DESTROY_EQ = 0x302,
117 MLX5_CMD_OP_QUERY_EQ = 0x303,
118
119 MLX5_CMD_OP_CREATE_CQ = 0x400,
120 MLX5_CMD_OP_DESTROY_CQ = 0x401,
121 MLX5_CMD_OP_QUERY_CQ = 0x402,
122 MLX5_CMD_OP_MODIFY_CQ = 0x403,
123
124 MLX5_CMD_OP_CREATE_QP = 0x500,
125 MLX5_CMD_OP_DESTROY_QP = 0x501,
126 MLX5_CMD_OP_RST2INIT_QP = 0x502,
127 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
128 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
129 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
130 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
131 MLX5_CMD_OP_2ERR_QP = 0x507,
132 MLX5_CMD_OP_RTS2SQD_QP = 0x508,
133 MLX5_CMD_OP_SQD2RTS_QP = 0x509,
134 MLX5_CMD_OP_2RST_QP = 0x50a,
135 MLX5_CMD_OP_QUERY_QP = 0x50b,
136 MLX5_CMD_OP_CONF_SQP = 0x50c,
137 MLX5_CMD_OP_MAD_IFC = 0x50d,
138 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
139 MLX5_CMD_OP_SUSPEND_QP = 0x50f,
140 MLX5_CMD_OP_UNSUSPEND_QP = 0x510,
141 MLX5_CMD_OP_SQD2SQD_QP = 0x511,
142 MLX5_CMD_OP_ALLOC_QP_COUNTER_SET = 0x512,
143 MLX5_CMD_OP_DEALLOC_QP_COUNTER_SET = 0x513,
144 MLX5_CMD_OP_QUERY_QP_COUNTER_SET = 0x514,
145
146 MLX5_CMD_OP_CREATE_PSV = 0x600,
147 MLX5_CMD_OP_DESTROY_PSV = 0x601,
148 MLX5_CMD_OP_QUERY_PSV = 0x602,
149 MLX5_CMD_OP_QUERY_SIG_RULE_TABLE = 0x603,
150 MLX5_CMD_OP_QUERY_BLOCK_SIZE_TABLE = 0x604,
151
152 MLX5_CMD_OP_CREATE_SRQ = 0x700,
153 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
154 MLX5_CMD_OP_QUERY_SRQ = 0x702,
155 MLX5_CMD_OP_ARM_RQ = 0x703,
156 MLX5_CMD_OP_RESIZE_SRQ = 0x704,
157
158 MLX5_CMD_OP_ALLOC_PD = 0x800,
159 MLX5_CMD_OP_DEALLOC_PD = 0x801,
160 MLX5_CMD_OP_ALLOC_UAR = 0x802,
161 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
162
163 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
164 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
165
166
167 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
168 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
169
170 MLX5_CMD_OP_ACCESS_REG = 0x805,
171 MLX5_CMD_OP_MAX = 0x810,
172};
173
174enum {
175 MLX5_REG_PCAP = 0x5001,
176 MLX5_REG_PMTU = 0x5003,
177 MLX5_REG_PTYS = 0x5004,
178 MLX5_REG_PAOS = 0x5006,
179 MLX5_REG_PMAOS = 0x5012,
180 MLX5_REG_PUDE = 0x5009,
181 MLX5_REG_PMPE = 0x5010,
182 MLX5_REG_PELC = 0x500e,
183 MLX5_REG_PMLP = 0, /* TBD */
184 MLX5_REG_NODE_DESC = 0x6001,
185 MLX5_REG_HOST_ENDIANNESS = 0x7004,
186};
187
188enum dbg_rsc_type {
189 MLX5_DBG_RSC_QP,
190 MLX5_DBG_RSC_EQ,
191 MLX5_DBG_RSC_CQ,
192};
193
194struct mlx5_field_desc {
195 struct dentry *dent;
196 int i;
197};
198
199struct mlx5_rsc_debug {
200 struct mlx5_core_dev *dev;
201 void *object;
202 enum dbg_rsc_type type;
203 struct dentry *root;
204 struct mlx5_field_desc fields[0];
205};
206
207enum mlx5_dev_event {
208 MLX5_DEV_EVENT_SYS_ERROR,
209 MLX5_DEV_EVENT_PORT_UP,
210 MLX5_DEV_EVENT_PORT_DOWN,
211 MLX5_DEV_EVENT_PORT_INITIALIZED,
212 MLX5_DEV_EVENT_LID_CHANGE,
213 MLX5_DEV_EVENT_PKEY_CHANGE,
214 MLX5_DEV_EVENT_GUID_CHANGE,
215 MLX5_DEV_EVENT_CLIENT_REREG,
216};
217
218struct mlx5_uuar_info {
219 struct mlx5_uar *uars;
220 int num_uars;
221 int num_low_latency_uuars;
222 unsigned long *bitmap;
223 unsigned int *count;
224 struct mlx5_bf *bfs;
225
226 /*
227 * protect uuar allocation data structs
228 */
229 struct mutex lock;
230};
231
232struct mlx5_bf {
233 void __iomem *reg;
234 void __iomem *regreg;
235 int buf_size;
236 struct mlx5_uar *uar;
237 unsigned long offset;
238 int need_lock;
239 /* protect blue flame buffer selection when needed
240 */
241 spinlock_t lock;
242
243 /* serialize 64 bit writes when done as two 32 bit accesses
244 */
245 spinlock_t lock32;
246 int uuarn;
247};
248
249struct mlx5_cmd_first {
250 __be32 data[4];
251};
252
253struct mlx5_cmd_msg {
254 struct list_head list;
255 struct cache_ent *cache;
256 u32 len;
257 struct mlx5_cmd_first first;
258 struct mlx5_cmd_mailbox *next;
259};
260
261struct mlx5_cmd_debug {
262 struct dentry *dbg_root;
263 struct dentry *dbg_in;
264 struct dentry *dbg_out;
265 struct dentry *dbg_outlen;
266 struct dentry *dbg_status;
267 struct dentry *dbg_run;
268 void *in_msg;
269 void *out_msg;
270 u8 status;
271 u16 inlen;
272 u16 outlen;
273};
274
275struct cache_ent {
276 /* protect block chain allocations
277 */
278 spinlock_t lock;
279 struct list_head head;
280};
281
282struct cmd_msg_cache {
283 struct cache_ent large;
284 struct cache_ent med;
285
286};
287
288struct mlx5_cmd_stats {
289 u64 sum;
290 u64 n;
291 struct dentry *root;
292 struct dentry *avg;
293 struct dentry *count;
294 /* protect command average calculations */
295 spinlock_t lock;
296};
297
298struct mlx5_cmd {
299 void *cmd_buf;
300 dma_addr_t dma;
301 u16 cmdif_rev;
302 u8 log_sz;
303 u8 log_stride;
304 int max_reg_cmds;
305 int events;
306 u32 __iomem *vector;
307
308 /* protect command queue allocations
309 */
310 spinlock_t alloc_lock;
311
312 /* protect token allocations
313 */
314 spinlock_t token_lock;
315 u8 token;
316 unsigned long bitmask;
317 char wq_name[MLX5_CMD_WQ_MAX_NAME];
318 struct workqueue_struct *wq;
319 struct semaphore sem;
320 struct semaphore pages_sem;
321 int mode;
322 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
323 struct pci_pool *pool;
324 struct mlx5_cmd_debug dbg;
325 struct cmd_msg_cache cache;
326 int checksum_disabled;
327 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
328};
329
330struct mlx5_port_caps {
331 int gid_table_len;
332 int pkey_table_len;
333};
334
335struct mlx5_caps {
336 u8 log_max_eq;
337 u8 log_max_cq;
338 u8 log_max_qp;
339 u8 log_max_mkey;
340 u8 log_max_pd;
341 u8 log_max_srq;
342 u32 max_cqes;
343 int max_wqes;
344 int max_sq_desc_sz;
345 int max_rq_desc_sz;
346 u64 flags;
347 u16 stat_rate_support;
348 int log_max_msg;
349 int num_ports;
350 int max_ra_res_qp;
351 int max_ra_req_qp;
352 int max_srq_wqes;
353 int bf_reg_size;
354 int bf_regs_per_page;
355 struct mlx5_port_caps port[MLX5_MAX_PORTS];
356 u8 ext_port_cap[MLX5_MAX_PORTS];
357 int max_vf;
358 u32 reserved_lkey;
359 u8 local_ca_ack_delay;
360 u8 log_max_mcg;
361 u32 max_qp_mcg;
362 int min_page_sz;
363};
364
365struct mlx5_cmd_mailbox {
366 void *buf;
367 dma_addr_t dma;
368 struct mlx5_cmd_mailbox *next;
369};
370
371struct mlx5_buf_list {
372 void *buf;
373 dma_addr_t map;
374};
375
376struct mlx5_buf {
377 struct mlx5_buf_list direct;
378 struct mlx5_buf_list *page_list;
379 int nbufs;
380 int npages;
381 int page_shift;
382 int size;
383};
384
385struct mlx5_eq {
386 struct mlx5_core_dev *dev;
387 __be32 __iomem *doorbell;
388 u32 cons_index;
389 struct mlx5_buf buf;
390 int size;
391 u8 irqn;
392 u8 eqn;
393 int nent;
394 u64 mask;
395 char name[MLX5_MAX_EQ_NAME];
396 struct list_head list;
397 int index;
398 struct mlx5_rsc_debug *dbg;
399};
400
401
402struct mlx5_core_mr {
403 u64 iova;
404 u64 size;
405 u32 key;
406 u32 pd;
407 u32 access;
408};
409
410struct mlx5_core_srq {
411 u32 srqn;
412 int max;
413 int max_gs;
414 int max_avail_gather;
415 int wqe_shift;
416 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
417
418 atomic_t refcount;
419 struct completion free;
420};
421
422struct mlx5_eq_table {
423 void __iomem *update_ci;
424 void __iomem *update_arm_ci;
425 struct list_head *comp_eq_head;
426 struct mlx5_eq pages_eq;
427 struct mlx5_eq async_eq;
428 struct mlx5_eq cmd_eq;
429 struct msix_entry *msix_arr;
430 int num_comp_vectors;
431 /* protect EQs list
432 */
433 spinlock_t lock;
434};
435
436struct mlx5_uar {
437 u32 index;
438 struct list_head bf_list;
439 unsigned free_bf_bmap;
440 void __iomem *wc_map;
441 void __iomem *map;
442};
443
444
445struct mlx5_core_health {
446 struct health_buffer __iomem *health;
447 __be32 __iomem *health_counter;
448 struct timer_list timer;
449 struct list_head list;
450 u32 prev;
451 int miss_counter;
452};
453
454struct mlx5_cq_table {
455 /* protect radix tree
456 */
457 spinlock_t lock;
458 struct radix_tree_root tree;
459};
460
461struct mlx5_qp_table {
462 /* protect radix tree
463 */
464 spinlock_t lock;
465 struct radix_tree_root tree;
466};
467
468struct mlx5_srq_table {
469 /* protect radix tree
470 */
471 spinlock_t lock;
472 struct radix_tree_root tree;
473};
474
475struct mlx5_priv {
476 char name[MLX5_MAX_NAME_LEN];
477 struct mlx5_eq_table eq_table;
478 struct mlx5_uuar_info uuari;
479 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
480
481 /* pages stuff */
482 struct workqueue_struct *pg_wq;
483 struct rb_root page_root;
484 int fw_pages;
485 int reg_pages;
486 struct list_head free_list;
487
488 struct mlx5_core_health health;
489
490 struct mlx5_srq_table srq_table;
491
492 /* start: qp staff */
493 struct mlx5_qp_table qp_table;
494 struct dentry *qp_debugfs;
495 struct dentry *eq_debugfs;
496 struct dentry *cq_debugfs;
497 struct dentry *cmdif_debugfs;
498 /* end: qp staff */
499
500 /* start: cq staff */
501 struct mlx5_cq_table cq_table;
502 /* end: cq staff */
503
504 /* start: alloc staff */
505 struct mutex pgdir_mutex;
506 struct list_head pgdir_list;
507 /* end: alloc staff */
508 struct dentry *dbg_root;
509
510 /* protect mkey key part */
511 spinlock_t mkey_lock;
512 u8 mkey_key;
513};
514
515struct mlx5_core_dev {
516 struct pci_dev *pdev;
517 u8 rev_id;
518 char board_id[MLX5_BOARD_ID_LEN];
519 struct mlx5_cmd cmd;
520 struct mlx5_caps caps;
521 phys_addr_t iseg_base;
522 struct mlx5_init_seg __iomem *iseg;
523 void (*event) (struct mlx5_core_dev *dev,
524 enum mlx5_dev_event event,
525 void *data);
526 struct mlx5_priv priv;
527 struct mlx5_profile *profile;
528 atomic_t num_qps;
529};
530
531struct mlx5_db {
532 __be32 *db;
533 union {
534 struct mlx5_db_pgdir *pgdir;
535 struct mlx5_ib_user_db_page *user_page;
536 } u;
537 dma_addr_t dma;
538 int index;
539};
540
541enum {
542 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES,
543};
544
545enum {
546 MLX5_COMP_EQ_SIZE = 1024,
547};
548
549struct mlx5_db_pgdir {
550 struct list_head list;
551 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
552 __be32 *db_page;
553 dma_addr_t db_dma;
554};
555
556typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
557
558struct mlx5_cmd_work_ent {
559 struct mlx5_cmd_msg *in;
560 struct mlx5_cmd_msg *out;
561 void *uout;
562 int uout_size;
563 mlx5_cmd_cbk_t callback;
564 void *context;
565 int idx;
566 struct completion done;
567 struct mlx5_cmd *cmd;
568 struct work_struct work;
569 struct mlx5_cmd_layout *lay;
570 int ret;
571 int page_queue;
572 u8 status;
573 u8 token;
574 struct timespec ts1;
575 struct timespec ts2;
576 u16 op;
577};
578
579struct mlx5_pas {
580 u64 pa;
581 u8 log_sz;
582};
583
584static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
585{
586 if (likely(BITS_PER_LONG == 64 || buf->nbufs == 1))
587 return buf->direct.buf + offset;
588 else
589 return buf->page_list[offset >> PAGE_SHIFT].buf +
590 (offset & (PAGE_SIZE - 1));
591}
592
593extern struct workqueue_struct *mlx5_core_wq;
594
595#define STRUCT_FIELD(header, field) \
596 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
597 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
598
599struct ib_field {
600 size_t struct_offset_bytes;
601 size_t struct_size_bytes;
602 int offset_bits;
603 int size_bits;
604};
605
606static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
607{
608 return pci_get_drvdata(pdev);
609}
610
611extern struct dentry *mlx5_debugfs_root;
612
613static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
614{
615 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
616}
617
618static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
619{
620 return ioread32be(&dev->iseg->fw_rev) >> 16;
621}
622
623static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
624{
625 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
626}
627
628static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
629{
630 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
631}
632
633static inline void *mlx5_vzalloc(unsigned long size)
634{
635 void *rtn;
636
637 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
638 if (!rtn)
639 rtn = vzalloc(size);
640 return rtn;
641}
642
643static inline void mlx5_vfree(const void *addr)
644{
645 if (addr && is_vmalloc_addr(addr))
646 vfree(addr);
647 else
648 kfree(addr);
649}
650
651int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev);
652void mlx5_dev_cleanup(struct mlx5_core_dev *dev);
653int mlx5_cmd_init(struct mlx5_core_dev *dev);
654void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
655void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
656void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
657int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
658int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
659 int out_size);
660int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
661 void *out, int out_size, mlx5_cmd_cbk_t callback,
662 void *context);
663int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
664int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
665int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
666int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
667void mlx5_health_cleanup(void);
668void __init mlx5_health_init(void);
669void mlx5_start_health_poll(struct mlx5_core_dev *dev);
670void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
671int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct,
672 struct mlx5_buf *buf);
673void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
674struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
675 gfp_t flags, int npages);
676void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
677 struct mlx5_cmd_mailbox *head);
678int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
679 struct mlx5_create_srq_mbox_in *in, int inlen);
680int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
681int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
682 struct mlx5_query_srq_mbox_out *out);
683int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
684 u16 lwm, int is_srq);
685int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
686 struct mlx5_create_mkey_mbox_in *in, int inlen,
687 mlx5_cmd_cbk_t callback, void *context,
688 struct mlx5_create_mkey_mbox_out *out);
689int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr);
690int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
691 struct mlx5_query_mkey_mbox_out *out, int outlen);
692int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
693 u32 *mkey);
694int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
695int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
696int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, void *inb, void *outb,
697 u16 opmod, int port);
698void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
699void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
700int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
701void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
702void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
703 s32 npages);
704int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
705int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
706void mlx5_register_debugfs(void);
707void mlx5_unregister_debugfs(void);
708int mlx5_eq_init(struct mlx5_core_dev *dev);
709void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
710void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
711void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
712void mlx5_qp_event(struct mlx5_core_dev *dev, u32 qpn, int event_type);
713void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
714struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
715void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector);
716void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
717int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
718 int nent, u64 mask, const char *name, struct mlx5_uar *uar);
719int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
720int mlx5_start_eqs(struct mlx5_core_dev *dev);
721int mlx5_stop_eqs(struct mlx5_core_dev *dev);
722int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
723int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
724
725int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
726void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
727int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
728 int size_in, void *data_out, int size_out,
729 u16 reg_num, int arg, int write);
730int mlx5_set_port_caps(struct mlx5_core_dev *dev, int port_num, u32 caps);
731
732int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
733void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
734int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
735 struct mlx5_query_eq_mbox_out *out, int outlen);
736int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
737void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
738int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
739void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
740int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
741void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
742
743const char *mlx5_command_str(int command);
744int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
745void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
746
747static inline u32 mlx5_mkey_to_idx(u32 mkey)
748{
749 return mkey >> 8;
750}
751
752static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
753{
754 return mkey_idx << 8;
755}
756
757static inline u8 mlx5_mkey_variant(u32 mkey)
758{
759 return mkey & 0xff;
760}
761
762enum {
763 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
764 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
765};
766
767enum {
768 MAX_MR_CACHE_ENTRIES = 16,
769};
770
771struct mlx5_profile {
772 u64 mask;
773 u32 log_max_qp;
774 struct {
775 int size;
776 int limit;
777 } mr_cache[MAX_MR_CACHE_ENTRIES];
778};
779
780#endif /* MLX5_DRIVER_H */