Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
38
39#if defined(__LITTLE_ENDIAN)
40#define MLX5_SET_HOST_ENDIANNESS 0
41#elif defined(__BIG_ENDIAN)
42#define MLX5_SET_HOST_ENDIANNESS 0x80
43#else
44#error Host endianness not defined
45#endif
46
47enum {
48 MLX5_MAX_COMMANDS = 32,
49 MLX5_CMD_DATA_BLOCK_SIZE = 512,
50 MLX5_PCI_CMD_XPORT = 7,
51};
52
53enum {
54 MLX5_EXTENDED_UD_AV = 0x80000000,
55};
56
57enum {
58 MLX5_CQ_STATE_ARMED = 9,
59 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
60 MLX5_CQ_STATE_FIRED = 0xa,
61};
62
63enum {
64 MLX5_STAT_RATE_OFFSET = 5,
65};
66
67enum {
68 MLX5_INLINE_SEG = 0x80000000,
69};
70
71enum {
72 MLX5_PERM_LOCAL_READ = 1 << 2,
73 MLX5_PERM_LOCAL_WRITE = 1 << 3,
74 MLX5_PERM_REMOTE_READ = 1 << 4,
75 MLX5_PERM_REMOTE_WRITE = 1 << 5,
76 MLX5_PERM_ATOMIC = 1 << 6,
77 MLX5_PERM_UMR_EN = 1 << 7,
78};
79
80enum {
81 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
82 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
83 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
84 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
85 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
86};
87
88enum {
89 MLX5_ACCESS_MODE_PA = 0,
90 MLX5_ACCESS_MODE_MTT = 1,
91 MLX5_ACCESS_MODE_KLM = 2
92};
93
94enum {
95 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
96 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
97 MLX5_MKEY_BSF_EN = 1 << 30,
98 MLX5_MKEY_LEN64 = 1 << 31,
99};
100
101enum {
102 MLX5_EN_RD = (u64)1,
103 MLX5_EN_WR = (u64)2
104};
105
106enum {
107 MLX5_BF_REGS_PER_PAGE = 4,
108 MLX5_MAX_UAR_PAGES = 1 << 8,
109 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_BF_REGS_PER_PAGE,
110};
111
112enum {
113 MLX5_MKEY_MASK_LEN = 1ull << 0,
114 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
115 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
116 MLX5_MKEY_MASK_PD = 1ull << 7,
117 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
118 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
119 MLX5_MKEY_MASK_KEY = 1ull << 13,
120 MLX5_MKEY_MASK_QPN = 1ull << 14,
121 MLX5_MKEY_MASK_LR = 1ull << 17,
122 MLX5_MKEY_MASK_LW = 1ull << 18,
123 MLX5_MKEY_MASK_RR = 1ull << 19,
124 MLX5_MKEY_MASK_RW = 1ull << 20,
125 MLX5_MKEY_MASK_A = 1ull << 21,
126 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
127 MLX5_MKEY_MASK_FREE = 1ull << 29,
128};
129
130enum mlx5_event {
131 MLX5_EVENT_TYPE_COMP = 0x0,
132
133 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
134 MLX5_EVENT_TYPE_COMM_EST = 0x02,
135 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
136 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
137 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
138
139 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
140 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
141 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
142 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
143 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
144 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
145
146 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
147 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
148 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
149 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
150
151 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
152 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
153
154 MLX5_EVENT_TYPE_CMD = 0x0a,
155 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
156};
157
158enum {
159 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
160 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
161 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
162 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
163 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
164 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
165 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
166};
167
168enum {
169 MLX5_DEV_CAP_FLAG_RC = 1LL << 0,
170 MLX5_DEV_CAP_FLAG_UC = 1LL << 1,
171 MLX5_DEV_CAP_FLAG_UD = 1LL << 2,
172 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
173 MLX5_DEV_CAP_FLAG_SRQ = 1LL << 6,
174 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
175 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
176 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
177 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
178 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
179 MLX5_DEV_CAP_FLAG_RESIZE_SRQ = 1LL << 32,
180 MLX5_DEV_CAP_FLAG_REMOTE_FENCE = 1LL << 38,
181 MLX5_DEV_CAP_FLAG_TLP_HINTS = 1LL << 39,
182 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
183 MLX5_DEV_CAP_FLAG_DCT = 1LL << 41,
184 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
185};
186
187enum {
188 MLX5_OPCODE_NOP = 0x00,
189 MLX5_OPCODE_SEND_INVAL = 0x01,
190 MLX5_OPCODE_RDMA_WRITE = 0x08,
191 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
192 MLX5_OPCODE_SEND = 0x0a,
193 MLX5_OPCODE_SEND_IMM = 0x0b,
194 MLX5_OPCODE_RDMA_READ = 0x10,
195 MLX5_OPCODE_ATOMIC_CS = 0x11,
196 MLX5_OPCODE_ATOMIC_FA = 0x12,
197 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
198 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
199 MLX5_OPCODE_BIND_MW = 0x18,
200 MLX5_OPCODE_CONFIG_CMD = 0x1f,
201
202 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
203 MLX5_RECV_OPCODE_SEND = 0x01,
204 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
205 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
206
207 MLX5_CQE_OPCODE_ERROR = 0x1e,
208 MLX5_CQE_OPCODE_RESIZE = 0x16,
209
210 MLX5_OPCODE_SET_PSV = 0x20,
211 MLX5_OPCODE_GET_PSV = 0x21,
212 MLX5_OPCODE_CHECK_PSV = 0x22,
213 MLX5_OPCODE_RGET_PSV = 0x26,
214 MLX5_OPCODE_RCHECK_PSV = 0x27,
215
216 MLX5_OPCODE_UMR = 0x25,
217
218};
219
220enum {
221 MLX5_SET_PORT_RESET_QKEY = 0,
222 MLX5_SET_PORT_GUID0 = 16,
223 MLX5_SET_PORT_NODE_GUID = 17,
224 MLX5_SET_PORT_SYS_GUID = 18,
225 MLX5_SET_PORT_GID_TABLE = 19,
226 MLX5_SET_PORT_PKEY_TABLE = 20,
227};
228
229enum {
230 MLX5_MAX_PAGE_SHIFT = 31
231};
232
233enum {
234 MLX5_ADAPTER_PAGE_SHIFT = 12
235};
236
237enum {
238 MLX5_CAP_OFF_DCT = 41,
239 MLX5_CAP_OFF_CMDIF_CSUM = 46,
240};
241
242struct mlx5_inbox_hdr {
243 __be16 opcode;
244 u8 rsvd[4];
245 __be16 opmod;
246};
247
248struct mlx5_outbox_hdr {
249 u8 status;
250 u8 rsvd[3];
251 __be32 syndrome;
252};
253
254struct mlx5_cmd_query_adapter_mbox_in {
255 struct mlx5_inbox_hdr hdr;
256 u8 rsvd[8];
257};
258
259struct mlx5_cmd_query_adapter_mbox_out {
260 struct mlx5_outbox_hdr hdr;
261 u8 rsvd0[24];
262 u8 intapin;
263 u8 rsvd1[13];
264 __be16 vsd_vendor_id;
265 u8 vsd[208];
266 u8 vsd_psid[16];
267};
268
269struct mlx5_hca_cap {
270 u8 rsvd1[16];
271 u8 log_max_srq_sz;
272 u8 log_max_qp_sz;
273 u8 rsvd2;
274 u8 log_max_qp;
275 u8 log_max_strq_sz;
276 u8 log_max_srqs;
277 u8 rsvd4[2];
278 u8 rsvd5;
279 u8 log_max_cq_sz;
280 u8 rsvd6;
281 u8 log_max_cq;
282 u8 log_max_eq_sz;
283 u8 log_max_mkey;
284 u8 rsvd7;
285 u8 log_max_eq;
286 u8 max_indirection;
287 u8 log_max_mrw_sz;
288 u8 log_max_bsf_list_sz;
289 u8 log_max_klm_list_sz;
290 u8 rsvd_8_0;
291 u8 log_max_ra_req_dc;
292 u8 rsvd_8_1;
293 u8 log_max_ra_res_dc;
294 u8 rsvd9;
295 u8 log_max_ra_req_qp;
296 u8 rsvd10;
297 u8 log_max_ra_res_qp;
298 u8 rsvd11[4];
299 __be16 max_qp_count;
300 __be16 rsvd12;
301 u8 rsvd13;
302 u8 local_ca_ack_delay;
303 u8 rsvd14;
304 u8 num_ports;
305 u8 log_max_msg;
306 u8 rsvd15[3];
307 __be16 stat_rate_support;
308 u8 rsvd16[2];
309 __be64 flags;
310 u8 rsvd17;
311 u8 uar_sz;
312 u8 rsvd18;
313 u8 log_pg_sz;
314 __be16 bf_log_bf_reg_size;
315 u8 rsvd19[4];
316 __be16 max_desc_sz_sq;
317 u8 rsvd20[2];
318 __be16 max_desc_sz_rq;
319 u8 rsvd21[2];
320 __be16 max_desc_sz_sq_dc;
321 __be32 max_qp_mcg;
322 u8 rsvd22[3];
323 u8 log_max_mcg;
324 u8 rsvd23;
325 u8 log_max_pd;
326 u8 rsvd24;
327 u8 log_max_xrcd;
328 u8 rsvd25[42];
329 __be16 log_uar_page_sz;
330 u8 rsvd26[28];
331 u8 log_max_atomic_size_qp;
332 u8 rsvd27[2];
333 u8 log_max_atomic_size_dc;
334 u8 rsvd28[76];
335};
336
337
338struct mlx5_cmd_query_hca_cap_mbox_in {
339 struct mlx5_inbox_hdr hdr;
340 u8 rsvd[8];
341};
342
343
344struct mlx5_cmd_query_hca_cap_mbox_out {
345 struct mlx5_outbox_hdr hdr;
346 u8 rsvd0[8];
347 struct mlx5_hca_cap hca_cap;
348};
349
350
351struct mlx5_cmd_set_hca_cap_mbox_in {
352 struct mlx5_inbox_hdr hdr;
353 u8 rsvd[8];
354 struct mlx5_hca_cap hca_cap;
355};
356
357
358struct mlx5_cmd_set_hca_cap_mbox_out {
359 struct mlx5_outbox_hdr hdr;
360 u8 rsvd0[8];
361};
362
363
364struct mlx5_cmd_init_hca_mbox_in {
365 struct mlx5_inbox_hdr hdr;
366 u8 rsvd0[2];
367 __be16 profile;
368 u8 rsvd1[4];
369};
370
371struct mlx5_cmd_init_hca_mbox_out {
372 struct mlx5_outbox_hdr hdr;
373 u8 rsvd[8];
374};
375
376struct mlx5_cmd_teardown_hca_mbox_in {
377 struct mlx5_inbox_hdr hdr;
378 u8 rsvd0[2];
379 __be16 profile;
380 u8 rsvd1[4];
381};
382
383struct mlx5_cmd_teardown_hca_mbox_out {
384 struct mlx5_outbox_hdr hdr;
385 u8 rsvd[8];
386};
387
388struct mlx5_cmd_layout {
389 u8 type;
390 u8 rsvd0[3];
391 __be32 inlen;
392 __be64 in_ptr;
393 __be32 in[4];
394 __be32 out[4];
395 __be64 out_ptr;
396 __be32 outlen;
397 u8 token;
398 u8 sig;
399 u8 rsvd1;
400 u8 status_own;
401};
402
403
404struct health_buffer {
405 __be32 assert_var[5];
406 __be32 rsvd0[3];
407 __be32 assert_exit_ptr;
408 __be32 assert_callra;
409 __be32 rsvd1[2];
410 __be32 fw_ver;
411 __be32 hw_id;
412 __be32 rsvd2;
413 u8 irisc_index;
414 u8 synd;
415 __be16 ext_sync;
416};
417
418struct mlx5_init_seg {
419 __be32 fw_rev;
420 __be32 cmdif_rev_fw_sub;
421 __be32 rsvd0[2];
422 __be32 cmdq_addr_h;
423 __be32 cmdq_addr_l_sz;
424 __be32 cmd_dbell;
425 __be32 rsvd1[121];
426 struct health_buffer health;
427 __be32 rsvd2[884];
428 __be32 health_counter;
429 __be32 rsvd3[1019];
430 __be64 ieee1588_clk;
431 __be32 ieee1588_clk_type;
432 __be32 clr_intx;
433};
434
435struct mlx5_eqe_comp {
436 __be32 reserved[6];
437 __be32 cqn;
438};
439
440struct mlx5_eqe_qp_srq {
441 __be32 reserved[6];
442 __be32 qp_srq_n;
443};
444
445struct mlx5_eqe_cq_err {
446 __be32 cqn;
447 u8 reserved1[7];
448 u8 syndrome;
449};
450
451struct mlx5_eqe_dropped_packet {
452};
453
454struct mlx5_eqe_port_state {
455 u8 reserved0[8];
456 u8 port;
457};
458
459struct mlx5_eqe_gpio {
460 __be32 reserved0[2];
461 __be64 gpio_event;
462};
463
464struct mlx5_eqe_congestion {
465 u8 type;
466 u8 rsvd0;
467 u8 congestion_level;
468};
469
470struct mlx5_eqe_stall_vl {
471 u8 rsvd0[3];
472 u8 port_vl;
473};
474
475struct mlx5_eqe_cmd {
476 __be32 vector;
477 __be32 rsvd[6];
478};
479
480struct mlx5_eqe_page_req {
481 u8 rsvd0[2];
482 __be16 func_id;
483 __be32 num_pages;
484 __be32 rsvd1[5];
485};
486
487union ev_data {
488 __be32 raw[7];
489 struct mlx5_eqe_cmd cmd;
490 struct mlx5_eqe_comp comp;
491 struct mlx5_eqe_qp_srq qp_srq;
492 struct mlx5_eqe_cq_err cq_err;
493 struct mlx5_eqe_dropped_packet dp;
494 struct mlx5_eqe_port_state port;
495 struct mlx5_eqe_gpio gpio;
496 struct mlx5_eqe_congestion cong;
497 struct mlx5_eqe_stall_vl stall_vl;
498 struct mlx5_eqe_page_req req_pages;
499} __packed;
500
501struct mlx5_eqe {
502 u8 rsvd0;
503 u8 type;
504 u8 rsvd1;
505 u8 sub_type;
506 __be32 rsvd2[7];
507 union ev_data data;
508 __be16 rsvd3;
509 u8 signature;
510 u8 owner;
511} __packed;
512
513struct mlx5_cmd_prot_block {
514 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
515 u8 rsvd0[48];
516 __be64 next;
517 __be32 block_num;
518 u8 rsvd1;
519 u8 token;
520 u8 ctrl_sig;
521 u8 sig;
522};
523
524struct mlx5_err_cqe {
525 u8 rsvd0[32];
526 __be32 srqn;
527 u8 rsvd1[18];
528 u8 vendor_err_synd;
529 u8 syndrome;
530 __be32 s_wqe_opcode_qpn;
531 __be16 wqe_counter;
532 u8 signature;
533 u8 op_own;
534};
535
536struct mlx5_cqe64 {
537 u8 rsvd0[17];
538 u8 ml_path;
539 u8 rsvd20[4];
540 __be16 slid;
541 __be32 flags_rqpn;
542 u8 rsvd28[4];
543 __be32 srqn;
544 __be32 imm_inval_pkey;
545 u8 rsvd40[4];
546 __be32 byte_cnt;
547 __be64 timestamp;
548 __be32 sop_drop_qpn;
549 __be16 wqe_counter;
550 u8 signature;
551 u8 op_own;
552};
553
554struct mlx5_wqe_srq_next_seg {
555 u8 rsvd0[2];
556 __be16 next_wqe_index;
557 u8 signature;
558 u8 rsvd1[11];
559};
560
561union mlx5_ext_cqe {
562 struct ib_grh grh;
563 u8 inl[64];
564};
565
566struct mlx5_cqe128 {
567 union mlx5_ext_cqe inl_grh;
568 struct mlx5_cqe64 cqe64;
569};
570
571struct mlx5_srq_ctx {
572 u8 state_log_sz;
573 u8 rsvd0[3];
574 __be32 flags_xrcd;
575 __be32 pgoff_cqn;
576 u8 rsvd1[4];
577 u8 log_pg_sz;
578 u8 rsvd2[7];
579 __be32 pd;
580 __be16 lwm;
581 __be16 wqe_cnt;
582 u8 rsvd3[8];
583 __be64 db_record;
584};
585
586struct mlx5_create_srq_mbox_in {
587 struct mlx5_inbox_hdr hdr;
588 __be32 input_srqn;
589 u8 rsvd0[4];
590 struct mlx5_srq_ctx ctx;
591 u8 rsvd1[208];
592 __be64 pas[0];
593};
594
595struct mlx5_create_srq_mbox_out {
596 struct mlx5_outbox_hdr hdr;
597 __be32 srqn;
598 u8 rsvd[4];
599};
600
601struct mlx5_destroy_srq_mbox_in {
602 struct mlx5_inbox_hdr hdr;
603 __be32 srqn;
604 u8 rsvd[4];
605};
606
607struct mlx5_destroy_srq_mbox_out {
608 struct mlx5_outbox_hdr hdr;
609 u8 rsvd[8];
610};
611
612struct mlx5_query_srq_mbox_in {
613 struct mlx5_inbox_hdr hdr;
614 __be32 srqn;
615 u8 rsvd0[4];
616};
617
618struct mlx5_query_srq_mbox_out {
619 struct mlx5_outbox_hdr hdr;
620 u8 rsvd0[8];
621 struct mlx5_srq_ctx ctx;
622 u8 rsvd1[32];
623 __be64 pas[0];
624};
625
626struct mlx5_arm_srq_mbox_in {
627 struct mlx5_inbox_hdr hdr;
628 __be32 srqn;
629 __be16 rsvd;
630 __be16 lwm;
631};
632
633struct mlx5_arm_srq_mbox_out {
634 struct mlx5_outbox_hdr hdr;
635 u8 rsvd[8];
636};
637
638struct mlx5_cq_context {
639 u8 status;
640 u8 cqe_sz_flags;
641 u8 st;
642 u8 rsvd3;
643 u8 rsvd4[6];
644 __be16 page_offset;
645 __be32 log_sz_usr_page;
646 __be16 cq_period;
647 __be16 cq_max_count;
648 __be16 rsvd20;
649 __be16 c_eqn;
650 u8 log_pg_sz;
651 u8 rsvd25[7];
652 __be32 last_notified_index;
653 __be32 solicit_producer_index;
654 __be32 consumer_counter;
655 __be32 producer_counter;
656 u8 rsvd48[8];
657 __be64 db_record_addr;
658};
659
660struct mlx5_create_cq_mbox_in {
661 struct mlx5_inbox_hdr hdr;
662 __be32 input_cqn;
663 u8 rsvdx[4];
664 struct mlx5_cq_context ctx;
665 u8 rsvd6[192];
666 __be64 pas[0];
667};
668
669struct mlx5_create_cq_mbox_out {
670 struct mlx5_outbox_hdr hdr;
671 __be32 cqn;
672 u8 rsvd0[4];
673};
674
675struct mlx5_destroy_cq_mbox_in {
676 struct mlx5_inbox_hdr hdr;
677 __be32 cqn;
678 u8 rsvd0[4];
679};
680
681struct mlx5_destroy_cq_mbox_out {
682 struct mlx5_outbox_hdr hdr;
683 u8 rsvd0[8];
684};
685
686struct mlx5_query_cq_mbox_in {
687 struct mlx5_inbox_hdr hdr;
688 __be32 cqn;
689 u8 rsvd0[4];
690};
691
692struct mlx5_query_cq_mbox_out {
693 struct mlx5_outbox_hdr hdr;
694 u8 rsvd0[8];
695 struct mlx5_cq_context ctx;
696 u8 rsvd6[16];
697 __be64 pas[0];
698};
699
700struct mlx5_enable_hca_mbox_in {
701 struct mlx5_inbox_hdr hdr;
702 u8 rsvd[8];
703};
704
705struct mlx5_enable_hca_mbox_out {
706 struct mlx5_outbox_hdr hdr;
707 u8 rsvd[8];
708};
709
710struct mlx5_disable_hca_mbox_in {
711 struct mlx5_inbox_hdr hdr;
712 u8 rsvd[8];
713};
714
715struct mlx5_disable_hca_mbox_out {
716 struct mlx5_outbox_hdr hdr;
717 u8 rsvd[8];
718};
719
720struct mlx5_eq_context {
721 u8 status;
722 u8 ec_oi;
723 u8 st;
724 u8 rsvd2[7];
725 __be16 page_pffset;
726 __be32 log_sz_usr_page;
727 u8 rsvd3[7];
728 u8 intr;
729 u8 log_page_size;
730 u8 rsvd4[15];
731 __be32 consumer_counter;
732 __be32 produser_counter;
733 u8 rsvd5[16];
734};
735
736struct mlx5_create_eq_mbox_in {
737 struct mlx5_inbox_hdr hdr;
738 u8 rsvd0[3];
739 u8 input_eqn;
740 u8 rsvd1[4];
741 struct mlx5_eq_context ctx;
742 u8 rsvd2[8];
743 __be64 events_mask;
744 u8 rsvd3[176];
745 __be64 pas[0];
746};
747
748struct mlx5_create_eq_mbox_out {
749 struct mlx5_outbox_hdr hdr;
750 u8 rsvd0[3];
751 u8 eq_number;
752 u8 rsvd1[4];
753};
754
755struct mlx5_destroy_eq_mbox_in {
756 struct mlx5_inbox_hdr hdr;
757 u8 rsvd0[3];
758 u8 eqn;
759 u8 rsvd1[4];
760};
761
762struct mlx5_destroy_eq_mbox_out {
763 struct mlx5_outbox_hdr hdr;
764 u8 rsvd[8];
765};
766
767struct mlx5_map_eq_mbox_in {
768 struct mlx5_inbox_hdr hdr;
769 __be64 mask;
770 u8 mu;
771 u8 rsvd0[2];
772 u8 eqn;
773 u8 rsvd1[24];
774};
775
776struct mlx5_map_eq_mbox_out {
777 struct mlx5_outbox_hdr hdr;
778 u8 rsvd[8];
779};
780
781struct mlx5_query_eq_mbox_in {
782 struct mlx5_inbox_hdr hdr;
783 u8 rsvd0[3];
784 u8 eqn;
785 u8 rsvd1[4];
786};
787
788struct mlx5_query_eq_mbox_out {
789 struct mlx5_outbox_hdr hdr;
790 u8 rsvd[8];
791 struct mlx5_eq_context ctx;
792};
793
794struct mlx5_mkey_seg {
795 /* This is a two bit field occupying bits 31-30.
796 * bit 31 is always 0,
797 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
798 */
799 u8 status;
800 u8 pcie_control;
801 u8 flags;
802 u8 version;
803 __be32 qpn_mkey7_0;
804 u8 rsvd1[4];
805 __be32 flags_pd;
806 __be64 start_addr;
807 __be64 len;
808 __be32 bsfs_octo_size;
809 u8 rsvd2[16];
810 __be32 xlt_oct_size;
811 u8 rsvd3[3];
812 u8 log2_page_size;
813 u8 rsvd4[4];
814};
815
816struct mlx5_query_special_ctxs_mbox_in {
817 struct mlx5_inbox_hdr hdr;
818 u8 rsvd[8];
819};
820
821struct mlx5_query_special_ctxs_mbox_out {
822 struct mlx5_outbox_hdr hdr;
823 __be32 dump_fill_mkey;
824 __be32 reserved_lkey;
825};
826
827struct mlx5_create_mkey_mbox_in {
828 struct mlx5_inbox_hdr hdr;
829 __be32 input_mkey_index;
830 u8 rsvd0[4];
831 struct mlx5_mkey_seg seg;
832 u8 rsvd1[16];
833 __be32 xlat_oct_act_size;
834 __be32 bsf_coto_act_size;
835 u8 rsvd2[168];
836 __be64 pas[0];
837};
838
839struct mlx5_create_mkey_mbox_out {
840 struct mlx5_outbox_hdr hdr;
841 __be32 mkey;
842 u8 rsvd[4];
843};
844
845struct mlx5_destroy_mkey_mbox_in {
846 struct mlx5_inbox_hdr hdr;
847 __be32 mkey;
848 u8 rsvd[4];
849};
850
851struct mlx5_destroy_mkey_mbox_out {
852 struct mlx5_outbox_hdr hdr;
853 u8 rsvd[8];
854};
855
856struct mlx5_query_mkey_mbox_in {
857 struct mlx5_inbox_hdr hdr;
858 __be32 mkey;
859};
860
861struct mlx5_query_mkey_mbox_out {
862 struct mlx5_outbox_hdr hdr;
863 __be64 pas[0];
864};
865
866struct mlx5_modify_mkey_mbox_in {
867 struct mlx5_inbox_hdr hdr;
868 __be32 mkey;
869 __be64 pas[0];
870};
871
872struct mlx5_modify_mkey_mbox_out {
873 struct mlx5_outbox_hdr hdr;
874};
875
876struct mlx5_dump_mkey_mbox_in {
877 struct mlx5_inbox_hdr hdr;
878};
879
880struct mlx5_dump_mkey_mbox_out {
881 struct mlx5_outbox_hdr hdr;
882 __be32 mkey;
883};
884
885struct mlx5_mad_ifc_mbox_in {
886 struct mlx5_inbox_hdr hdr;
887 __be16 remote_lid;
888 u8 rsvd0;
889 u8 port;
890 u8 rsvd1[4];
891 u8 data[256];
892};
893
894struct mlx5_mad_ifc_mbox_out {
895 struct mlx5_outbox_hdr hdr;
896 u8 rsvd[8];
897 u8 data[256];
898};
899
900struct mlx5_access_reg_mbox_in {
901 struct mlx5_inbox_hdr hdr;
902 u8 rsvd0[2];
903 __be16 register_id;
904 __be32 arg;
905 __be32 data[0];
906};
907
908struct mlx5_access_reg_mbox_out {
909 struct mlx5_outbox_hdr hdr;
910 u8 rsvd[8];
911 __be32 data[0];
912};
913
914#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
915
916enum {
917 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
918};
919
920#endif /* MLX5_DEVICE_H */