tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom
kernel / include / linux / mfd / palmas.h
at v3.13 2931 lines 115 kB view raw
1/* 2 * TI Palmas 3 * 4 * Copyright 2011-2013 Texas Instruments Inc. 5 * 6 * Author: Graeme Gregory <gg@slimlogic.co.uk> 7 * Author: Ian Lartey <ian@slimlogic.co.uk> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 */ 15 16#ifndef __LINUX_MFD_PALMAS_H 17#define __LINUX_MFD_PALMAS_H 18 19#include <linux/usb/otg.h> 20#include <linux/leds.h> 21#include <linux/regmap.h> 22#include <linux/regulator/driver.h> 23#include <linux/extcon.h> 24#include <linux/usb/phy_companion.h> 25 26#define PALMAS_NUM_CLIENTS 3 27 28/* The ID_REVISION NUMBERS */ 29#define PALMAS_CHIP_OLD_ID 0x0000 30#define PALMAS_CHIP_ID 0xC035 31#define PALMAS_CHIP_CHARGER_ID 0xC036 32 33#define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \ 34 ((a) == PALMAS_CHIP_ID)) 35#define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID) 36 37/** 38 * Palmas PMIC feature types 39 * 40 * PALMAS_PMIC_FEATURE_SMPS10_BOOST - used when the PMIC provides SMPS10_BOOST 41 * regulator. 42 * 43 * PALMAS_PMIC_HAS(b, f) - macro to check if a bandgap device is capable of a 44 * specific feature (above) or not. Return non-zero, if yes. 45 */ 46#define PALMAS_PMIC_FEATURE_SMPS10_BOOST BIT(0) 47#define PALMAS_PMIC_HAS(b, f) \ 48 ((b)->features & PALMAS_PMIC_FEATURE_ ## f) 49 50struct palmas_pmic; 51struct palmas_gpadc; 52struct palmas_resource; 53struct palmas_usb; 54 55enum palmas_usb_state { 56 PALMAS_USB_STATE_DISCONNECT, 57 PALMAS_USB_STATE_VBUS, 58 PALMAS_USB_STATE_ID, 59}; 60 61struct palmas { 62 struct device *dev; 63 64 struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS]; 65 struct regmap *regmap[PALMAS_NUM_CLIENTS]; 66 67 /* Stored chip id */ 68 int id; 69 70 unsigned int features; 71 /* IRQ Data */ 72 int irq; 73 u32 irq_mask; 74 struct mutex irq_lock; 75 struct regmap_irq_chip_data *irq_data; 76 77 /* Child Devices */ 78 struct palmas_pmic *pmic; 79 struct palmas_gpadc *gpadc; 80 struct palmas_resource *resource; 81 struct palmas_usb *usb; 82 83 /* GPIO MUXing */ 84 u8 gpio_muxed; 85 u8 led_muxed; 86 u8 pwm_muxed; 87}; 88 89struct palmas_gpadc_platform_data { 90 /* Channel 3 current source is only enabled during conversion */ 91 int ch3_current; 92 93 /* Channel 0 current source can be used for battery detection. 94 * If used for battery detection this will cause a permanent current 95 * consumption depending on current level set here. 96 */ 97 int ch0_current; 98 99 /* default BAT_REMOVAL_DAT setting on device probe */ 100 int bat_removal; 101 102 /* Sets the START_POLARITY bit in the RT_CTRL register */ 103 int start_polarity; 104}; 105 106struct palmas_reg_init { 107 /* warm_rest controls the voltage levels after a warm reset 108 * 109 * 0: reload default values from OTP on warm reset 110 * 1: maintain voltage from VSEL on warm reset 111 */ 112 int warm_reset; 113 114 /* roof_floor controls whether the regulator uses the i2c style 115 * of DVS or uses the method where a GPIO or other control method is 116 * attached to the NSLEEP/ENABLE1/ENABLE2 pins 117 * 118 * For SMPS 119 * 120 * 0: i2c selection of voltage 121 * 1: pin selection of voltage. 122 * 123 * For LDO unused 124 */ 125 int roof_floor; 126 127 /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in 128 * the data sheet. 129 * 130 * For SMPS 131 * 132 * 0: Off 133 * 1: AUTO 134 * 2: ECO 135 * 3: Forced PWM 136 * 137 * For LDO 138 * 139 * 0: Off 140 * 1: On 141 */ 142 int mode_sleep; 143 144 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE 145 * register. Set this is the default voltage set in OTP needs 146 * to be overridden. 147 */ 148 u8 vsel; 149 150}; 151 152enum palmas_regulators { 153 /* SMPS regulators */ 154 PALMAS_REG_SMPS12, 155 PALMAS_REG_SMPS123, 156 PALMAS_REG_SMPS3, 157 PALMAS_REG_SMPS45, 158 PALMAS_REG_SMPS457, 159 PALMAS_REG_SMPS6, 160 PALMAS_REG_SMPS7, 161 PALMAS_REG_SMPS8, 162 PALMAS_REG_SMPS9, 163 PALMAS_REG_SMPS10_OUT2, 164 PALMAS_REG_SMPS10_OUT1, 165 /* LDO regulators */ 166 PALMAS_REG_LDO1, 167 PALMAS_REG_LDO2, 168 PALMAS_REG_LDO3, 169 PALMAS_REG_LDO4, 170 PALMAS_REG_LDO5, 171 PALMAS_REG_LDO6, 172 PALMAS_REG_LDO7, 173 PALMAS_REG_LDO8, 174 PALMAS_REG_LDO9, 175 PALMAS_REG_LDOLN, 176 PALMAS_REG_LDOUSB, 177 /* External regulators */ 178 PALMAS_REG_REGEN1, 179 PALMAS_REG_REGEN2, 180 PALMAS_REG_REGEN3, 181 PALMAS_REG_SYSEN1, 182 PALMAS_REG_SYSEN2, 183 /* Total number of regulators */ 184 PALMAS_NUM_REGS, 185}; 186 187/* External controll signal name */ 188enum { 189 PALMAS_EXT_CONTROL_ENABLE1 = 0x1, 190 PALMAS_EXT_CONTROL_ENABLE2 = 0x2, 191 PALMAS_EXT_CONTROL_NSLEEP = 0x4, 192}; 193 194/* 195 * Palmas device resources can be controlled externally for 196 * enabling/disabling it rather than register write through i2c. 197 * Add the external controlled requestor ID for different resources. 198 */ 199enum palmas_external_requestor_id { 200 PALMAS_EXTERNAL_REQSTR_ID_REGEN1, 201 PALMAS_EXTERNAL_REQSTR_ID_REGEN2, 202 PALMAS_EXTERNAL_REQSTR_ID_SYSEN1, 203 PALMAS_EXTERNAL_REQSTR_ID_SYSEN2, 204 PALMAS_EXTERNAL_REQSTR_ID_CLK32KG, 205 PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO, 206 PALMAS_EXTERNAL_REQSTR_ID_REGEN3, 207 PALMAS_EXTERNAL_REQSTR_ID_SMPS12, 208 PALMAS_EXTERNAL_REQSTR_ID_SMPS3, 209 PALMAS_EXTERNAL_REQSTR_ID_SMPS45, 210 PALMAS_EXTERNAL_REQSTR_ID_SMPS6, 211 PALMAS_EXTERNAL_REQSTR_ID_SMPS7, 212 PALMAS_EXTERNAL_REQSTR_ID_SMPS8, 213 PALMAS_EXTERNAL_REQSTR_ID_SMPS9, 214 PALMAS_EXTERNAL_REQSTR_ID_SMPS10, 215 PALMAS_EXTERNAL_REQSTR_ID_LDO1, 216 PALMAS_EXTERNAL_REQSTR_ID_LDO2, 217 PALMAS_EXTERNAL_REQSTR_ID_LDO3, 218 PALMAS_EXTERNAL_REQSTR_ID_LDO4, 219 PALMAS_EXTERNAL_REQSTR_ID_LDO5, 220 PALMAS_EXTERNAL_REQSTR_ID_LDO6, 221 PALMAS_EXTERNAL_REQSTR_ID_LDO7, 222 PALMAS_EXTERNAL_REQSTR_ID_LDO8, 223 PALMAS_EXTERNAL_REQSTR_ID_LDO9, 224 PALMAS_EXTERNAL_REQSTR_ID_LDOLN, 225 PALMAS_EXTERNAL_REQSTR_ID_LDOUSB, 226 227 /* Last entry */ 228 PALMAS_EXTERNAL_REQSTR_ID_MAX, 229}; 230 231struct palmas_pmic_platform_data { 232 /* An array of pointers to regulator init data indexed by regulator 233 * ID 234 */ 235 struct regulator_init_data *reg_data[PALMAS_NUM_REGS]; 236 237 /* An array of pointers to structures containing sleep mode and DVS 238 * configuration for regulators indexed by ID 239 */ 240 struct palmas_reg_init *reg_init[PALMAS_NUM_REGS]; 241 242 /* use LDO6 for vibrator control */ 243 int ldo6_vibrator; 244 245 /* Enable tracking mode of LDO8 */ 246 bool enable_ldo8_tracking; 247}; 248 249struct palmas_usb_platform_data { 250 /* Do we enable the wakeup comparator on probe */ 251 int wakeup; 252}; 253 254struct palmas_resource_platform_data { 255 int regen1_mode_sleep; 256 int regen2_mode_sleep; 257 int sysen1_mode_sleep; 258 int sysen2_mode_sleep; 259 260 /* bitfield to be loaded to NSLEEP_RES_ASSIGN */ 261 u8 nsleep_res; 262 /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */ 263 u8 nsleep_smps; 264 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */ 265 u8 nsleep_ldo1; 266 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */ 267 u8 nsleep_ldo2; 268 269 /* bitfield to be loaded to ENABLE1_RES_ASSIGN */ 270 u8 enable1_res; 271 /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */ 272 u8 enable1_smps; 273 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */ 274 u8 enable1_ldo1; 275 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */ 276 u8 enable1_ldo2; 277 278 /* bitfield to be loaded to ENABLE2_RES_ASSIGN */ 279 u8 enable2_res; 280 /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */ 281 u8 enable2_smps; 282 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */ 283 u8 enable2_ldo1; 284 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */ 285 u8 enable2_ldo2; 286}; 287 288struct palmas_clk_platform_data { 289 int clk32kg_mode_sleep; 290 int clk32kgaudio_mode_sleep; 291}; 292 293struct palmas_platform_data { 294 int irq_flags; 295 int gpio_base; 296 297 /* bit value to be loaded to the POWER_CTRL register */ 298 u8 power_ctrl; 299 300 /* 301 * boolean to select if we want to configure muxing here 302 * then the two value to load into the registers if true 303 */ 304 int mux_from_pdata; 305 u8 pad1, pad2; 306 bool pm_off; 307 308 struct palmas_pmic_platform_data *pmic_pdata; 309 struct palmas_gpadc_platform_data *gpadc_pdata; 310 struct palmas_usb_platform_data *usb_pdata; 311 struct palmas_resource_platform_data *resource_pdata; 312 struct palmas_clk_platform_data *clk_pdata; 313}; 314 315struct palmas_gpadc_calibration { 316 s32 gain; 317 s32 gain_error; 318 s32 offset_error; 319}; 320 321struct palmas_gpadc { 322 struct device *dev; 323 struct palmas *palmas; 324 325 int ch3_current; 326 int ch0_current; 327 328 int gpadc_force; 329 330 int bat_removal; 331 332 struct mutex reading_lock; 333 struct completion irq_complete; 334 335 int eoc_sw_irq; 336 337 struct palmas_gpadc_calibration *palmas_cal_tbl; 338 339 int conv0_channel; 340 int conv1_channel; 341 int rt_channel; 342}; 343 344struct palmas_gpadc_result { 345 s32 raw_code; 346 s32 corrected_code; 347 s32 result; 348}; 349 350#define PALMAS_MAX_CHANNELS 16 351 352/* Define the palmas IRQ numbers */ 353enum palmas_irqs { 354 /* INT1 registers */ 355 PALMAS_CHARG_DET_N_VBUS_OVV_IRQ, 356 PALMAS_PWRON_IRQ, 357 PALMAS_LONG_PRESS_KEY_IRQ, 358 PALMAS_RPWRON_IRQ, 359 PALMAS_PWRDOWN_IRQ, 360 PALMAS_HOTDIE_IRQ, 361 PALMAS_VSYS_MON_IRQ, 362 PALMAS_VBAT_MON_IRQ, 363 /* INT2 registers */ 364 PALMAS_RTC_ALARM_IRQ, 365 PALMAS_RTC_TIMER_IRQ, 366 PALMAS_WDT_IRQ, 367 PALMAS_BATREMOVAL_IRQ, 368 PALMAS_RESET_IN_IRQ, 369 PALMAS_FBI_BB_IRQ, 370 PALMAS_SHORT_IRQ, 371 PALMAS_VAC_ACOK_IRQ, 372 /* INT3 registers */ 373 PALMAS_GPADC_AUTO_0_IRQ, 374 PALMAS_GPADC_AUTO_1_IRQ, 375 PALMAS_GPADC_EOC_SW_IRQ, 376 PALMAS_GPADC_EOC_RT_IRQ, 377 PALMAS_ID_OTG_IRQ, 378 PALMAS_ID_IRQ, 379 PALMAS_VBUS_OTG_IRQ, 380 PALMAS_VBUS_IRQ, 381 /* INT4 registers */ 382 PALMAS_GPIO_0_IRQ, 383 PALMAS_GPIO_1_IRQ, 384 PALMAS_GPIO_2_IRQ, 385 PALMAS_GPIO_3_IRQ, 386 PALMAS_GPIO_4_IRQ, 387 PALMAS_GPIO_5_IRQ, 388 PALMAS_GPIO_6_IRQ, 389 PALMAS_GPIO_7_IRQ, 390 /* Total Number IRQs */ 391 PALMAS_NUM_IRQ, 392}; 393 394struct palmas_pmic { 395 struct palmas *palmas; 396 struct device *dev; 397 struct regulator_desc desc[PALMAS_NUM_REGS]; 398 struct regulator_dev *rdev[PALMAS_NUM_REGS]; 399 struct mutex mutex; 400 401 int smps123; 402 int smps457; 403 404 int range[PALMAS_REG_SMPS10_OUT1]; 405 unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1]; 406 unsigned int current_reg_mode[PALMAS_REG_SMPS10_OUT1]; 407}; 408 409struct palmas_resource { 410 struct palmas *palmas; 411 struct device *dev; 412}; 413 414struct palmas_usb { 415 struct palmas *palmas; 416 struct device *dev; 417 418 struct extcon_dev edev; 419 420 int id_otg_irq; 421 int id_irq; 422 int vbus_otg_irq; 423 int vbus_irq; 424 425 enum palmas_usb_state linkstat; 426 int wakeup; 427 bool enable_vbus_detection; 428 bool enable_id_detection; 429}; 430 431#define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator) 432 433enum usb_irq_events { 434 /* Wakeup events from INT3 */ 435 PALMAS_USB_ID_WAKEPUP, 436 PALMAS_USB_VBUS_WAKEUP, 437 438 /* ID_OTG_EVENTS */ 439 PALMAS_USB_ID_GND, 440 N_PALMAS_USB_ID_GND, 441 PALMAS_USB_ID_C, 442 N_PALMAS_USB_ID_C, 443 PALMAS_USB_ID_B, 444 N_PALMAS_USB_ID_B, 445 PALMAS_USB_ID_A, 446 N_PALMAS_USB_ID_A, 447 PALMAS_USB_ID_FLOAT, 448 N_PALMAS_USB_ID_FLOAT, 449 450 /* VBUS_OTG_EVENTS */ 451 PALMAS_USB_VB_SESS_END, 452 N_PALMAS_USB_VB_SESS_END, 453 PALMAS_USB_VB_SESS_VLD, 454 N_PALMAS_USB_VB_SESS_VLD, 455 PALMAS_USB_VA_SESS_VLD, 456 N_PALMAS_USB_VA_SESS_VLD, 457 PALMAS_USB_VA_VBUS_VLD, 458 N_PALMAS_USB_VA_VBUS_VLD, 459 PALMAS_USB_VADP_SNS, 460 N_PALMAS_USB_VADP_SNS, 461 PALMAS_USB_VADP_PRB, 462 N_PALMAS_USB_VADP_PRB, 463 PALMAS_USB_VOTG_SESS_VLD, 464 N_PALMAS_USB_VOTG_SESS_VLD, 465}; 466 467/* defines so we can store the mux settings */ 468#define PALMAS_GPIO_0_MUXED (1 << 0) 469#define PALMAS_GPIO_1_MUXED (1 << 1) 470#define PALMAS_GPIO_2_MUXED (1 << 2) 471#define PALMAS_GPIO_3_MUXED (1 << 3) 472#define PALMAS_GPIO_4_MUXED (1 << 4) 473#define PALMAS_GPIO_5_MUXED (1 << 5) 474#define PALMAS_GPIO_6_MUXED (1 << 6) 475#define PALMAS_GPIO_7_MUXED (1 << 7) 476 477#define PALMAS_LED1_MUXED (1 << 0) 478#define PALMAS_LED2_MUXED (1 << 1) 479 480#define PALMAS_PWM1_MUXED (1 << 0) 481#define PALMAS_PWM2_MUXED (1 << 1) 482 483/* helper macro to get correct slave number */ 484#define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1) 485#define PALMAS_BASE_TO_REG(x, y) ((x & 0xff) + y) 486 487/* Base addresses of IP blocks in Palmas */ 488#define PALMAS_SMPS_DVS_BASE 0x20 489#define PALMAS_RTC_BASE 0x100 490#define PALMAS_VALIDITY_BASE 0x118 491#define PALMAS_SMPS_BASE 0x120 492#define PALMAS_LDO_BASE 0x150 493#define PALMAS_DVFS_BASE 0x180 494#define PALMAS_PMU_CONTROL_BASE 0x1A0 495#define PALMAS_RESOURCE_BASE 0x1D4 496#define PALMAS_PU_PD_OD_BASE 0x1F0 497#define PALMAS_LED_BASE 0x200 498#define PALMAS_INTERRUPT_BASE 0x210 499#define PALMAS_USB_OTG_BASE 0x250 500#define PALMAS_VIBRATOR_BASE 0x270 501#define PALMAS_GPIO_BASE 0x280 502#define PALMAS_USB_BASE 0x290 503#define PALMAS_GPADC_BASE 0x2C0 504#define PALMAS_TRIM_GPADC_BASE 0x3CD 505 506/* Registers for function RTC */ 507#define PALMAS_SECONDS_REG 0x0 508#define PALMAS_MINUTES_REG 0x1 509#define PALMAS_HOURS_REG 0x2 510#define PALMAS_DAYS_REG 0x3 511#define PALMAS_MONTHS_REG 0x4 512#define PALMAS_YEARS_REG 0x5 513#define PALMAS_WEEKS_REG 0x6 514#define PALMAS_ALARM_SECONDS_REG 0x8 515#define PALMAS_ALARM_MINUTES_REG 0x9 516#define PALMAS_ALARM_HOURS_REG 0xA 517#define PALMAS_ALARM_DAYS_REG 0xB 518#define PALMAS_ALARM_MONTHS_REG 0xC 519#define PALMAS_ALARM_YEARS_REG 0xD 520#define PALMAS_RTC_CTRL_REG 0x10 521#define PALMAS_RTC_STATUS_REG 0x11 522#define PALMAS_RTC_INTERRUPTS_REG 0x12 523#define PALMAS_RTC_COMP_LSB_REG 0x13 524#define PALMAS_RTC_COMP_MSB_REG 0x14 525#define PALMAS_RTC_RES_PROG_REG 0x15 526#define PALMAS_RTC_RESET_STATUS_REG 0x16 527 528/* Bit definitions for SECONDS_REG */ 529#define PALMAS_SECONDS_REG_SEC1_MASK 0x70 530#define PALMAS_SECONDS_REG_SEC1_SHIFT 4 531#define PALMAS_SECONDS_REG_SEC0_MASK 0x0f 532#define PALMAS_SECONDS_REG_SEC0_SHIFT 0 533 534/* Bit definitions for MINUTES_REG */ 535#define PALMAS_MINUTES_REG_MIN1_MASK 0x70 536#define PALMAS_MINUTES_REG_MIN1_SHIFT 4 537#define PALMAS_MINUTES_REG_MIN0_MASK 0x0f 538#define PALMAS_MINUTES_REG_MIN0_SHIFT 0 539 540/* Bit definitions for HOURS_REG */ 541#define PALMAS_HOURS_REG_PM_NAM 0x80 542#define PALMAS_HOURS_REG_PM_NAM_SHIFT 7 543#define PALMAS_HOURS_REG_HOUR1_MASK 0x30 544#define PALMAS_HOURS_REG_HOUR1_SHIFT 4 545#define PALMAS_HOURS_REG_HOUR0_MASK 0x0f 546#define PALMAS_HOURS_REG_HOUR0_SHIFT 0 547 548/* Bit definitions for DAYS_REG */ 549#define PALMAS_DAYS_REG_DAY1_MASK 0x30 550#define PALMAS_DAYS_REG_DAY1_SHIFT 4 551#define PALMAS_DAYS_REG_DAY0_MASK 0x0f 552#define PALMAS_DAYS_REG_DAY0_SHIFT 0 553 554/* Bit definitions for MONTHS_REG */ 555#define PALMAS_MONTHS_REG_MONTH1 0x10 556#define PALMAS_MONTHS_REG_MONTH1_SHIFT 4 557#define PALMAS_MONTHS_REG_MONTH0_MASK 0x0f 558#define PALMAS_MONTHS_REG_MONTH0_SHIFT 0 559 560/* Bit definitions for YEARS_REG */ 561#define PALMAS_YEARS_REG_YEAR1_MASK 0xf0 562#define PALMAS_YEARS_REG_YEAR1_SHIFT 4 563#define PALMAS_YEARS_REG_YEAR0_MASK 0x0f 564#define PALMAS_YEARS_REG_YEAR0_SHIFT 0 565 566/* Bit definitions for WEEKS_REG */ 567#define PALMAS_WEEKS_REG_WEEK_MASK 0x07 568#define PALMAS_WEEKS_REG_WEEK_SHIFT 0 569 570/* Bit definitions for ALARM_SECONDS_REG */ 571#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70 572#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 4 573#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0f 574#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0 575 576/* Bit definitions for ALARM_MINUTES_REG */ 577#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70 578#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 4 579#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0f 580#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0 581 582/* Bit definitions for ALARM_HOURS_REG */ 583#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80 584#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 7 585#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30 586#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 4 587#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0f 588#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0 589 590/* Bit definitions for ALARM_DAYS_REG */ 591#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30 592#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 4 593#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0f 594#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0 595 596/* Bit definitions for ALARM_MONTHS_REG */ 597#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10 598#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 4 599#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0f 600#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0 601 602/* Bit definitions for ALARM_YEARS_REG */ 603#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0 604#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 4 605#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0f 606#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0 607 608/* Bit definitions for RTC_CTRL_REG */ 609#define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80 610#define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 7 611#define PALMAS_RTC_CTRL_REG_GET_TIME 0x40 612#define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 6 613#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20 614#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 5 615#define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10 616#define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 4 617#define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08 618#define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 3 619#define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04 620#define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 2 621#define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02 622#define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 1 623#define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01 624#define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0 625 626/* Bit definitions for RTC_STATUS_REG */ 627#define PALMAS_RTC_STATUS_REG_POWER_UP 0x80 628#define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 7 629#define PALMAS_RTC_STATUS_REG_ALARM 0x40 630#define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 6 631#define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20 632#define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 5 633#define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10 634#define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 4 635#define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08 636#define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 3 637#define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04 638#define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 2 639#define PALMAS_RTC_STATUS_REG_RUN 0x02 640#define PALMAS_RTC_STATUS_REG_RUN_SHIFT 1 641 642/* Bit definitions for RTC_INTERRUPTS_REG */ 643#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10 644#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 4 645#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08 646#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 3 647#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04 648#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 2 649#define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03 650#define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0 651 652/* Bit definitions for RTC_COMP_LSB_REG */ 653#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xff 654#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0 655 656/* Bit definitions for RTC_COMP_MSB_REG */ 657#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xff 658#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0 659 660/* Bit definitions for RTC_RES_PROG_REG */ 661#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3f 662#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0 663 664/* Bit definitions for RTC_RESET_STATUS_REG */ 665#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01 666#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0 667 668/* Registers for function BACKUP */ 669#define PALMAS_BACKUP0 0x0 670#define PALMAS_BACKUP1 0x1 671#define PALMAS_BACKUP2 0x2 672#define PALMAS_BACKUP3 0x3 673#define PALMAS_BACKUP4 0x4 674#define PALMAS_BACKUP5 0x5 675#define PALMAS_BACKUP6 0x6 676#define PALMAS_BACKUP7 0x7 677 678/* Bit definitions for BACKUP0 */ 679#define PALMAS_BACKUP0_BACKUP_MASK 0xff 680#define PALMAS_BACKUP0_BACKUP_SHIFT 0 681 682/* Bit definitions for BACKUP1 */ 683#define PALMAS_BACKUP1_BACKUP_MASK 0xff 684#define PALMAS_BACKUP1_BACKUP_SHIFT 0 685 686/* Bit definitions for BACKUP2 */ 687#define PALMAS_BACKUP2_BACKUP_MASK 0xff 688#define PALMAS_BACKUP2_BACKUP_SHIFT 0 689 690/* Bit definitions for BACKUP3 */ 691#define PALMAS_BACKUP3_BACKUP_MASK 0xff 692#define PALMAS_BACKUP3_BACKUP_SHIFT 0 693 694/* Bit definitions for BACKUP4 */ 695#define PALMAS_BACKUP4_BACKUP_MASK 0xff 696#define PALMAS_BACKUP4_BACKUP_SHIFT 0 697 698/* Bit definitions for BACKUP5 */ 699#define PALMAS_BACKUP5_BACKUP_MASK 0xff 700#define PALMAS_BACKUP5_BACKUP_SHIFT 0 701 702/* Bit definitions for BACKUP6 */ 703#define PALMAS_BACKUP6_BACKUP_MASK 0xff 704#define PALMAS_BACKUP6_BACKUP_SHIFT 0 705 706/* Bit definitions for BACKUP7 */ 707#define PALMAS_BACKUP7_BACKUP_MASK 0xff 708#define PALMAS_BACKUP7_BACKUP_SHIFT 0 709 710/* Registers for function SMPS */ 711#define PALMAS_SMPS12_CTRL 0x0 712#define PALMAS_SMPS12_TSTEP 0x1 713#define PALMAS_SMPS12_FORCE 0x2 714#define PALMAS_SMPS12_VOLTAGE 0x3 715#define PALMAS_SMPS3_CTRL 0x4 716#define PALMAS_SMPS3_VOLTAGE 0x7 717#define PALMAS_SMPS45_CTRL 0x8 718#define PALMAS_SMPS45_TSTEP 0x9 719#define PALMAS_SMPS45_FORCE 0xA 720#define PALMAS_SMPS45_VOLTAGE 0xB 721#define PALMAS_SMPS6_CTRL 0xC 722#define PALMAS_SMPS6_TSTEP 0xD 723#define PALMAS_SMPS6_FORCE 0xE 724#define PALMAS_SMPS6_VOLTAGE 0xF 725#define PALMAS_SMPS7_CTRL 0x10 726#define PALMAS_SMPS7_VOLTAGE 0x13 727#define PALMAS_SMPS8_CTRL 0x14 728#define PALMAS_SMPS8_TSTEP 0x15 729#define PALMAS_SMPS8_FORCE 0x16 730#define PALMAS_SMPS8_VOLTAGE 0x17 731#define PALMAS_SMPS9_CTRL 0x18 732#define PALMAS_SMPS9_VOLTAGE 0x1B 733#define PALMAS_SMPS10_CTRL 0x1C 734#define PALMAS_SMPS10_STATUS 0x1F 735#define PALMAS_SMPS_CTRL 0x24 736#define PALMAS_SMPS_PD_CTRL 0x25 737#define PALMAS_SMPS_DITHER_EN 0x26 738#define PALMAS_SMPS_THERMAL_EN 0x27 739#define PALMAS_SMPS_THERMAL_STATUS 0x28 740#define PALMAS_SMPS_SHORT_STATUS 0x29 741#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A 742#define PALMAS_SMPS_POWERGOOD_MASK1 0x2B 743#define PALMAS_SMPS_POWERGOOD_MASK2 0x2C 744 745/* Bit definitions for SMPS12_CTRL */ 746#define PALMAS_SMPS12_CTRL_WR_S 0x80 747#define PALMAS_SMPS12_CTRL_WR_S_SHIFT 7 748#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40 749#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 6 750#define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30 751#define PALMAS_SMPS12_CTRL_STATUS_SHIFT 4 752#define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c 753#define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 2 754#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03 755#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0 756 757/* Bit definitions for SMPS12_TSTEP */ 758#define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03 759#define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0 760 761/* Bit definitions for SMPS12_FORCE */ 762#define PALMAS_SMPS12_FORCE_CMD 0x80 763#define PALMAS_SMPS12_FORCE_CMD_SHIFT 7 764#define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7f 765#define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0 766 767/* Bit definitions for SMPS12_VOLTAGE */ 768#define PALMAS_SMPS12_VOLTAGE_RANGE 0x80 769#define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 7 770#define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7f 771#define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0 772 773/* Bit definitions for SMPS3_CTRL */ 774#define PALMAS_SMPS3_CTRL_WR_S 0x80 775#define PALMAS_SMPS3_CTRL_WR_S_SHIFT 7 776#define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30 777#define PALMAS_SMPS3_CTRL_STATUS_SHIFT 4 778#define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c 779#define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 2 780#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03 781#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0 782 783/* Bit definitions for SMPS3_VOLTAGE */ 784#define PALMAS_SMPS3_VOLTAGE_RANGE 0x80 785#define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 7 786#define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7f 787#define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0 788 789/* Bit definitions for SMPS45_CTRL */ 790#define PALMAS_SMPS45_CTRL_WR_S 0x80 791#define PALMAS_SMPS45_CTRL_WR_S_SHIFT 7 792#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40 793#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 6 794#define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30 795#define PALMAS_SMPS45_CTRL_STATUS_SHIFT 4 796#define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c 797#define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 2 798#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03 799#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0 800 801/* Bit definitions for SMPS45_TSTEP */ 802#define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03 803#define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0 804 805/* Bit definitions for SMPS45_FORCE */ 806#define PALMAS_SMPS45_FORCE_CMD 0x80 807#define PALMAS_SMPS45_FORCE_CMD_SHIFT 7 808#define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7f 809#define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0 810 811/* Bit definitions for SMPS45_VOLTAGE */ 812#define PALMAS_SMPS45_VOLTAGE_RANGE 0x80 813#define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 7 814#define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7f 815#define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0 816 817/* Bit definitions for SMPS6_CTRL */ 818#define PALMAS_SMPS6_CTRL_WR_S 0x80 819#define PALMAS_SMPS6_CTRL_WR_S_SHIFT 7 820#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40 821#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 6 822#define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30 823#define PALMAS_SMPS6_CTRL_STATUS_SHIFT 4 824#define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c 825#define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 2 826#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03 827#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0 828 829/* Bit definitions for SMPS6_TSTEP */ 830#define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03 831#define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0 832 833/* Bit definitions for SMPS6_FORCE */ 834#define PALMAS_SMPS6_FORCE_CMD 0x80 835#define PALMAS_SMPS6_FORCE_CMD_SHIFT 7 836#define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7f 837#define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0 838 839/* Bit definitions for SMPS6_VOLTAGE */ 840#define PALMAS_SMPS6_VOLTAGE_RANGE 0x80 841#define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 7 842#define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7f 843#define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0 844 845/* Bit definitions for SMPS7_CTRL */ 846#define PALMAS_SMPS7_CTRL_WR_S 0x80 847#define PALMAS_SMPS7_CTRL_WR_S_SHIFT 7 848#define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30 849#define PALMAS_SMPS7_CTRL_STATUS_SHIFT 4 850#define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c 851#define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 2 852#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03 853#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0 854 855/* Bit definitions for SMPS7_VOLTAGE */ 856#define PALMAS_SMPS7_VOLTAGE_RANGE 0x80 857#define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 7 858#define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7f 859#define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0 860 861/* Bit definitions for SMPS8_CTRL */ 862#define PALMAS_SMPS8_CTRL_WR_S 0x80 863#define PALMAS_SMPS8_CTRL_WR_S_SHIFT 7 864#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40 865#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 6 866#define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30 867#define PALMAS_SMPS8_CTRL_STATUS_SHIFT 4 868#define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c 869#define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 2 870#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03 871#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0 872 873/* Bit definitions for SMPS8_TSTEP */ 874#define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03 875#define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0 876 877/* Bit definitions for SMPS8_FORCE */ 878#define PALMAS_SMPS8_FORCE_CMD 0x80 879#define PALMAS_SMPS8_FORCE_CMD_SHIFT 7 880#define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7f 881#define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0 882 883/* Bit definitions for SMPS8_VOLTAGE */ 884#define PALMAS_SMPS8_VOLTAGE_RANGE 0x80 885#define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 7 886#define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7f 887#define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0 888 889/* Bit definitions for SMPS9_CTRL */ 890#define PALMAS_SMPS9_CTRL_WR_S 0x80 891#define PALMAS_SMPS9_CTRL_WR_S_SHIFT 7 892#define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30 893#define PALMAS_SMPS9_CTRL_STATUS_SHIFT 4 894#define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c 895#define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 2 896#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03 897#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0 898 899/* Bit definitions for SMPS9_VOLTAGE */ 900#define PALMAS_SMPS9_VOLTAGE_RANGE 0x80 901#define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 7 902#define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7f 903#define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0 904 905/* Bit definitions for SMPS10_CTRL */ 906#define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0 907#define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 4 908#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0f 909#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0 910 911/* Bit definitions for SMPS10_STATUS */ 912#define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0f 913#define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0 914 915/* Bit definitions for SMPS_CTRL */ 916#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20 917#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 5 918#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10 919#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 4 920#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c 921#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 2 922#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03 923#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0 924 925/* Bit definitions for SMPS_PD_CTRL */ 926#define PALMAS_SMPS_PD_CTRL_SMPS9 0x40 927#define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 6 928#define PALMAS_SMPS_PD_CTRL_SMPS8 0x20 929#define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 5 930#define PALMAS_SMPS_PD_CTRL_SMPS7 0x10 931#define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 4 932#define PALMAS_SMPS_PD_CTRL_SMPS6 0x08 933#define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 3 934#define PALMAS_SMPS_PD_CTRL_SMPS45 0x04 935#define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 2 936#define PALMAS_SMPS_PD_CTRL_SMPS3 0x02 937#define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 1 938#define PALMAS_SMPS_PD_CTRL_SMPS12 0x01 939#define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0 940 941/* Bit definitions for SMPS_THERMAL_EN */ 942#define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40 943#define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 6 944#define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20 945#define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 5 946#define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08 947#define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 3 948#define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04 949#define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 2 950#define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01 951#define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0 952 953/* Bit definitions for SMPS_THERMAL_STATUS */ 954#define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40 955#define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 6 956#define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20 957#define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 5 958#define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08 959#define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 3 960#define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04 961#define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 2 962#define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01 963#define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0 964 965/* Bit definitions for SMPS_SHORT_STATUS */ 966#define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80 967#define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 7 968#define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40 969#define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 6 970#define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20 971#define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 5 972#define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10 973#define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 4 974#define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08 975#define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 3 976#define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04 977#define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 2 978#define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02 979#define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 1 980#define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01 981#define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0 982 983/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ 984#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40 985#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 6 986#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20 987#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 5 988#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10 989#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 4 990#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08 991#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 3 992#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04 993#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 2 994#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02 995#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 1 996#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01 997#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0 998 999/* Bit definitions for SMPS_POWERGOOD_MASK1 */ 1000#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80 1001#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 7 1002#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40 1003#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 6 1004#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20 1005#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 5 1006#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10 1007#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 4 1008#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08 1009#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 3 1010#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04 1011#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 2 1012#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02 1013#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 1 1014#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01 1015#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0 1016 1017/* Bit definitions for SMPS_POWERGOOD_MASK2 */ 1018#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80 1019#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7 1020#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04 1021#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 2 1022#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02 1023#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 1 1024#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01 1025#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0 1026 1027/* Registers for function LDO */ 1028#define PALMAS_LDO1_CTRL 0x0 1029#define PALMAS_LDO1_VOLTAGE 0x1 1030#define PALMAS_LDO2_CTRL 0x2 1031#define PALMAS_LDO2_VOLTAGE 0x3 1032#define PALMAS_LDO3_CTRL 0x4 1033#define PALMAS_LDO3_VOLTAGE 0x5 1034#define PALMAS_LDO4_CTRL 0x6 1035#define PALMAS_LDO4_VOLTAGE 0x7 1036#define PALMAS_LDO5_CTRL 0x8 1037#define PALMAS_LDO5_VOLTAGE 0x9 1038#define PALMAS_LDO6_CTRL 0xA 1039#define PALMAS_LDO6_VOLTAGE 0xB 1040#define PALMAS_LDO7_CTRL 0xC 1041#define PALMAS_LDO7_VOLTAGE 0xD 1042#define PALMAS_LDO8_CTRL 0xE 1043#define PALMAS_LDO8_VOLTAGE 0xF 1044#define PALMAS_LDO9_CTRL 0x10 1045#define PALMAS_LDO9_VOLTAGE 0x11 1046#define PALMAS_LDOLN_CTRL 0x12 1047#define PALMAS_LDOLN_VOLTAGE 0x13 1048#define PALMAS_LDOUSB_CTRL 0x14 1049#define PALMAS_LDOUSB_VOLTAGE 0x15 1050#define PALMAS_LDO_CTRL 0x1A 1051#define PALMAS_LDO_PD_CTRL1 0x1B 1052#define PALMAS_LDO_PD_CTRL2 0x1C 1053#define PALMAS_LDO_SHORT_STATUS1 0x1D 1054#define PALMAS_LDO_SHORT_STATUS2 0x1E 1055 1056/* Bit definitions for LDO1_CTRL */ 1057#define PALMAS_LDO1_CTRL_WR_S 0x80 1058#define PALMAS_LDO1_CTRL_WR_S_SHIFT 7 1059#define PALMAS_LDO1_CTRL_STATUS 0x10 1060#define PALMAS_LDO1_CTRL_STATUS_SHIFT 4 1061#define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04 1062#define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 2 1063#define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01 1064#define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0 1065 1066/* Bit definitions for LDO1_VOLTAGE */ 1067#define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3f 1068#define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0 1069 1070/* Bit definitions for LDO2_CTRL */ 1071#define PALMAS_LDO2_CTRL_WR_S 0x80 1072#define PALMAS_LDO2_CTRL_WR_S_SHIFT 7 1073#define PALMAS_LDO2_CTRL_STATUS 0x10 1074#define PALMAS_LDO2_CTRL_STATUS_SHIFT 4 1075#define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04 1076#define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 2 1077#define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01 1078#define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0 1079 1080/* Bit definitions for LDO2_VOLTAGE */ 1081#define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3f 1082#define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0 1083 1084/* Bit definitions for LDO3_CTRL */ 1085#define PALMAS_LDO3_CTRL_WR_S 0x80 1086#define PALMAS_LDO3_CTRL_WR_S_SHIFT 7 1087#define PALMAS_LDO3_CTRL_STATUS 0x10 1088#define PALMAS_LDO3_CTRL_STATUS_SHIFT 4 1089#define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04 1090#define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 2 1091#define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01 1092#define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0 1093 1094/* Bit definitions for LDO3_VOLTAGE */ 1095#define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3f 1096#define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0 1097 1098/* Bit definitions for LDO4_CTRL */ 1099#define PALMAS_LDO4_CTRL_WR_S 0x80 1100#define PALMAS_LDO4_CTRL_WR_S_SHIFT 7 1101#define PALMAS_LDO4_CTRL_STATUS 0x10 1102#define PALMAS_LDO4_CTRL_STATUS_SHIFT 4 1103#define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04 1104#define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 2 1105#define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01 1106#define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0 1107 1108/* Bit definitions for LDO4_VOLTAGE */ 1109#define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3f 1110#define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0 1111 1112/* Bit definitions for LDO5_CTRL */ 1113#define PALMAS_LDO5_CTRL_WR_S 0x80 1114#define PALMAS_LDO5_CTRL_WR_S_SHIFT 7 1115#define PALMAS_LDO5_CTRL_STATUS 0x10 1116#define PALMAS_LDO5_CTRL_STATUS_SHIFT 4 1117#define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04 1118#define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 2 1119#define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01 1120#define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0 1121 1122/* Bit definitions for LDO5_VOLTAGE */ 1123#define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3f 1124#define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0 1125 1126/* Bit definitions for LDO6_CTRL */ 1127#define PALMAS_LDO6_CTRL_WR_S 0x80 1128#define PALMAS_LDO6_CTRL_WR_S_SHIFT 7 1129#define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40 1130#define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 6 1131#define PALMAS_LDO6_CTRL_STATUS 0x10 1132#define PALMAS_LDO6_CTRL_STATUS_SHIFT 4 1133#define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04 1134#define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 2 1135#define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01 1136#define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0 1137 1138/* Bit definitions for LDO6_VOLTAGE */ 1139#define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3f 1140#define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0 1141 1142/* Bit definitions for LDO7_CTRL */ 1143#define PALMAS_LDO7_CTRL_WR_S 0x80 1144#define PALMAS_LDO7_CTRL_WR_S_SHIFT 7 1145#define PALMAS_LDO7_CTRL_STATUS 0x10 1146#define PALMAS_LDO7_CTRL_STATUS_SHIFT 4 1147#define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04 1148#define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 2 1149#define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01 1150#define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0 1151 1152/* Bit definitions for LDO7_VOLTAGE */ 1153#define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3f 1154#define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0 1155 1156/* Bit definitions for LDO8_CTRL */ 1157#define PALMAS_LDO8_CTRL_WR_S 0x80 1158#define PALMAS_LDO8_CTRL_WR_S_SHIFT 7 1159#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40 1160#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 6 1161#define PALMAS_LDO8_CTRL_STATUS 0x10 1162#define PALMAS_LDO8_CTRL_STATUS_SHIFT 4 1163#define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04 1164#define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 2 1165#define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01 1166#define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0 1167 1168/* Bit definitions for LDO8_VOLTAGE */ 1169#define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3f 1170#define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0 1171 1172/* Bit definitions for LDO9_CTRL */ 1173#define PALMAS_LDO9_CTRL_WR_S 0x80 1174#define PALMAS_LDO9_CTRL_WR_S_SHIFT 7 1175#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40 1176#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 6 1177#define PALMAS_LDO9_CTRL_STATUS 0x10 1178#define PALMAS_LDO9_CTRL_STATUS_SHIFT 4 1179#define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04 1180#define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 2 1181#define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01 1182#define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0 1183 1184/* Bit definitions for LDO9_VOLTAGE */ 1185#define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3f 1186#define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0 1187 1188/* Bit definitions for LDOLN_CTRL */ 1189#define PALMAS_LDOLN_CTRL_WR_S 0x80 1190#define PALMAS_LDOLN_CTRL_WR_S_SHIFT 7 1191#define PALMAS_LDOLN_CTRL_STATUS 0x10 1192#define PALMAS_LDOLN_CTRL_STATUS_SHIFT 4 1193#define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04 1194#define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 2 1195#define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01 1196#define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0 1197 1198/* Bit definitions for LDOLN_VOLTAGE */ 1199#define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3f 1200#define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0 1201 1202/* Bit definitions for LDOUSB_CTRL */ 1203#define PALMAS_LDOUSB_CTRL_WR_S 0x80 1204#define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 7 1205#define PALMAS_LDOUSB_CTRL_STATUS 0x10 1206#define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 4 1207#define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04 1208#define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 2 1209#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01 1210#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0 1211 1212/* Bit definitions for LDOUSB_VOLTAGE */ 1213#define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3f 1214#define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0 1215 1216/* Bit definitions for LDO_CTRL */ 1217#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01 1218#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0 1219 1220/* Bit definitions for LDO_PD_CTRL1 */ 1221#define PALMAS_LDO_PD_CTRL1_LDO8 0x80 1222#define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 7 1223#define PALMAS_LDO_PD_CTRL1_LDO7 0x40 1224#define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 6 1225#define PALMAS_LDO_PD_CTRL1_LDO6 0x20 1226#define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 5 1227#define PALMAS_LDO_PD_CTRL1_LDO5 0x10 1228#define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 4 1229#define PALMAS_LDO_PD_CTRL1_LDO4 0x08 1230#define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 3 1231#define PALMAS_LDO_PD_CTRL1_LDO3 0x04 1232#define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 2 1233#define PALMAS_LDO_PD_CTRL1_LDO2 0x02 1234#define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 1 1235#define PALMAS_LDO_PD_CTRL1_LDO1 0x01 1236#define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0 1237 1238/* Bit definitions for LDO_PD_CTRL2 */ 1239#define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04 1240#define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 2 1241#define PALMAS_LDO_PD_CTRL2_LDOLN 0x02 1242#define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 1 1243#define PALMAS_LDO_PD_CTRL2_LDO9 0x01 1244#define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0 1245 1246/* Bit definitions for LDO_SHORT_STATUS1 */ 1247#define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80 1248#define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 7 1249#define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40 1250#define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 6 1251#define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20 1252#define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 5 1253#define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10 1254#define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 4 1255#define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08 1256#define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 3 1257#define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04 1258#define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 2 1259#define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02 1260#define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 1 1261#define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01 1262#define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0 1263 1264/* Bit definitions for LDO_SHORT_STATUS2 */ 1265#define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08 1266#define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 3 1267#define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04 1268#define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 2 1269#define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02 1270#define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 1 1271#define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01 1272#define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0 1273 1274/* Registers for function PMU_CONTROL */ 1275#define PALMAS_DEV_CTRL 0x0 1276#define PALMAS_POWER_CTRL 0x1 1277#define PALMAS_VSYS_LO 0x2 1278#define PALMAS_VSYS_MON 0x3 1279#define PALMAS_VBAT_MON 0x4 1280#define PALMAS_WATCHDOG 0x5 1281#define PALMAS_BOOT_STATUS 0x6 1282#define PALMAS_BATTERY_BOUNCE 0x7 1283#define PALMAS_BACKUP_BATTERY_CTRL 0x8 1284#define PALMAS_LONG_PRESS_KEY 0x9 1285#define PALMAS_OSC_THERM_CTRL 0xA 1286#define PALMAS_BATDEBOUNCING 0xB 1287#define PALMAS_SWOFF_HWRST 0xF 1288#define PALMAS_SWOFF_COLDRST 0x10 1289#define PALMAS_SWOFF_STATUS 0x11 1290#define PALMAS_PMU_CONFIG 0x12 1291#define PALMAS_SPARE 0x14 1292#define PALMAS_PMU_SECONDARY_INT 0x15 1293#define PALMAS_SW_REVISION 0x17 1294#define PALMAS_EXT_CHRG_CTRL 0x18 1295#define PALMAS_PMU_SECONDARY_INT2 0x19 1296 1297/* Bit definitions for DEV_CTRL */ 1298#define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c 1299#define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 2 1300#define PALMAS_DEV_CTRL_SW_RST 0x02 1301#define PALMAS_DEV_CTRL_SW_RST_SHIFT 1 1302#define PALMAS_DEV_CTRL_DEV_ON 0x01 1303#define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0 1304 1305/* Bit definitions for POWER_CTRL */ 1306#define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04 1307#define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 2 1308#define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02 1309#define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 1 1310#define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01 1311#define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0 1312 1313/* Bit definitions for VSYS_LO */ 1314#define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1f 1315#define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0 1316 1317/* Bit definitions for VSYS_MON */ 1318#define PALMAS_VSYS_MON_ENABLE 0x80 1319#define PALMAS_VSYS_MON_ENABLE_SHIFT 7 1320#define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3f 1321#define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0 1322 1323/* Bit definitions for VBAT_MON */ 1324#define PALMAS_VBAT_MON_ENABLE 0x80 1325#define PALMAS_VBAT_MON_ENABLE_SHIFT 7 1326#define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3f 1327#define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0 1328 1329/* Bit definitions for WATCHDOG */ 1330#define PALMAS_WATCHDOG_LOCK 0x20 1331#define PALMAS_WATCHDOG_LOCK_SHIFT 5 1332#define PALMAS_WATCHDOG_ENABLE 0x10 1333#define PALMAS_WATCHDOG_ENABLE_SHIFT 4 1334#define PALMAS_WATCHDOG_MODE 0x08 1335#define PALMAS_WATCHDOG_MODE_SHIFT 3 1336#define PALMAS_WATCHDOG_TIMER_MASK 0x07 1337#define PALMAS_WATCHDOG_TIMER_SHIFT 0 1338 1339/* Bit definitions for BOOT_STATUS */ 1340#define PALMAS_BOOT_STATUS_BOOT1 0x02 1341#define PALMAS_BOOT_STATUS_BOOT1_SHIFT 1 1342#define PALMAS_BOOT_STATUS_BOOT0 0x01 1343#define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0 1344 1345/* Bit definitions for BATTERY_BOUNCE */ 1346#define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3f 1347#define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0 1348 1349/* Bit definitions for BACKUP_BATTERY_CTRL */ 1350#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80 1351#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 7 1352#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40 1353#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 6 1354#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20 1355#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 5 1356#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10 1357#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 4 1358#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08 1359#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 3 1360#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06 1361#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 1 1362#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01 1363#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0 1364 1365/* Bit definitions for LONG_PRESS_KEY */ 1366#define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80 1367#define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 7 1368#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10 1369#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 4 1370#define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c 1371#define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 2 1372#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03 1373#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0 1374 1375/* Bit definitions for OSC_THERM_CTRL */ 1376#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80 1377#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 7 1378#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40 1379#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 6 1380#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20 1381#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 5 1382#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10 1383#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 4 1384#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c 1385#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 2 1386#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02 1387#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 1 1388#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01 1389#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0 1390 1391/* Bit definitions for BATDEBOUNCING */ 1392#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80 1393#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 7 1394#define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78 1395#define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 3 1396#define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07 1397#define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0 1398 1399/* Bit definitions for SWOFF_HWRST */ 1400#define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80 1401#define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 7 1402#define PALMAS_SWOFF_HWRST_PWRDOWN 0x40 1403#define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 6 1404#define PALMAS_SWOFF_HWRST_WTD 0x20 1405#define PALMAS_SWOFF_HWRST_WTD_SHIFT 5 1406#define PALMAS_SWOFF_HWRST_TSHUT 0x10 1407#define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 4 1408#define PALMAS_SWOFF_HWRST_RESET_IN 0x08 1409#define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 3 1410#define PALMAS_SWOFF_HWRST_SW_RST 0x04 1411#define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 2 1412#define PALMAS_SWOFF_HWRST_VSYS_LO 0x02 1413#define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 1 1414#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01 1415#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0 1416 1417/* Bit definitions for SWOFF_COLDRST */ 1418#define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80 1419#define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 7 1420#define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40 1421#define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 6 1422#define PALMAS_SWOFF_COLDRST_WTD 0x20 1423#define PALMAS_SWOFF_COLDRST_WTD_SHIFT 5 1424#define PALMAS_SWOFF_COLDRST_TSHUT 0x10 1425#define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 4 1426#define PALMAS_SWOFF_COLDRST_RESET_IN 0x08 1427#define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 3 1428#define PALMAS_SWOFF_COLDRST_SW_RST 0x04 1429#define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 2 1430#define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02 1431#define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 1 1432#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01 1433#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0 1434 1435/* Bit definitions for SWOFF_STATUS */ 1436#define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80 1437#define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 7 1438#define PALMAS_SWOFF_STATUS_PWRDOWN 0x40 1439#define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 6 1440#define PALMAS_SWOFF_STATUS_WTD 0x20 1441#define PALMAS_SWOFF_STATUS_WTD_SHIFT 5 1442#define PALMAS_SWOFF_STATUS_TSHUT 0x10 1443#define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 4 1444#define PALMAS_SWOFF_STATUS_RESET_IN 0x08 1445#define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 3 1446#define PALMAS_SWOFF_STATUS_SW_RST 0x04 1447#define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 2 1448#define PALMAS_SWOFF_STATUS_VSYS_LO 0x02 1449#define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 1 1450#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01 1451#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0 1452 1453/* Bit definitions for PMU_CONFIG */ 1454#define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40 1455#define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 6 1456#define PALMAS_PMU_CONFIG_SPARE_MASK 0x30 1457#define PALMAS_PMU_CONFIG_SPARE_SHIFT 4 1458#define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c 1459#define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 2 1460#define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02 1461#define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 1 1462#define PALMAS_PMU_CONFIG_AUTODEVON 0x01 1463#define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0 1464 1465/* Bit definitions for SPARE */ 1466#define PALMAS_SPARE_SPARE_MASK 0xf8 1467#define PALMAS_SPARE_SPARE_SHIFT 3 1468#define PALMAS_SPARE_REGEN3_OD 0x04 1469#define PALMAS_SPARE_REGEN3_OD_SHIFT 2 1470#define PALMAS_SPARE_REGEN2_OD 0x02 1471#define PALMAS_SPARE_REGEN2_OD_SHIFT 1 1472#define PALMAS_SPARE_REGEN1_OD 0x01 1473#define PALMAS_SPARE_REGEN1_OD_SHIFT 0 1474 1475/* Bit definitions for PMU_SECONDARY_INT */ 1476#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80 1477#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 7 1478#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40 1479#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 6 1480#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20 1481#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 5 1482#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10 1483#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 4 1484#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08 1485#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 3 1486#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04 1487#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 2 1488#define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02 1489#define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 1 1490#define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01 1491#define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0 1492 1493/* Bit definitions for SW_REVISION */ 1494#define PALMAS_SW_REVISION_SW_REVISION_MASK 0xff 1495#define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0 1496 1497/* Bit definitions for EXT_CHRG_CTRL */ 1498#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80 1499#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 7 1500#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40 1501#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 6 1502#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08 1503#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 3 1504#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04 1505#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 2 1506#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02 1507#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 1 1508#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01 1509#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0 1510 1511/* Bit definitions for PMU_SECONDARY_INT2 */ 1512#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20 1513#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 5 1514#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10 1515#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 4 1516#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02 1517#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 1 1518#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01 1519#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0 1520 1521/* Registers for function RESOURCE */ 1522#define PALMAS_CLK32KG_CTRL 0x0 1523#define PALMAS_CLK32KGAUDIO_CTRL 0x1 1524#define PALMAS_REGEN1_CTRL 0x2 1525#define PALMAS_REGEN2_CTRL 0x3 1526#define PALMAS_SYSEN1_CTRL 0x4 1527#define PALMAS_SYSEN2_CTRL 0x5 1528#define PALMAS_NSLEEP_RES_ASSIGN 0x6 1529#define PALMAS_NSLEEP_SMPS_ASSIGN 0x7 1530#define PALMAS_NSLEEP_LDO_ASSIGN1 0x8 1531#define PALMAS_NSLEEP_LDO_ASSIGN2 0x9 1532#define PALMAS_ENABLE1_RES_ASSIGN 0xA 1533#define PALMAS_ENABLE1_SMPS_ASSIGN 0xB 1534#define PALMAS_ENABLE1_LDO_ASSIGN1 0xC 1535#define PALMAS_ENABLE1_LDO_ASSIGN2 0xD 1536#define PALMAS_ENABLE2_RES_ASSIGN 0xE 1537#define PALMAS_ENABLE2_SMPS_ASSIGN 0xF 1538#define PALMAS_ENABLE2_LDO_ASSIGN1 0x10 1539#define PALMAS_ENABLE2_LDO_ASSIGN2 0x11 1540#define PALMAS_REGEN3_CTRL 0x12 1541 1542/* Bit definitions for CLK32KG_CTRL */ 1543#define PALMAS_CLK32KG_CTRL_STATUS 0x10 1544#define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 4 1545#define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04 1546#define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 2 1547#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01 1548#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0 1549 1550/* Bit definitions for CLK32KGAUDIO_CTRL */ 1551#define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10 1552#define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 4 1553#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08 1554#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 3 1555#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04 1556#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 2 1557#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01 1558#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0 1559 1560/* Bit definitions for REGEN1_CTRL */ 1561#define PALMAS_REGEN1_CTRL_STATUS 0x10 1562#define PALMAS_REGEN1_CTRL_STATUS_SHIFT 4 1563#define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04 1564#define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 2 1565#define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01 1566#define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0 1567 1568/* Bit definitions for REGEN2_CTRL */ 1569#define PALMAS_REGEN2_CTRL_STATUS 0x10 1570#define PALMAS_REGEN2_CTRL_STATUS_SHIFT 4 1571#define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04 1572#define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 2 1573#define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01 1574#define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0 1575 1576/* Bit definitions for SYSEN1_CTRL */ 1577#define PALMAS_SYSEN1_CTRL_STATUS 0x10 1578#define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 4 1579#define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04 1580#define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 2 1581#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01 1582#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0 1583 1584/* Bit definitions for SYSEN2_CTRL */ 1585#define PALMAS_SYSEN2_CTRL_STATUS 0x10 1586#define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 4 1587#define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04 1588#define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 2 1589#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01 1590#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0 1591 1592/* Bit definitions for NSLEEP_RES_ASSIGN */ 1593#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40 1594#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 6 1595#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20 1596#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 1597#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10 1598#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 4 1599#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08 1600#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 3 1601#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04 1602#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 2 1603#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02 1604#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 1 1605#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01 1606#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0 1607 1608/* Bit definitions for NSLEEP_SMPS_ASSIGN */ 1609#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80 1610#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 7 1611#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40 1612#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 6 1613#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20 1614#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 5 1615#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10 1616#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 4 1617#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08 1618#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 3 1619#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04 1620#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 2 1621#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02 1622#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 1 1623#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01 1624#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0 1625 1626/* Bit definitions for NSLEEP_LDO_ASSIGN1 */ 1627#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80 1628#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 7 1629#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40 1630#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 6 1631#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20 1632#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 5 1633#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10 1634#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 4 1635#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08 1636#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 3 1637#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04 1638#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 2 1639#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02 1640#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 1 1641#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01 1642#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0 1643 1644/* Bit definitions for NSLEEP_LDO_ASSIGN2 */ 1645#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04 1646#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 2 1647#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02 1648#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 1 1649#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01 1650#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0 1651 1652/* Bit definitions for ENABLE1_RES_ASSIGN */ 1653#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40 1654#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 6 1655#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20 1656#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 1657#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10 1658#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 4 1659#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08 1660#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 3 1661#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04 1662#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 2 1663#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02 1664#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 1 1665#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01 1666#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0 1667 1668/* Bit definitions for ENABLE1_SMPS_ASSIGN */ 1669#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80 1670#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 7 1671#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40 1672#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 6 1673#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20 1674#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 5 1675#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10 1676#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 4 1677#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08 1678#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 3 1679#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04 1680#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 2 1681#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02 1682#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 1 1683#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01 1684#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0 1685 1686/* Bit definitions for ENABLE1_LDO_ASSIGN1 */ 1687#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80 1688#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 7 1689#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40 1690#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 6 1691#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20 1692#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 5 1693#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10 1694#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 4 1695#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08 1696#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 3 1697#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04 1698#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 2 1699#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02 1700#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 1 1701#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01 1702#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0 1703 1704/* Bit definitions for ENABLE1_LDO_ASSIGN2 */ 1705#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04 1706#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 2 1707#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02 1708#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 1 1709#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01 1710#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0 1711 1712/* Bit definitions for ENABLE2_RES_ASSIGN */ 1713#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40 1714#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 6 1715#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20 1716#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 1717#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10 1718#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 4 1719#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08 1720#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 3 1721#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04 1722#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 2 1723#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02 1724#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 1 1725#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01 1726#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0 1727 1728/* Bit definitions for ENABLE2_SMPS_ASSIGN */ 1729#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80 1730#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 7 1731#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40 1732#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 6 1733#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20 1734#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 5 1735#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10 1736#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 4 1737#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08 1738#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 3 1739#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04 1740#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 2 1741#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02 1742#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 1 1743#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01 1744#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0 1745 1746/* Bit definitions for ENABLE2_LDO_ASSIGN1 */ 1747#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80 1748#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 7 1749#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40 1750#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 6 1751#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20 1752#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 5 1753#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10 1754#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 4 1755#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08 1756#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 3 1757#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04 1758#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 2 1759#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02 1760#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 1 1761#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01 1762#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0 1763 1764/* Bit definitions for ENABLE2_LDO_ASSIGN2 */ 1765#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04 1766#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 2 1767#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02 1768#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 1 1769#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01 1770#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0 1771 1772/* Bit definitions for REGEN3_CTRL */ 1773#define PALMAS_REGEN3_CTRL_STATUS 0x10 1774#define PALMAS_REGEN3_CTRL_STATUS_SHIFT 4 1775#define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04 1776#define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 2 1777#define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01 1778#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0 1779 1780/* Registers for function PAD_CONTROL */ 1781#define PALMAS_OD_OUTPUT_CTRL2 0x2 1782#define PALMAS_POLARITY_CTRL2 0x3 1783#define PALMAS_PU_PD_INPUT_CTRL1 0x4 1784#define PALMAS_PU_PD_INPUT_CTRL2 0x5 1785#define PALMAS_PU_PD_INPUT_CTRL3 0x6 1786#define PALMAS_PU_PD_INPUT_CTRL5 0x7 1787#define PALMAS_OD_OUTPUT_CTRL 0x8 1788#define PALMAS_POLARITY_CTRL 0x9 1789#define PALMAS_PRIMARY_SECONDARY_PAD1 0xA 1790#define PALMAS_PRIMARY_SECONDARY_PAD2 0xB 1791#define PALMAS_I2C_SPI 0xC 1792#define PALMAS_PU_PD_INPUT_CTRL4 0xD 1793#define PALMAS_PRIMARY_SECONDARY_PAD3 0xE 1794#define PALMAS_PRIMARY_SECONDARY_PAD4 0xF 1795 1796/* Bit definitions for PU_PD_INPUT_CTRL1 */ 1797#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40 1798#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 6 1799#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20 1800#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 5 1801#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10 1802#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 4 1803#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04 1804#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 2 1805#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02 1806#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 1 1807 1808/* Bit definitions for PU_PD_INPUT_CTRL2 */ 1809#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20 1810#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 5 1811#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10 1812#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 4 1813#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08 1814#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 3 1815#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04 1816#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 2 1817#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02 1818#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 1 1819#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01 1820#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0 1821 1822/* Bit definitions for PU_PD_INPUT_CTRL3 */ 1823#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40 1824#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 6 1825#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10 1826#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 4 1827#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04 1828#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 2 1829#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01 1830#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0 1831 1832/* Bit definitions for OD_OUTPUT_CTRL */ 1833#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80 1834#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 7 1835#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40 1836#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 6 1837#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20 1838#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 5 1839#define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08 1840#define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 3 1841 1842/* Bit definitions for POLARITY_CTRL */ 1843#define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80 1844#define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 7 1845#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40 1846#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 6 1847#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20 1848#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 5 1849#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10 1850#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 4 1851#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08 1852#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 3 1853#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04 1854#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 2 1855#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02 1856#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 1 1857#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01 1858#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0 1859 1860/* Bit definitions for PRIMARY_SECONDARY_PAD1 */ 1861#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80 1862#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 7 1863#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60 1864#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 5 1865#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18 1866#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 3 1867#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04 1868#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 2 1869#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02 1870#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 1 1871#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01 1872#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0 1873 1874/* Bit definitions for PRIMARY_SECONDARY_PAD2 */ 1875#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30 1876#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 4 1877#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08 1878#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 3 1879#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06 1880#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 1 1881#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01 1882#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0 1883 1884/* Bit definitions for I2C_SPI */ 1885#define PALMAS_I2C_SPI_I2C2OTP_EN 0x80 1886#define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 7 1887#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40 1888#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 6 1889#define PALMAS_I2C_SPI_ID_I2C2 0x20 1890#define PALMAS_I2C_SPI_ID_I2C2_SHIFT 5 1891#define PALMAS_I2C_SPI_I2C_SPI 0x10 1892#define PALMAS_I2C_SPI_I2C_SPI_SHIFT 4 1893#define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0f 1894#define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0 1895 1896/* Bit definitions for PU_PD_INPUT_CTRL4 */ 1897#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40 1898#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 6 1899#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10 1900#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 4 1901#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04 1902#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 2 1903#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01 1904#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0 1905 1906/* Bit definitions for PRIMARY_SECONDARY_PAD3 */ 1907#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02 1908#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 1 1909#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01 1910#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0 1911 1912/* Registers for function LED_PWM */ 1913#define PALMAS_LED_PERIOD_CTRL 0x0 1914#define PALMAS_LED_CTRL 0x1 1915#define PALMAS_PWM_CTRL1 0x2 1916#define PALMAS_PWM_CTRL2 0x3 1917 1918/* Bit definitions for LED_PERIOD_CTRL */ 1919#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38 1920#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 3 1921#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07 1922#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0 1923 1924/* Bit definitions for LED_CTRL */ 1925#define PALMAS_LED_CTRL_LED_2_SEQ 0x20 1926#define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 5 1927#define PALMAS_LED_CTRL_LED_1_SEQ 0x10 1928#define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 4 1929#define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c 1930#define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 2 1931#define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03 1932#define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0 1933 1934/* Bit definitions for PWM_CTRL1 */ 1935#define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02 1936#define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 1 1937#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01 1938#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0 1939 1940/* Bit definitions for PWM_CTRL2 */ 1941#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xff 1942#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0 1943 1944/* Registers for function INTERRUPT */ 1945#define PALMAS_INT1_STATUS 0x0 1946#define PALMAS_INT1_MASK 0x1 1947#define PALMAS_INT1_LINE_STATE 0x2 1948#define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x3 1949#define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x4 1950#define PALMAS_INT2_STATUS 0x5 1951#define PALMAS_INT2_MASK 0x6 1952#define PALMAS_INT2_LINE_STATE 0x7 1953#define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x8 1954#define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x9 1955#define PALMAS_INT3_STATUS 0xA 1956#define PALMAS_INT3_MASK 0xB 1957#define PALMAS_INT3_LINE_STATE 0xC 1958#define PALMAS_INT3_EDGE_DETECT1_RESERVED 0xD 1959#define PALMAS_INT3_EDGE_DETECT2_RESERVED 0xE 1960#define PALMAS_INT4_STATUS 0xF 1961#define PALMAS_INT4_MASK 0x10 1962#define PALMAS_INT4_LINE_STATE 0x11 1963#define PALMAS_INT4_EDGE_DETECT1 0x12 1964#define PALMAS_INT4_EDGE_DETECT2 0x13 1965#define PALMAS_INT_CTRL 0x14 1966 1967/* Bit definitions for INT1_STATUS */ 1968#define PALMAS_INT1_STATUS_VBAT_MON 0x80 1969#define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 7 1970#define PALMAS_INT1_STATUS_VSYS_MON 0x40 1971#define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 6 1972#define PALMAS_INT1_STATUS_HOTDIE 0x20 1973#define PALMAS_INT1_STATUS_HOTDIE_SHIFT 5 1974#define PALMAS_INT1_STATUS_PWRDOWN 0x10 1975#define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 4 1976#define PALMAS_INT1_STATUS_RPWRON 0x08 1977#define PALMAS_INT1_STATUS_RPWRON_SHIFT 3 1978#define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04 1979#define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 2 1980#define PALMAS_INT1_STATUS_PWRON 0x02 1981#define PALMAS_INT1_STATUS_PWRON_SHIFT 1 1982#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01 1983#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0 1984 1985/* Bit definitions for INT1_MASK */ 1986#define PALMAS_INT1_MASK_VBAT_MON 0x80 1987#define PALMAS_INT1_MASK_VBAT_MON_SHIFT 7 1988#define PALMAS_INT1_MASK_VSYS_MON 0x40 1989#define PALMAS_INT1_MASK_VSYS_MON_SHIFT 6 1990#define PALMAS_INT1_MASK_HOTDIE 0x20 1991#define PALMAS_INT1_MASK_HOTDIE_SHIFT 5 1992#define PALMAS_INT1_MASK_PWRDOWN 0x10 1993#define PALMAS_INT1_MASK_PWRDOWN_SHIFT 4 1994#define PALMAS_INT1_MASK_RPWRON 0x08 1995#define PALMAS_INT1_MASK_RPWRON_SHIFT 3 1996#define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04 1997#define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 2 1998#define PALMAS_INT1_MASK_PWRON 0x02 1999#define PALMAS_INT1_MASK_PWRON_SHIFT 1 2000#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01 2001#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0 2002 2003/* Bit definitions for INT1_LINE_STATE */ 2004#define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80 2005#define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 7 2006#define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40 2007#define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 6 2008#define PALMAS_INT1_LINE_STATE_HOTDIE 0x20 2009#define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 5 2010#define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10 2011#define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 4 2012#define PALMAS_INT1_LINE_STATE_RPWRON 0x08 2013#define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 3 2014#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04 2015#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 2 2016#define PALMAS_INT1_LINE_STATE_PWRON 0x02 2017#define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 1 2018#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01 2019#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0 2020 2021/* Bit definitions for INT2_STATUS */ 2022#define PALMAS_INT2_STATUS_VAC_ACOK 0x80 2023#define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 7 2024#define PALMAS_INT2_STATUS_SHORT 0x40 2025#define PALMAS_INT2_STATUS_SHORT_SHIFT 6 2026#define PALMAS_INT2_STATUS_FBI_BB 0x20 2027#define PALMAS_INT2_STATUS_FBI_BB_SHIFT 5 2028#define PALMAS_INT2_STATUS_RESET_IN 0x10 2029#define PALMAS_INT2_STATUS_RESET_IN_SHIFT 4 2030#define PALMAS_INT2_STATUS_BATREMOVAL 0x08 2031#define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 3 2032#define PALMAS_INT2_STATUS_WDT 0x04 2033#define PALMAS_INT2_STATUS_WDT_SHIFT 2 2034#define PALMAS_INT2_STATUS_RTC_TIMER 0x02 2035#define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 1 2036#define PALMAS_INT2_STATUS_RTC_ALARM 0x01 2037#define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0 2038 2039/* Bit definitions for INT2_MASK */ 2040#define PALMAS_INT2_MASK_VAC_ACOK 0x80 2041#define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 7 2042#define PALMAS_INT2_MASK_SHORT 0x40 2043#define PALMAS_INT2_MASK_SHORT_SHIFT 6 2044#define PALMAS_INT2_MASK_FBI_BB 0x20 2045#define PALMAS_INT2_MASK_FBI_BB_SHIFT 5 2046#define PALMAS_INT2_MASK_RESET_IN 0x10 2047#define PALMAS_INT2_MASK_RESET_IN_SHIFT 4 2048#define PALMAS_INT2_MASK_BATREMOVAL 0x08 2049#define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 3 2050#define PALMAS_INT2_MASK_WDT 0x04 2051#define PALMAS_INT2_MASK_WDT_SHIFT 2 2052#define PALMAS_INT2_MASK_RTC_TIMER 0x02 2053#define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 1 2054#define PALMAS_INT2_MASK_RTC_ALARM 0x01 2055#define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0 2056 2057/* Bit definitions for INT2_LINE_STATE */ 2058#define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80 2059#define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 7 2060#define PALMAS_INT2_LINE_STATE_SHORT 0x40 2061#define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 6 2062#define PALMAS_INT2_LINE_STATE_FBI_BB 0x20 2063#define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 5 2064#define PALMAS_INT2_LINE_STATE_RESET_IN 0x10 2065#define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 4 2066#define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08 2067#define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 3 2068#define PALMAS_INT2_LINE_STATE_WDT 0x04 2069#define PALMAS_INT2_LINE_STATE_WDT_SHIFT 2 2070#define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02 2071#define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 1 2072#define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01 2073#define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0 2074 2075/* Bit definitions for INT3_STATUS */ 2076#define PALMAS_INT3_STATUS_VBUS 0x80 2077#define PALMAS_INT3_STATUS_VBUS_SHIFT 7 2078#define PALMAS_INT3_STATUS_VBUS_OTG 0x40 2079#define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 6 2080#define PALMAS_INT3_STATUS_ID 0x20 2081#define PALMAS_INT3_STATUS_ID_SHIFT 5 2082#define PALMAS_INT3_STATUS_ID_OTG 0x10 2083#define PALMAS_INT3_STATUS_ID_OTG_SHIFT 4 2084#define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08 2085#define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 3 2086#define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04 2087#define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 2 2088#define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02 2089#define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 1 2090#define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01 2091#define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0 2092 2093/* Bit definitions for INT3_MASK */ 2094#define PALMAS_INT3_MASK_VBUS 0x80 2095#define PALMAS_INT3_MASK_VBUS_SHIFT 7 2096#define PALMAS_INT3_MASK_VBUS_OTG 0x40 2097#define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 6 2098#define PALMAS_INT3_MASK_ID 0x20 2099#define PALMAS_INT3_MASK_ID_SHIFT 5 2100#define PALMAS_INT3_MASK_ID_OTG 0x10 2101#define PALMAS_INT3_MASK_ID_OTG_SHIFT 4 2102#define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08 2103#define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 3 2104#define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04 2105#define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 2 2106#define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02 2107#define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 1 2108#define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01 2109#define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0 2110 2111/* Bit definitions for INT3_LINE_STATE */ 2112#define PALMAS_INT3_LINE_STATE_VBUS 0x80 2113#define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 7 2114#define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40 2115#define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 6 2116#define PALMAS_INT3_LINE_STATE_ID 0x20 2117#define PALMAS_INT3_LINE_STATE_ID_SHIFT 5 2118#define PALMAS_INT3_LINE_STATE_ID_OTG 0x10 2119#define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 4 2120#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08 2121#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 3 2122#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04 2123#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 2 2124#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02 2125#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 1 2126#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01 2127#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0 2128 2129/* Bit definitions for INT4_STATUS */ 2130#define PALMAS_INT4_STATUS_GPIO_7 0x80 2131#define PALMAS_INT4_STATUS_GPIO_7_SHIFT 7 2132#define PALMAS_INT4_STATUS_GPIO_6 0x40 2133#define PALMAS_INT4_STATUS_GPIO_6_SHIFT 6 2134#define PALMAS_INT4_STATUS_GPIO_5 0x20 2135#define PALMAS_INT4_STATUS_GPIO_5_SHIFT 5 2136#define PALMAS_INT4_STATUS_GPIO_4 0x10 2137#define PALMAS_INT4_STATUS_GPIO_4_SHIFT 4 2138#define PALMAS_INT4_STATUS_GPIO_3 0x08 2139#define PALMAS_INT4_STATUS_GPIO_3_SHIFT 3 2140#define PALMAS_INT4_STATUS_GPIO_2 0x04 2141#define PALMAS_INT4_STATUS_GPIO_2_SHIFT 2 2142#define PALMAS_INT4_STATUS_GPIO_1 0x02 2143#define PALMAS_INT4_STATUS_GPIO_1_SHIFT 1 2144#define PALMAS_INT4_STATUS_GPIO_0 0x01 2145#define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0 2146 2147/* Bit definitions for INT4_MASK */ 2148#define PALMAS_INT4_MASK_GPIO_7 0x80 2149#define PALMAS_INT4_MASK_GPIO_7_SHIFT 7 2150#define PALMAS_INT4_MASK_GPIO_6 0x40 2151#define PALMAS_INT4_MASK_GPIO_6_SHIFT 6 2152#define PALMAS_INT4_MASK_GPIO_5 0x20 2153#define PALMAS_INT4_MASK_GPIO_5_SHIFT 5 2154#define PALMAS_INT4_MASK_GPIO_4 0x10 2155#define PALMAS_INT4_MASK_GPIO_4_SHIFT 4 2156#define PALMAS_INT4_MASK_GPIO_3 0x08 2157#define PALMAS_INT4_MASK_GPIO_3_SHIFT 3 2158#define PALMAS_INT4_MASK_GPIO_2 0x04 2159#define PALMAS_INT4_MASK_GPIO_2_SHIFT 2 2160#define PALMAS_INT4_MASK_GPIO_1 0x02 2161#define PALMAS_INT4_MASK_GPIO_1_SHIFT 1 2162#define PALMAS_INT4_MASK_GPIO_0 0x01 2163#define PALMAS_INT4_MASK_GPIO_0_SHIFT 0 2164 2165/* Bit definitions for INT4_LINE_STATE */ 2166#define PALMAS_INT4_LINE_STATE_GPIO_7 0x80 2167#define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 7 2168#define PALMAS_INT4_LINE_STATE_GPIO_6 0x40 2169#define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 6 2170#define PALMAS_INT4_LINE_STATE_GPIO_5 0x20 2171#define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 5 2172#define PALMAS_INT4_LINE_STATE_GPIO_4 0x10 2173#define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 4 2174#define PALMAS_INT4_LINE_STATE_GPIO_3 0x08 2175#define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 3 2176#define PALMAS_INT4_LINE_STATE_GPIO_2 0x04 2177#define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 2 2178#define PALMAS_INT4_LINE_STATE_GPIO_1 0x02 2179#define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 1 2180#define PALMAS_INT4_LINE_STATE_GPIO_0 0x01 2181#define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0 2182 2183/* Bit definitions for INT4_EDGE_DETECT1 */ 2184#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80 2185#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 7 2186#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40 2187#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 6 2188#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20 2189#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 5 2190#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10 2191#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 4 2192#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08 2193#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 3 2194#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04 2195#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 2 2196#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02 2197#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 1 2198#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01 2199#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0 2200 2201/* Bit definitions for INT4_EDGE_DETECT2 */ 2202#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80 2203#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 7 2204#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40 2205#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 6 2206#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20 2207#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 5 2208#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10 2209#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 4 2210#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08 2211#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 3 2212#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04 2213#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 2 2214#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02 2215#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 1 2216#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01 2217#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0 2218 2219/* Bit definitions for INT_CTRL */ 2220#define PALMAS_INT_CTRL_INT_PENDING 0x04 2221#define PALMAS_INT_CTRL_INT_PENDING_SHIFT 2 2222#define PALMAS_INT_CTRL_INT_CLEAR 0x01 2223#define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0 2224 2225/* Registers for function USB_OTG */ 2226#define PALMAS_USB_WAKEUP 0x3 2227#define PALMAS_USB_VBUS_CTRL_SET 0x4 2228#define PALMAS_USB_VBUS_CTRL_CLR 0x5 2229#define PALMAS_USB_ID_CTRL_SET 0x6 2230#define PALMAS_USB_ID_CTRL_CLEAR 0x7 2231#define PALMAS_USB_VBUS_INT_SRC 0x8 2232#define PALMAS_USB_VBUS_INT_LATCH_SET 0x9 2233#define PALMAS_USB_VBUS_INT_LATCH_CLR 0xA 2234#define PALMAS_USB_VBUS_INT_EN_LO_SET 0xB 2235#define PALMAS_USB_VBUS_INT_EN_LO_CLR 0xC 2236#define PALMAS_USB_VBUS_INT_EN_HI_SET 0xD 2237#define PALMAS_USB_VBUS_INT_EN_HI_CLR 0xE 2238#define PALMAS_USB_ID_INT_SRC 0xF 2239#define PALMAS_USB_ID_INT_LATCH_SET 0x10 2240#define PALMAS_USB_ID_INT_LATCH_CLR 0x11 2241#define PALMAS_USB_ID_INT_EN_LO_SET 0x12 2242#define PALMAS_USB_ID_INT_EN_LO_CLR 0x13 2243#define PALMAS_USB_ID_INT_EN_HI_SET 0x14 2244#define PALMAS_USB_ID_INT_EN_HI_CLR 0x15 2245#define PALMAS_USB_OTG_ADP_CTRL 0x16 2246#define PALMAS_USB_OTG_ADP_HIGH 0x17 2247#define PALMAS_USB_OTG_ADP_LOW 0x18 2248#define PALMAS_USB_OTG_ADP_RISE 0x19 2249#define PALMAS_USB_OTG_REVISION 0x1A 2250 2251/* Bit definitions for USB_WAKEUP */ 2252#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01 2253#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0 2254 2255/* Bit definitions for USB_VBUS_CTRL_SET */ 2256#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80 2257#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 7 2258#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20 2259#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 5 2260#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10 2261#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 4 2262#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08 2263#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 3 2264#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04 2265#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 2 2266 2267/* Bit definitions for USB_VBUS_CTRL_CLR */ 2268#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80 2269#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 7 2270#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20 2271#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 5 2272#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10 2273#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 4 2274#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08 2275#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 3 2276#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04 2277#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 2 2278 2279/* Bit definitions for USB_ID_CTRL_SET */ 2280#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80 2281#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 7 2282#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40 2283#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 6 2284#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20 2285#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 5 2286#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10 2287#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 4 2288#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08 2289#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 3 2290#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04 2291#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 2 2292 2293/* Bit definitions for USB_ID_CTRL_CLEAR */ 2294#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80 2295#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 7 2296#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40 2297#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 6 2298#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20 2299#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 5 2300#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10 2301#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 4 2302#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08 2303#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 3 2304#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04 2305#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 2 2306 2307/* Bit definitions for USB_VBUS_INT_SRC */ 2308#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80 2309#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 7 2310#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40 2311#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 6 2312#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20 2313#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 5 2314#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08 2315#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 3 2316#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04 2317#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 2 2318#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02 2319#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 1 2320#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01 2321#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0 2322 2323/* Bit definitions for USB_VBUS_INT_LATCH_SET */ 2324#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80 2325#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 7 2326#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40 2327#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 6 2328#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20 2329#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 5 2330#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10 2331#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 4 2332#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08 2333#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 3 2334#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04 2335#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 2 2336#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02 2337#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 1 2338#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01 2339#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0 2340 2341/* Bit definitions for USB_VBUS_INT_LATCH_CLR */ 2342#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80 2343#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 7 2344#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40 2345#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 6 2346#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20 2347#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 5 2348#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10 2349#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 4 2350#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08 2351#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 3 2352#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04 2353#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 2 2354#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02 2355#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 1 2356#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01 2357#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0 2358 2359/* Bit definitions for USB_VBUS_INT_EN_LO_SET */ 2360#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80 2361#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 7 2362#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40 2363#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 6 2364#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20 2365#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 5 2366#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08 2367#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 3 2368#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04 2369#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 2 2370#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02 2371#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 1 2372#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01 2373#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0 2374 2375/* Bit definitions for USB_VBUS_INT_EN_LO_CLR */ 2376#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80 2377#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 7 2378#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40 2379#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 6 2380#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20 2381#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 5 2382#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08 2383#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 3 2384#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04 2385#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 2 2386#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02 2387#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 1 2388#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01 2389#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0 2390 2391/* Bit definitions for USB_VBUS_INT_EN_HI_SET */ 2392#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80 2393#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 7 2394#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40 2395#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 6 2396#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20 2397#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 5 2398#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10 2399#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 4 2400#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08 2401#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 3 2402#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04 2403#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 2 2404#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02 2405#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 1 2406#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01 2407#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0 2408 2409/* Bit definitions for USB_VBUS_INT_EN_HI_CLR */ 2410#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80 2411#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 7 2412#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40 2413#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 6 2414#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20 2415#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 5 2416#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10 2417#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 4 2418#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08 2419#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 3 2420#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04 2421#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 2 2422#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02 2423#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 1 2424#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01 2425#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0 2426 2427/* Bit definitions for USB_ID_INT_SRC */ 2428#define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10 2429#define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 4 2430#define PALMAS_USB_ID_INT_SRC_ID_A 0x08 2431#define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 3 2432#define PALMAS_USB_ID_INT_SRC_ID_B 0x04 2433#define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 2 2434#define PALMAS_USB_ID_INT_SRC_ID_C 0x02 2435#define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 1 2436#define PALMAS_USB_ID_INT_SRC_ID_GND 0x01 2437#define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0 2438 2439/* Bit definitions for USB_ID_INT_LATCH_SET */ 2440#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10 2441#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 4 2442#define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08 2443#define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 3 2444#define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04 2445#define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 2 2446#define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02 2447#define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 1 2448#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01 2449#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0 2450 2451/* Bit definitions for USB_ID_INT_LATCH_CLR */ 2452#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10 2453#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 4 2454#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08 2455#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 3 2456#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04 2457#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 2 2458#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02 2459#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 1 2460#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01 2461#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0 2462 2463/* Bit definitions for USB_ID_INT_EN_LO_SET */ 2464#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10 2465#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 4 2466#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08 2467#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 3 2468#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04 2469#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 2 2470#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02 2471#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 1 2472#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01 2473#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0 2474 2475/* Bit definitions for USB_ID_INT_EN_LO_CLR */ 2476#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10 2477#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 4 2478#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08 2479#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 3 2480#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04 2481#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 2 2482#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02 2483#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 1 2484#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01 2485#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0 2486 2487/* Bit definitions for USB_ID_INT_EN_HI_SET */ 2488#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10 2489#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 4 2490#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08 2491#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 3 2492#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04 2493#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 2 2494#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02 2495#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 1 2496#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01 2497#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0 2498 2499/* Bit definitions for USB_ID_INT_EN_HI_CLR */ 2500#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10 2501#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 4 2502#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08 2503#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 3 2504#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04 2505#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 2 2506#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02 2507#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 1 2508#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01 2509#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0 2510 2511/* Bit definitions for USB_OTG_ADP_CTRL */ 2512#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04 2513#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 2 2514#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03 2515#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0 2516 2517/* Bit definitions for USB_OTG_ADP_HIGH */ 2518#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xff 2519#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0 2520 2521/* Bit definitions for USB_OTG_ADP_LOW */ 2522#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xff 2523#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0 2524 2525/* Bit definitions for USB_OTG_ADP_RISE */ 2526#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xff 2527#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0 2528 2529/* Bit definitions for USB_OTG_REVISION */ 2530#define PALMAS_USB_OTG_REVISION_OTG_REV 0x01 2531#define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0 2532 2533/* Registers for function VIBRATOR */ 2534#define PALMAS_VIBRA_CTRL 0x0 2535 2536/* Bit definitions for VIBRA_CTRL */ 2537#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06 2538#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 1 2539#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01 2540#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0 2541 2542/* Registers for function GPIO */ 2543#define PALMAS_GPIO_DATA_IN 0x0 2544#define PALMAS_GPIO_DATA_DIR 0x1 2545#define PALMAS_GPIO_DATA_OUT 0x2 2546#define PALMAS_GPIO_DEBOUNCE_EN 0x3 2547#define PALMAS_GPIO_CLEAR_DATA_OUT 0x4 2548#define PALMAS_GPIO_SET_DATA_OUT 0x5 2549#define PALMAS_PU_PD_GPIO_CTRL1 0x6 2550#define PALMAS_PU_PD_GPIO_CTRL2 0x7 2551#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x8 2552#define PALMAS_GPIO_DATA_IN2 0x9 2553#define PALMAS_GPIO_DATA_DIR2 0x0A 2554#define PALMAS_GPIO_DATA_OUT2 0x0B 2555#define PALMAS_GPIO_DEBOUNCE_EN2 0x0C 2556#define PALMAS_GPIO_CLEAR_DATA_OUT2 0x0D 2557#define PALMAS_GPIO_SET_DATA_OUT2 0x0E 2558#define PALMAS_PU_PD_GPIO_CTRL3 0x0F 2559#define PALMAS_PU_PD_GPIO_CTRL4 0x10 2560#define PALMAS_OD_OUTPUT_GPIO_CTRL2 0x11 2561 2562/* Bit definitions for GPIO_DATA_IN */ 2563#define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80 2564#define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 7 2565#define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40 2566#define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 6 2567#define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20 2568#define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 5 2569#define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10 2570#define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 4 2571#define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08 2572#define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 3 2573#define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04 2574#define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 2 2575#define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02 2576#define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 1 2577#define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01 2578#define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0 2579 2580/* Bit definitions for GPIO_DATA_DIR */ 2581#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80 2582#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 7 2583#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40 2584#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 6 2585#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20 2586#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 5 2587#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10 2588#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 4 2589#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08 2590#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 3 2591#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04 2592#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 2 2593#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02 2594#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 1 2595#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01 2596#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0 2597 2598/* Bit definitions for GPIO_DATA_OUT */ 2599#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80 2600#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 7 2601#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40 2602#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 6 2603#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20 2604#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 5 2605#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10 2606#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 4 2607#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08 2608#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 3 2609#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04 2610#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 2 2611#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02 2612#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 1 2613#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01 2614#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0 2615 2616/* Bit definitions for GPIO_DEBOUNCE_EN */ 2617#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80 2618#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 7 2619#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40 2620#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 6 2621#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20 2622#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 5 2623#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10 2624#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 4 2625#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08 2626#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 3 2627#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04 2628#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 2 2629#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02 2630#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 1 2631#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01 2632#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0 2633 2634/* Bit definitions for GPIO_CLEAR_DATA_OUT */ 2635#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80 2636#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 7 2637#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40 2638#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 6 2639#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20 2640#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 5 2641#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10 2642#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 4 2643#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08 2644#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 3 2645#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04 2646#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 2 2647#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02 2648#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 1 2649#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01 2650#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0 2651 2652/* Bit definitions for GPIO_SET_DATA_OUT */ 2653#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80 2654#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 7 2655#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40 2656#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 6 2657#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20 2658#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 5 2659#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10 2660#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 4 2661#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08 2662#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 3 2663#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04 2664#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 2 2665#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02 2666#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 1 2667#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01 2668#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0 2669 2670/* Bit definitions for PU_PD_GPIO_CTRL1 */ 2671#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40 2672#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 6 2673#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20 2674#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 5 2675#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10 2676#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 4 2677#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08 2678#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 3 2679#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04 2680#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 2 2681#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01 2682#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0 2683 2684/* Bit definitions for PU_PD_GPIO_CTRL2 */ 2685#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40 2686#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 6 2687#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20 2688#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 5 2689#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10 2690#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 4 2691#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08 2692#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 3 2693#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04 2694#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 2 2695#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02 2696#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 1 2697#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01 2698#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0 2699 2700/* Bit definitions for OD_OUTPUT_GPIO_CTRL */ 2701#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20 2702#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 5 2703#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04 2704#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 2 2705#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02 2706#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 1 2707 2708/* Registers for function GPADC */ 2709#define PALMAS_GPADC_CTRL1 0x0 2710#define PALMAS_GPADC_CTRL2 0x1 2711#define PALMAS_GPADC_RT_CTRL 0x2 2712#define PALMAS_GPADC_AUTO_CTRL 0x3 2713#define PALMAS_GPADC_STATUS 0x4 2714#define PALMAS_GPADC_RT_SELECT 0x5 2715#define PALMAS_GPADC_RT_CONV0_LSB 0x6 2716#define PALMAS_GPADC_RT_CONV0_MSB 0x7 2717#define PALMAS_GPADC_AUTO_SELECT 0x8 2718#define PALMAS_GPADC_AUTO_CONV0_LSB 0x9 2719#define PALMAS_GPADC_AUTO_CONV0_MSB 0xA 2720#define PALMAS_GPADC_AUTO_CONV1_LSB 0xB 2721#define PALMAS_GPADC_AUTO_CONV1_MSB 0xC 2722#define PALMAS_GPADC_SW_SELECT 0xD 2723#define PALMAS_GPADC_SW_CONV0_LSB 0xE 2724#define PALMAS_GPADC_SW_CONV0_MSB 0xF 2725#define PALMAS_GPADC_THRES_CONV0_LSB 0x10 2726#define PALMAS_GPADC_THRES_CONV0_MSB 0x11 2727#define PALMAS_GPADC_THRES_CONV1_LSB 0x12 2728#define PALMAS_GPADC_THRES_CONV1_MSB 0x13 2729#define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14 2730#define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15 2731 2732/* Bit definitions for GPADC_CTRL1 */ 2733#define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0 2734#define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 6 2735#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30 2736#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 4 2737#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c 2738#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 2 2739#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02 2740#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 1 2741#define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01 2742#define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0 2743 2744/* Bit definitions for GPADC_CTRL2 */ 2745#define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06 2746#define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 1 2747 2748/* Bit definitions for GPADC_RT_CTRL */ 2749#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02 2750#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 1 2751#define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01 2752#define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0 2753 2754/* Bit definitions for GPADC_AUTO_CTRL */ 2755#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80 2756#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 7 2757#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40 2758#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 6 2759#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20 2760#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 5 2761#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10 2762#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 4 2763#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0f 2764#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0 2765 2766/* Bit definitions for GPADC_STATUS */ 2767#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10 2768#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 4 2769 2770/* Bit definitions for GPADC_RT_SELECT */ 2771#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80 2772#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 7 2773#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0f 2774#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0 2775 2776/* Bit definitions for GPADC_RT_CONV0_LSB */ 2777#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xff 2778#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0 2779 2780/* Bit definitions for GPADC_RT_CONV0_MSB */ 2781#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0f 2782#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0 2783 2784/* Bit definitions for GPADC_AUTO_SELECT */ 2785#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xf0 2786#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 4 2787#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0f 2788#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0 2789 2790/* Bit definitions for GPADC_AUTO_CONV0_LSB */ 2791#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xff 2792#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0 2793 2794/* Bit definitions for GPADC_AUTO_CONV0_MSB */ 2795#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0f 2796#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0 2797 2798/* Bit definitions for GPADC_AUTO_CONV1_LSB */ 2799#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xff 2800#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0 2801 2802/* Bit definitions for GPADC_AUTO_CONV1_MSB */ 2803#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0f 2804#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0 2805 2806/* Bit definitions for GPADC_SW_SELECT */ 2807#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80 2808#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 7 2809#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10 2810#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 4 2811#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0f 2812#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0 2813 2814/* Bit definitions for GPADC_SW_CONV0_LSB */ 2815#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xff 2816#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0 2817 2818/* Bit definitions for GPADC_SW_CONV0_MSB */ 2819#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0f 2820#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0 2821 2822/* Bit definitions for GPADC_THRES_CONV0_LSB */ 2823#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xff 2824#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0 2825 2826/* Bit definitions for GPADC_THRES_CONV0_MSB */ 2827#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80 2828#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 7 2829#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0f 2830#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0 2831 2832/* Bit definitions for GPADC_THRES_CONV1_LSB */ 2833#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xff 2834#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0 2835 2836/* Bit definitions for GPADC_THRES_CONV1_MSB */ 2837#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80 2838#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 7 2839#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0f 2840#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0 2841 2842/* Bit definitions for GPADC_SMPS_ILMONITOR_EN */ 2843#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20 2844#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 5 2845#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10 2846#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 4 2847#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0f 2848#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0 2849 2850/* Bit definitions for GPADC_SMPS_VSEL_MONITORING */ 2851#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80 2852#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 7 2853#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7f 2854#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0 2855 2856/* Registers for function GPADC */ 2857#define PALMAS_GPADC_TRIM1 0x0 2858#define PALMAS_GPADC_TRIM2 0x1 2859#define PALMAS_GPADC_TRIM3 0x2 2860#define PALMAS_GPADC_TRIM4 0x3 2861#define PALMAS_GPADC_TRIM5 0x4 2862#define PALMAS_GPADC_TRIM6 0x5 2863#define PALMAS_GPADC_TRIM7 0x6 2864#define PALMAS_GPADC_TRIM8 0x7 2865#define PALMAS_GPADC_TRIM9 0x8 2866#define PALMAS_GPADC_TRIM10 0x9 2867#define PALMAS_GPADC_TRIM11 0xA 2868#define PALMAS_GPADC_TRIM12 0xB 2869#define PALMAS_GPADC_TRIM13 0xC 2870#define PALMAS_GPADC_TRIM14 0xD 2871#define PALMAS_GPADC_TRIM15 0xE 2872#define PALMAS_GPADC_TRIM16 0xF 2873 2874static inline int palmas_read(struct palmas *palmas, unsigned int base, 2875 unsigned int reg, unsigned int *val) 2876{ 2877 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 2878 int slave_id = PALMAS_BASE_TO_SLAVE(base); 2879 2880 return regmap_read(palmas->regmap[slave_id], addr, val); 2881} 2882 2883static inline int palmas_write(struct palmas *palmas, unsigned int base, 2884 unsigned int reg, unsigned int value) 2885{ 2886 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 2887 int slave_id = PALMAS_BASE_TO_SLAVE(base); 2888 2889 return regmap_write(palmas->regmap[slave_id], addr, value); 2890} 2891 2892static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base, 2893 unsigned int reg, const void *val, size_t val_count) 2894{ 2895 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 2896 int slave_id = PALMAS_BASE_TO_SLAVE(base); 2897 2898 return regmap_bulk_write(palmas->regmap[slave_id], addr, 2899 val, val_count); 2900} 2901 2902static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base, 2903 unsigned int reg, void *val, size_t val_count) 2904{ 2905 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 2906 int slave_id = PALMAS_BASE_TO_SLAVE(base); 2907 2908 return regmap_bulk_read(palmas->regmap[slave_id], addr, 2909 val, val_count); 2910} 2911 2912static inline int palmas_update_bits(struct palmas *palmas, unsigned int base, 2913 unsigned int reg, unsigned int mask, unsigned int val) 2914{ 2915 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 2916 int slave_id = PALMAS_BASE_TO_SLAVE(base); 2917 2918 return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val); 2919} 2920 2921static inline int palmas_irq_get_virq(struct palmas *palmas, int irq) 2922{ 2923 return regmap_irq_get_virq(palmas->irq_data, irq); 2924} 2925 2926 2927int palmas_ext_control_req_config(struct palmas *palmas, 2928 enum palmas_external_requestor_id ext_control_req_id, 2929 int ext_ctrl, bool enable); 2930 2931#endif /* __LINUX_MFD_PALMAS_H */