tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_ASIC_H__
29#define __RADEON_ASIC_H__
30
31/*
32 * common functions
33 */
34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
36uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
37void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
38
39uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
40void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
41uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
42void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
43void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
44
45void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
46u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
47void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
48u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
49
50u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev,
51 struct radeon_ring *ring);
52u32 radeon_ring_generic_get_wptr(struct radeon_device *rdev,
53 struct radeon_ring *ring);
54void radeon_ring_generic_set_wptr(struct radeon_device *rdev,
55 struct radeon_ring *ring);
56
57/*
58 * r100,rv100,rs100,rv200,rs200
59 */
60struct r100_mc_save {
61 u32 GENMO_WT;
62 u32 CRTC_EXT_CNTL;
63 u32 CRTC_GEN_CNTL;
64 u32 CRTC2_GEN_CNTL;
65 u32 CUR_OFFSET;
66 u32 CUR2_OFFSET;
67};
68int r100_init(struct radeon_device *rdev);
69void r100_fini(struct radeon_device *rdev);
70int r100_suspend(struct radeon_device *rdev);
71int r100_resume(struct radeon_device *rdev);
72void r100_vga_set_state(struct radeon_device *rdev, bool state);
73bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
74int r100_asic_reset(struct radeon_device *rdev);
75u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
76void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
77int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
78void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
79int r100_irq_set(struct radeon_device *rdev);
80int r100_irq_process(struct radeon_device *rdev);
81void r100_fence_ring_emit(struct radeon_device *rdev,
82 struct radeon_fence *fence);
83bool r100_semaphore_ring_emit(struct radeon_device *rdev,
84 struct radeon_ring *cp,
85 struct radeon_semaphore *semaphore,
86 bool emit_wait);
87int r100_cs_parse(struct radeon_cs_parser *p);
88void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
89uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
90int r100_copy_blit(struct radeon_device *rdev,
91 uint64_t src_offset,
92 uint64_t dst_offset,
93 unsigned num_gpu_pages,
94 struct radeon_fence **fence);
95int r100_set_surface_reg(struct radeon_device *rdev, int reg,
96 uint32_t tiling_flags, uint32_t pitch,
97 uint32_t offset, uint32_t obj_size);
98void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
99void r100_bandwidth_update(struct radeon_device *rdev);
100void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
101int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
102void r100_hpd_init(struct radeon_device *rdev);
103void r100_hpd_fini(struct radeon_device *rdev);
104bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
105void r100_hpd_set_polarity(struct radeon_device *rdev,
106 enum radeon_hpd_id hpd);
107int r100_debugfs_rbbm_init(struct radeon_device *rdev);
108int r100_debugfs_cp_init(struct radeon_device *rdev);
109void r100_cp_disable(struct radeon_device *rdev);
110int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
111void r100_cp_fini(struct radeon_device *rdev);
112int r100_pci_gart_init(struct radeon_device *rdev);
113void r100_pci_gart_fini(struct radeon_device *rdev);
114int r100_pci_gart_enable(struct radeon_device *rdev);
115void r100_pci_gart_disable(struct radeon_device *rdev);
116int r100_debugfs_mc_info_init(struct radeon_device *rdev);
117int r100_gui_wait_for_idle(struct radeon_device *rdev);
118int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
119void r100_irq_disable(struct radeon_device *rdev);
120void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
121void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
122void r100_vram_init_sizes(struct radeon_device *rdev);
123int r100_cp_reset(struct radeon_device *rdev);
124void r100_vga_render_disable(struct radeon_device *rdev);
125void r100_restore_sanity(struct radeon_device *rdev);
126int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
127 struct radeon_cs_packet *pkt,
128 struct radeon_bo *robj);
129int r100_cs_parse_packet0(struct radeon_cs_parser *p,
130 struct radeon_cs_packet *pkt,
131 const unsigned *auth, unsigned n,
132 radeon_packet0_check_t check);
133int r100_cs_packet_parse(struct radeon_cs_parser *p,
134 struct radeon_cs_packet *pkt,
135 unsigned idx);
136void r100_enable_bm(struct radeon_device *rdev);
137void r100_set_common_regs(struct radeon_device *rdev);
138void r100_bm_disable(struct radeon_device *rdev);
139extern bool r100_gui_idle(struct radeon_device *rdev);
140extern void r100_pm_misc(struct radeon_device *rdev);
141extern void r100_pm_prepare(struct radeon_device *rdev);
142extern void r100_pm_finish(struct radeon_device *rdev);
143extern void r100_pm_init_profile(struct radeon_device *rdev);
144extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
145extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc);
146extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
147extern void r100_post_page_flip(struct radeon_device *rdev, int crtc);
148extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
149extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
150
151/*
152 * r200,rv250,rs300,rv280
153 */
154extern int r200_copy_dma(struct radeon_device *rdev,
155 uint64_t src_offset,
156 uint64_t dst_offset,
157 unsigned num_gpu_pages,
158 struct radeon_fence **fence);
159void r200_set_safe_registers(struct radeon_device *rdev);
160
161/*
162 * r300,r350,rv350,rv380
163 */
164extern int r300_init(struct radeon_device *rdev);
165extern void r300_fini(struct radeon_device *rdev);
166extern int r300_suspend(struct radeon_device *rdev);
167extern int r300_resume(struct radeon_device *rdev);
168extern int r300_asic_reset(struct radeon_device *rdev);
169extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
170extern void r300_fence_ring_emit(struct radeon_device *rdev,
171 struct radeon_fence *fence);
172extern int r300_cs_parse(struct radeon_cs_parser *p);
173extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
174extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
175extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
176extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
177extern void r300_set_reg_safe(struct radeon_device *rdev);
178extern void r300_mc_program(struct radeon_device *rdev);
179extern void r300_mc_init(struct radeon_device *rdev);
180extern void r300_clock_startup(struct radeon_device *rdev);
181extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
182extern int rv370_pcie_gart_init(struct radeon_device *rdev);
183extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
184extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
185extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
186extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
187
188/*
189 * r420,r423,rv410
190 */
191extern int r420_init(struct radeon_device *rdev);
192extern void r420_fini(struct radeon_device *rdev);
193extern int r420_suspend(struct radeon_device *rdev);
194extern int r420_resume(struct radeon_device *rdev);
195extern void r420_pm_init_profile(struct radeon_device *rdev);
196extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
197extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
198extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
199extern void r420_pipes_init(struct radeon_device *rdev);
200
201/*
202 * rs400,rs480
203 */
204extern int rs400_init(struct radeon_device *rdev);
205extern void rs400_fini(struct radeon_device *rdev);
206extern int rs400_suspend(struct radeon_device *rdev);
207extern int rs400_resume(struct radeon_device *rdev);
208void rs400_gart_tlb_flush(struct radeon_device *rdev);
209int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
210uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
211void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
212int rs400_gart_init(struct radeon_device *rdev);
213int rs400_gart_enable(struct radeon_device *rdev);
214void rs400_gart_adjust_size(struct radeon_device *rdev);
215void rs400_gart_disable(struct radeon_device *rdev);
216void rs400_gart_fini(struct radeon_device *rdev);
217extern int rs400_mc_wait_for_idle(struct radeon_device *rdev);
218
219/*
220 * rs600.
221 */
222extern int rs600_asic_reset(struct radeon_device *rdev);
223extern int rs600_init(struct radeon_device *rdev);
224extern void rs600_fini(struct radeon_device *rdev);
225extern int rs600_suspend(struct radeon_device *rdev);
226extern int rs600_resume(struct radeon_device *rdev);
227int rs600_irq_set(struct radeon_device *rdev);
228int rs600_irq_process(struct radeon_device *rdev);
229void rs600_irq_disable(struct radeon_device *rdev);
230u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
231void rs600_gart_tlb_flush(struct radeon_device *rdev);
232int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
233uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
234void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
235void rs600_bandwidth_update(struct radeon_device *rdev);
236void rs600_hpd_init(struct radeon_device *rdev);
237void rs600_hpd_fini(struct radeon_device *rdev);
238bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
239void rs600_hpd_set_polarity(struct radeon_device *rdev,
240 enum radeon_hpd_id hpd);
241extern void rs600_pm_misc(struct radeon_device *rdev);
242extern void rs600_pm_prepare(struct radeon_device *rdev);
243extern void rs600_pm_finish(struct radeon_device *rdev);
244extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc);
245extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
246extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc);
247void rs600_set_safe_registers(struct radeon_device *rdev);
248extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc);
249extern int rs600_mc_wait_for_idle(struct radeon_device *rdev);
250
251/*
252 * rs690,rs740
253 */
254int rs690_init(struct radeon_device *rdev);
255void rs690_fini(struct radeon_device *rdev);
256int rs690_resume(struct radeon_device *rdev);
257int rs690_suspend(struct radeon_device *rdev);
258uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
259void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
260void rs690_bandwidth_update(struct radeon_device *rdev);
261void rs690_line_buffer_adjust(struct radeon_device *rdev,
262 struct drm_display_mode *mode1,
263 struct drm_display_mode *mode2);
264extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
265
266/*
267 * rv515
268 */
269struct rv515_mc_save {
270 u32 vga_render_control;
271 u32 vga_hdp_control;
272 bool crtc_enabled[2];
273};
274
275int rv515_init(struct radeon_device *rdev);
276void rv515_fini(struct radeon_device *rdev);
277uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
278void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
279void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
280void rv515_bandwidth_update(struct radeon_device *rdev);
281int rv515_resume(struct radeon_device *rdev);
282int rv515_suspend(struct radeon_device *rdev);
283void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
284void rv515_vga_render_disable(struct radeon_device *rdev);
285void rv515_set_safe_registers(struct radeon_device *rdev);
286void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
287void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
288void rv515_clock_startup(struct radeon_device *rdev);
289void rv515_debugfs(struct radeon_device *rdev);
290int rv515_mc_wait_for_idle(struct radeon_device *rdev);
291
292/*
293 * r520,rv530,rv560,rv570,r580
294 */
295int r520_init(struct radeon_device *rdev);
296int r520_resume(struct radeon_device *rdev);
297int r520_mc_wait_for_idle(struct radeon_device *rdev);
298
299/*
300 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
301 */
302int r600_init(struct radeon_device *rdev);
303void r600_fini(struct radeon_device *rdev);
304int r600_suspend(struct radeon_device *rdev);
305int r600_resume(struct radeon_device *rdev);
306void r600_vga_set_state(struct radeon_device *rdev, bool state);
307int r600_wb_init(struct radeon_device *rdev);
308void r600_wb_fini(struct radeon_device *rdev);
309void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
310uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
311void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
312int r600_cs_parse(struct radeon_cs_parser *p);
313int r600_dma_cs_parse(struct radeon_cs_parser *p);
314void r600_fence_ring_emit(struct radeon_device *rdev,
315 struct radeon_fence *fence);
316bool r600_semaphore_ring_emit(struct radeon_device *rdev,
317 struct radeon_ring *cp,
318 struct radeon_semaphore *semaphore,
319 bool emit_wait);
320void r600_dma_fence_ring_emit(struct radeon_device *rdev,
321 struct radeon_fence *fence);
322bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
323 struct radeon_ring *ring,
324 struct radeon_semaphore *semaphore,
325 bool emit_wait);
326void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
327bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
328bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
329int r600_asic_reset(struct radeon_device *rdev);
330int r600_set_surface_reg(struct radeon_device *rdev, int reg,
331 uint32_t tiling_flags, uint32_t pitch,
332 uint32_t offset, uint32_t obj_size);
333void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
334int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
335int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
336void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
337int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
338int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
339int r600_copy_cpdma(struct radeon_device *rdev,
340 uint64_t src_offset, uint64_t dst_offset,
341 unsigned num_gpu_pages, struct radeon_fence **fence);
342int r600_copy_dma(struct radeon_device *rdev,
343 uint64_t src_offset, uint64_t dst_offset,
344 unsigned num_gpu_pages, struct radeon_fence **fence);
345void r600_hpd_init(struct radeon_device *rdev);
346void r600_hpd_fini(struct radeon_device *rdev);
347bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
348void r600_hpd_set_polarity(struct radeon_device *rdev,
349 enum radeon_hpd_id hpd);
350extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
351extern bool r600_gui_idle(struct radeon_device *rdev);
352extern void r600_pm_misc(struct radeon_device *rdev);
353extern void r600_pm_init_profile(struct radeon_device *rdev);
354extern void rs780_pm_init_profile(struct radeon_device *rdev);
355extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);
356extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
357extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
358extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
359extern int r600_get_pcie_lanes(struct radeon_device *rdev);
360bool r600_card_posted(struct radeon_device *rdev);
361void r600_cp_stop(struct radeon_device *rdev);
362int r600_cp_start(struct radeon_device *rdev);
363void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size);
364int r600_cp_resume(struct radeon_device *rdev);
365void r600_cp_fini(struct radeon_device *rdev);
366int r600_count_pipe_bits(uint32_t val);
367int r600_mc_wait_for_idle(struct radeon_device *rdev);
368int r600_pcie_gart_init(struct radeon_device *rdev);
369void r600_scratch_init(struct radeon_device *rdev);
370int r600_init_microcode(struct radeon_device *rdev);
371/* r600 irq */
372int r600_irq_process(struct radeon_device *rdev);
373int r600_irq_init(struct radeon_device *rdev);
374void r600_irq_fini(struct radeon_device *rdev);
375void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
376int r600_irq_set(struct radeon_device *rdev);
377void r600_irq_suspend(struct radeon_device *rdev);
378void r600_disable_interrupts(struct radeon_device *rdev);
379void r600_rlc_stop(struct radeon_device *rdev);
380/* r600 audio */
381int r600_audio_init(struct radeon_device *rdev);
382struct r600_audio_pin r600_audio_status(struct radeon_device *rdev);
383void r600_audio_fini(struct radeon_device *rdev);
384int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
385void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
386void r600_hdmi_enable(struct drm_encoder *encoder, bool enable);
387void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
388int r600_mc_wait_for_idle(struct radeon_device *rdev);
389u32 r600_get_xclk(struct radeon_device *rdev);
390uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
391int rv6xx_get_temp(struct radeon_device *rdev);
392int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
393int r600_dpm_pre_set_power_state(struct radeon_device *rdev);
394void r600_dpm_post_set_power_state(struct radeon_device *rdev);
395/* r600 dma */
396uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
397 struct radeon_ring *ring);
398uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
399 struct radeon_ring *ring);
400void r600_dma_set_wptr(struct radeon_device *rdev,
401 struct radeon_ring *ring);
402/* rv6xx dpm */
403int rv6xx_dpm_init(struct radeon_device *rdev);
404int rv6xx_dpm_enable(struct radeon_device *rdev);
405void rv6xx_dpm_disable(struct radeon_device *rdev);
406int rv6xx_dpm_set_power_state(struct radeon_device *rdev);
407void rv6xx_setup_asic(struct radeon_device *rdev);
408void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev);
409void rv6xx_dpm_fini(struct radeon_device *rdev);
410u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low);
411u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low);
412void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
413 struct radeon_ps *ps);
414void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
415 struct seq_file *m);
416int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
417 enum radeon_dpm_forced_level level);
418/* rs780 dpm */
419int rs780_dpm_init(struct radeon_device *rdev);
420int rs780_dpm_enable(struct radeon_device *rdev);
421void rs780_dpm_disable(struct radeon_device *rdev);
422int rs780_dpm_set_power_state(struct radeon_device *rdev);
423void rs780_dpm_setup_asic(struct radeon_device *rdev);
424void rs780_dpm_display_configuration_changed(struct radeon_device *rdev);
425void rs780_dpm_fini(struct radeon_device *rdev);
426u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low);
427u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low);
428void rs780_dpm_print_power_state(struct radeon_device *rdev,
429 struct radeon_ps *ps);
430void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
431 struct seq_file *m);
432int rs780_dpm_force_performance_level(struct radeon_device *rdev,
433 enum radeon_dpm_forced_level level);
434
435/*
436 * rv770,rv730,rv710,rv740
437 */
438int rv770_init(struct radeon_device *rdev);
439void rv770_fini(struct radeon_device *rdev);
440int rv770_suspend(struct radeon_device *rdev);
441int rv770_resume(struct radeon_device *rdev);
442void rv770_pm_misc(struct radeon_device *rdev);
443u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
444void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
445void r700_cp_stop(struct radeon_device *rdev);
446void r700_cp_fini(struct radeon_device *rdev);
447int rv770_copy_dma(struct radeon_device *rdev,
448 uint64_t src_offset, uint64_t dst_offset,
449 unsigned num_gpu_pages,
450 struct radeon_fence **fence);
451u32 rv770_get_xclk(struct radeon_device *rdev);
452int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
453int rv770_get_temp(struct radeon_device *rdev);
454/* rv7xx pm */
455int rv770_dpm_init(struct radeon_device *rdev);
456int rv770_dpm_enable(struct radeon_device *rdev);
457void rv770_dpm_disable(struct radeon_device *rdev);
458int rv770_dpm_set_power_state(struct radeon_device *rdev);
459void rv770_dpm_setup_asic(struct radeon_device *rdev);
460void rv770_dpm_display_configuration_changed(struct radeon_device *rdev);
461void rv770_dpm_fini(struct radeon_device *rdev);
462u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low);
463u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low);
464void rv770_dpm_print_power_state(struct radeon_device *rdev,
465 struct radeon_ps *ps);
466void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
467 struct seq_file *m);
468int rv770_dpm_force_performance_level(struct radeon_device *rdev,
469 enum radeon_dpm_forced_level level);
470bool rv770_dpm_vblank_too_short(struct radeon_device *rdev);
471
472/*
473 * evergreen
474 */
475struct evergreen_mc_save {
476 u32 vga_render_control;
477 u32 vga_hdp_control;
478 bool crtc_enabled[RADEON_MAX_CRTCS];
479};
480
481void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
482int evergreen_init(struct radeon_device *rdev);
483void evergreen_fini(struct radeon_device *rdev);
484int evergreen_suspend(struct radeon_device *rdev);
485int evergreen_resume(struct radeon_device *rdev);
486bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
487bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
488int evergreen_asic_reset(struct radeon_device *rdev);
489void evergreen_bandwidth_update(struct radeon_device *rdev);
490void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
491void evergreen_hpd_init(struct radeon_device *rdev);
492void evergreen_hpd_fini(struct radeon_device *rdev);
493bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
494void evergreen_hpd_set_polarity(struct radeon_device *rdev,
495 enum radeon_hpd_id hpd);
496u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
497int evergreen_irq_set(struct radeon_device *rdev);
498int evergreen_irq_process(struct radeon_device *rdev);
499extern int evergreen_cs_parse(struct radeon_cs_parser *p);
500extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p);
501extern void evergreen_pm_misc(struct radeon_device *rdev);
502extern void evergreen_pm_prepare(struct radeon_device *rdev);
503extern void evergreen_pm_finish(struct radeon_device *rdev);
504extern void sumo_pm_init_profile(struct radeon_device *rdev);
505extern void btc_pm_init_profile(struct radeon_device *rdev);
506int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
507int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
508extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc);
509extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
510extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
511extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
512void evergreen_disable_interrupt_state(struct radeon_device *rdev);
513int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
514void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
515 struct radeon_fence *fence);
516void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
517 struct radeon_ib *ib);
518int evergreen_copy_dma(struct radeon_device *rdev,
519 uint64_t src_offset, uint64_t dst_offset,
520 unsigned num_gpu_pages,
521 struct radeon_fence **fence);
522void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable);
523void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
524int evergreen_get_temp(struct radeon_device *rdev);
525int sumo_get_temp(struct radeon_device *rdev);
526int tn_get_temp(struct radeon_device *rdev);
527int cypress_dpm_init(struct radeon_device *rdev);
528void cypress_dpm_setup_asic(struct radeon_device *rdev);
529int cypress_dpm_enable(struct radeon_device *rdev);
530void cypress_dpm_disable(struct radeon_device *rdev);
531int cypress_dpm_set_power_state(struct radeon_device *rdev);
532void cypress_dpm_display_configuration_changed(struct radeon_device *rdev);
533void cypress_dpm_fini(struct radeon_device *rdev);
534bool cypress_dpm_vblank_too_short(struct radeon_device *rdev);
535int btc_dpm_init(struct radeon_device *rdev);
536void btc_dpm_setup_asic(struct radeon_device *rdev);
537int btc_dpm_enable(struct radeon_device *rdev);
538void btc_dpm_disable(struct radeon_device *rdev);
539int btc_dpm_pre_set_power_state(struct radeon_device *rdev);
540int btc_dpm_set_power_state(struct radeon_device *rdev);
541void btc_dpm_post_set_power_state(struct radeon_device *rdev);
542void btc_dpm_fini(struct radeon_device *rdev);
543u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low);
544u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low);
545bool btc_dpm_vblank_too_short(struct radeon_device *rdev);
546int sumo_dpm_init(struct radeon_device *rdev);
547int sumo_dpm_enable(struct radeon_device *rdev);
548void sumo_dpm_disable(struct radeon_device *rdev);
549int sumo_dpm_pre_set_power_state(struct radeon_device *rdev);
550int sumo_dpm_set_power_state(struct radeon_device *rdev);
551void sumo_dpm_post_set_power_state(struct radeon_device *rdev);
552void sumo_dpm_setup_asic(struct radeon_device *rdev);
553void sumo_dpm_display_configuration_changed(struct radeon_device *rdev);
554void sumo_dpm_fini(struct radeon_device *rdev);
555u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low);
556u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low);
557void sumo_dpm_print_power_state(struct radeon_device *rdev,
558 struct radeon_ps *ps);
559void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
560 struct seq_file *m);
561int sumo_dpm_force_performance_level(struct radeon_device *rdev,
562 enum radeon_dpm_forced_level level);
563
564/*
565 * cayman
566 */
567void cayman_fence_ring_emit(struct radeon_device *rdev,
568 struct radeon_fence *fence);
569void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
570int cayman_init(struct radeon_device *rdev);
571void cayman_fini(struct radeon_device *rdev);
572int cayman_suspend(struct radeon_device *rdev);
573int cayman_resume(struct radeon_device *rdev);
574int cayman_asic_reset(struct radeon_device *rdev);
575void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
576int cayman_vm_init(struct radeon_device *rdev);
577void cayman_vm_fini(struct radeon_device *rdev);
578void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
579uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
580int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
581int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
582void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
583 struct radeon_ib *ib);
584bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
585bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
586void cayman_dma_vm_set_page(struct radeon_device *rdev,
587 struct radeon_ib *ib,
588 uint64_t pe,
589 uint64_t addr, unsigned count,
590 uint32_t incr, uint32_t flags);
591
592void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
593
594int ni_dpm_init(struct radeon_device *rdev);
595void ni_dpm_setup_asic(struct radeon_device *rdev);
596int ni_dpm_enable(struct radeon_device *rdev);
597void ni_dpm_disable(struct radeon_device *rdev);
598int ni_dpm_pre_set_power_state(struct radeon_device *rdev);
599int ni_dpm_set_power_state(struct radeon_device *rdev);
600void ni_dpm_post_set_power_state(struct radeon_device *rdev);
601void ni_dpm_fini(struct radeon_device *rdev);
602u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low);
603u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low);
604void ni_dpm_print_power_state(struct radeon_device *rdev,
605 struct radeon_ps *ps);
606void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
607 struct seq_file *m);
608int ni_dpm_force_performance_level(struct radeon_device *rdev,
609 enum radeon_dpm_forced_level level);
610bool ni_dpm_vblank_too_short(struct radeon_device *rdev);
611int trinity_dpm_init(struct radeon_device *rdev);
612int trinity_dpm_enable(struct radeon_device *rdev);
613void trinity_dpm_disable(struct radeon_device *rdev);
614int trinity_dpm_pre_set_power_state(struct radeon_device *rdev);
615int trinity_dpm_set_power_state(struct radeon_device *rdev);
616void trinity_dpm_post_set_power_state(struct radeon_device *rdev);
617void trinity_dpm_setup_asic(struct radeon_device *rdev);
618void trinity_dpm_display_configuration_changed(struct radeon_device *rdev);
619void trinity_dpm_fini(struct radeon_device *rdev);
620u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low);
621u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low);
622void trinity_dpm_print_power_state(struct radeon_device *rdev,
623 struct radeon_ps *ps);
624void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
625 struct seq_file *m);
626int trinity_dpm_force_performance_level(struct radeon_device *rdev,
627 enum radeon_dpm_forced_level level);
628void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
629
630/* DCE6 - SI */
631void dce6_bandwidth_update(struct radeon_device *rdev);
632int dce6_audio_init(struct radeon_device *rdev);
633void dce6_audio_fini(struct radeon_device *rdev);
634
635/*
636 * si
637 */
638void si_fence_ring_emit(struct radeon_device *rdev,
639 struct radeon_fence *fence);
640void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
641int si_init(struct radeon_device *rdev);
642void si_fini(struct radeon_device *rdev);
643int si_suspend(struct radeon_device *rdev);
644int si_resume(struct radeon_device *rdev);
645bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
646bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
647int si_asic_reset(struct radeon_device *rdev);
648void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
649int si_irq_set(struct radeon_device *rdev);
650int si_irq_process(struct radeon_device *rdev);
651int si_vm_init(struct radeon_device *rdev);
652void si_vm_fini(struct radeon_device *rdev);
653void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
654int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
655int si_copy_dma(struct radeon_device *rdev,
656 uint64_t src_offset, uint64_t dst_offset,
657 unsigned num_gpu_pages,
658 struct radeon_fence **fence);
659void si_dma_vm_set_page(struct radeon_device *rdev,
660 struct radeon_ib *ib,
661 uint64_t pe,
662 uint64_t addr, unsigned count,
663 uint32_t incr, uint32_t flags);
664void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
665u32 si_get_xclk(struct radeon_device *rdev);
666uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
667int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
668int si_get_temp(struct radeon_device *rdev);
669int si_dpm_init(struct radeon_device *rdev);
670void si_dpm_setup_asic(struct radeon_device *rdev);
671int si_dpm_enable(struct radeon_device *rdev);
672void si_dpm_disable(struct radeon_device *rdev);
673int si_dpm_pre_set_power_state(struct radeon_device *rdev);
674int si_dpm_set_power_state(struct radeon_device *rdev);
675void si_dpm_post_set_power_state(struct radeon_device *rdev);
676void si_dpm_fini(struct radeon_device *rdev);
677void si_dpm_display_configuration_changed(struct radeon_device *rdev);
678void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
679 struct seq_file *m);
680int si_dpm_force_performance_level(struct radeon_device *rdev,
681 enum radeon_dpm_forced_level level);
682
683/* DCE8 - CIK */
684void dce8_bandwidth_update(struct radeon_device *rdev);
685
686/*
687 * cik
688 */
689uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev);
690u32 cik_get_xclk(struct radeon_device *rdev);
691uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
692void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
693int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
694void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
695 struct radeon_fence *fence);
696bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
697 struct radeon_ring *ring,
698 struct radeon_semaphore *semaphore,
699 bool emit_wait);
700void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
701int cik_copy_dma(struct radeon_device *rdev,
702 uint64_t src_offset, uint64_t dst_offset,
703 unsigned num_gpu_pages,
704 struct radeon_fence **fence);
705int cik_copy_cpdma(struct radeon_device *rdev,
706 uint64_t src_offset, uint64_t dst_offset,
707 unsigned num_gpu_pages,
708 struct radeon_fence **fence);
709int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
710int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
711bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
712void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
713 struct radeon_fence *fence);
714void cik_fence_compute_ring_emit(struct radeon_device *rdev,
715 struct radeon_fence *fence);
716bool cik_semaphore_ring_emit(struct radeon_device *rdev,
717 struct radeon_ring *cp,
718 struct radeon_semaphore *semaphore,
719 bool emit_wait);
720void cik_pcie_gart_tlb_flush(struct radeon_device *rdev);
721int cik_init(struct radeon_device *rdev);
722void cik_fini(struct radeon_device *rdev);
723int cik_suspend(struct radeon_device *rdev);
724int cik_resume(struct radeon_device *rdev);
725bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
726int cik_asic_reset(struct radeon_device *rdev);
727void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
728int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
729int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
730int cik_irq_set(struct radeon_device *rdev);
731int cik_irq_process(struct radeon_device *rdev);
732int cik_vm_init(struct radeon_device *rdev);
733void cik_vm_fini(struct radeon_device *rdev);
734void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
735void cik_sdma_vm_set_page(struct radeon_device *rdev,
736 struct radeon_ib *ib,
737 uint64_t pe,
738 uint64_t addr, unsigned count,
739 uint32_t incr, uint32_t flags);
740void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
741int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
742u32 cik_compute_ring_get_rptr(struct radeon_device *rdev,
743 struct radeon_ring *ring);
744u32 cik_compute_ring_get_wptr(struct radeon_device *rdev,
745 struct radeon_ring *ring);
746void cik_compute_ring_set_wptr(struct radeon_device *rdev,
747 struct radeon_ring *ring);
748int ci_get_temp(struct radeon_device *rdev);
749int kv_get_temp(struct radeon_device *rdev);
750
751int ci_dpm_init(struct radeon_device *rdev);
752int ci_dpm_enable(struct radeon_device *rdev);
753void ci_dpm_disable(struct radeon_device *rdev);
754int ci_dpm_pre_set_power_state(struct radeon_device *rdev);
755int ci_dpm_set_power_state(struct radeon_device *rdev);
756void ci_dpm_post_set_power_state(struct radeon_device *rdev);
757void ci_dpm_setup_asic(struct radeon_device *rdev);
758void ci_dpm_display_configuration_changed(struct radeon_device *rdev);
759void ci_dpm_fini(struct radeon_device *rdev);
760u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low);
761u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low);
762void ci_dpm_print_power_state(struct radeon_device *rdev,
763 struct radeon_ps *ps);
764void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
765 struct seq_file *m);
766int ci_dpm_force_performance_level(struct radeon_device *rdev,
767 enum radeon_dpm_forced_level level);
768bool ci_dpm_vblank_too_short(struct radeon_device *rdev);
769void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
770
771int kv_dpm_init(struct radeon_device *rdev);
772int kv_dpm_enable(struct radeon_device *rdev);
773void kv_dpm_disable(struct radeon_device *rdev);
774int kv_dpm_pre_set_power_state(struct radeon_device *rdev);
775int kv_dpm_set_power_state(struct radeon_device *rdev);
776void kv_dpm_post_set_power_state(struct radeon_device *rdev);
777void kv_dpm_setup_asic(struct radeon_device *rdev);
778void kv_dpm_display_configuration_changed(struct radeon_device *rdev);
779void kv_dpm_fini(struct radeon_device *rdev);
780u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low);
781u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low);
782void kv_dpm_print_power_state(struct radeon_device *rdev,
783 struct radeon_ps *ps);
784void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
785 struct seq_file *m);
786int kv_dpm_force_performance_level(struct radeon_device *rdev,
787 enum radeon_dpm_forced_level level);
788void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
789void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
790
791/* uvd v1.0 */
792uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev,
793 struct radeon_ring *ring);
794uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev,
795 struct radeon_ring *ring);
796void uvd_v1_0_set_wptr(struct radeon_device *rdev,
797 struct radeon_ring *ring);
798
799int uvd_v1_0_init(struct radeon_device *rdev);
800void uvd_v1_0_fini(struct radeon_device *rdev);
801int uvd_v1_0_start(struct radeon_device *rdev);
802void uvd_v1_0_stop(struct radeon_device *rdev);
803
804int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
805int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
806bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev,
807 struct radeon_ring *ring,
808 struct radeon_semaphore *semaphore,
809 bool emit_wait);
810void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
811
812/* uvd v2.2 */
813int uvd_v2_2_resume(struct radeon_device *rdev);
814void uvd_v2_2_fence_emit(struct radeon_device *rdev,
815 struct radeon_fence *fence);
816
817/* uvd v3.1 */
818bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev,
819 struct radeon_ring *ring,
820 struct radeon_semaphore *semaphore,
821 bool emit_wait);
822
823/* uvd v4.2 */
824int uvd_v4_2_resume(struct radeon_device *rdev);
825
826#endif