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1/*
2 * PowerNV OPAL definitions.
3 *
4 * Copyright 2011 IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#ifndef __OPAL_H
13#define __OPAL_H
14
15/****** Takeover interface ********/
16
17/* PAPR H-Call used to querty the HAL existence and/or instanciate
18 * it from within pHyp (tech preview only).
19 *
20 * This is exclusively used in prom_init.c
21 */
22
23#ifndef __ASSEMBLY__
24
25struct opal_takeover_args {
26 u64 k_image; /* r4 */
27 u64 k_size; /* r5 */
28 u64 k_entry; /* r6 */
29 u64 k_entry2; /* r7 */
30 u64 hal_addr; /* r8 */
31 u64 rd_image; /* r9 */
32 u64 rd_size; /* r10 */
33 u64 rd_loc; /* r11 */
34};
35
36extern long opal_query_takeover(u64 *hal_size, u64 *hal_align);
37
38extern long opal_do_takeover(struct opal_takeover_args *args);
39
40struct rtas_args;
41extern int opal_enter_rtas(struct rtas_args *args,
42 unsigned long data,
43 unsigned long entry);
44
45#endif /* __ASSEMBLY__ */
46
47/****** OPAL APIs ******/
48
49/* Return codes */
50#define OPAL_SUCCESS 0
51#define OPAL_PARAMETER -1
52#define OPAL_BUSY -2
53#define OPAL_PARTIAL -3
54#define OPAL_CONSTRAINED -4
55#define OPAL_CLOSED -5
56#define OPAL_HARDWARE -6
57#define OPAL_UNSUPPORTED -7
58#define OPAL_PERMISSION -8
59#define OPAL_NO_MEM -9
60#define OPAL_RESOURCE -10
61#define OPAL_INTERNAL_ERROR -11
62#define OPAL_BUSY_EVENT -12
63#define OPAL_HARDWARE_FROZEN -13
64
65/* API Tokens (in r0) */
66#define OPAL_CONSOLE_WRITE 1
67#define OPAL_CONSOLE_READ 2
68#define OPAL_RTC_READ 3
69#define OPAL_RTC_WRITE 4
70#define OPAL_CEC_POWER_DOWN 5
71#define OPAL_CEC_REBOOT 6
72#define OPAL_READ_NVRAM 7
73#define OPAL_WRITE_NVRAM 8
74#define OPAL_HANDLE_INTERRUPT 9
75#define OPAL_POLL_EVENTS 10
76#define OPAL_PCI_SET_HUB_TCE_MEMORY 11
77#define OPAL_PCI_SET_PHB_TCE_MEMORY 12
78#define OPAL_PCI_CONFIG_READ_BYTE 13
79#define OPAL_PCI_CONFIG_READ_HALF_WORD 14
80#define OPAL_PCI_CONFIG_READ_WORD 15
81#define OPAL_PCI_CONFIG_WRITE_BYTE 16
82#define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
83#define OPAL_PCI_CONFIG_WRITE_WORD 18
84#define OPAL_SET_XIVE 19
85#define OPAL_GET_XIVE 20
86#define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
87#define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
88#define OPAL_PCI_EEH_FREEZE_STATUS 23
89#define OPAL_PCI_SHPC 24
90#define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
91#define OPAL_PCI_EEH_FREEZE_CLEAR 26
92#define OPAL_PCI_PHB_MMIO_ENABLE 27
93#define OPAL_PCI_SET_PHB_MEM_WINDOW 28
94#define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
95#define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
96#define OPAL_PCI_SET_PE 31
97#define OPAL_PCI_SET_PELTV 32
98#define OPAL_PCI_SET_MVE 33
99#define OPAL_PCI_SET_MVE_ENABLE 34
100#define OPAL_PCI_GET_XIVE_REISSUE 35
101#define OPAL_PCI_SET_XIVE_REISSUE 36
102#define OPAL_PCI_SET_XIVE_PE 37
103#define OPAL_GET_XIVE_SOURCE 38
104#define OPAL_GET_MSI_32 39
105#define OPAL_GET_MSI_64 40
106#define OPAL_START_CPU 41
107#define OPAL_QUERY_CPU_STATUS 42
108#define OPAL_WRITE_OPPANEL 43
109#define OPAL_PCI_MAP_PE_DMA_WINDOW 44
110#define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
111#define OPAL_PCI_RESET 49
112#define OPAL_PCI_GET_HUB_DIAG_DATA 50
113#define OPAL_PCI_GET_PHB_DIAG_DATA 51
114#define OPAL_PCI_FENCE_PHB 52
115#define OPAL_PCI_REINIT 53
116#define OPAL_PCI_MASK_PE_ERROR 54
117#define OPAL_SET_SLOT_LED_STATUS 55
118#define OPAL_GET_EPOW_STATUS 56
119#define OPAL_SET_SYSTEM_ATTENTION_LED 57
120#define OPAL_RESERVED1 58
121#define OPAL_RESERVED2 59
122#define OPAL_PCI_NEXT_ERROR 60
123#define OPAL_PCI_EEH_FREEZE_STATUS2 61
124#define OPAL_PCI_POLL 62
125#define OPAL_PCI_MSI_EOI 63
126#define OPAL_PCI_GET_PHB_DIAG_DATA2 64
127#define OPAL_XSCOM_READ 65
128#define OPAL_XSCOM_WRITE 66
129#define OPAL_LPC_READ 67
130#define OPAL_LPC_WRITE 68
131#define OPAL_RETURN_CPU 69
132#define OPAL_FLASH_VALIDATE 76
133#define OPAL_FLASH_MANAGE 77
134#define OPAL_FLASH_UPDATE 78
135
136#ifndef __ASSEMBLY__
137
138/* Other enums */
139enum OpalVendorApiTokens {
140 OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
141};
142
143enum OpalFreezeState {
144 OPAL_EEH_STOPPED_NOT_FROZEN = 0,
145 OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
146 OPAL_EEH_STOPPED_DMA_FREEZE = 2,
147 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
148 OPAL_EEH_STOPPED_RESET = 4,
149 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
150 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
151};
152
153enum OpalEehFreezeActionToken {
154 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
155 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
156 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
157};
158
159enum OpalPciStatusToken {
160 OPAL_EEH_NO_ERROR = 0,
161 OPAL_EEH_IOC_ERROR = 1,
162 OPAL_EEH_PHB_ERROR = 2,
163 OPAL_EEH_PE_ERROR = 3,
164 OPAL_EEH_PE_MMIO_ERROR = 4,
165 OPAL_EEH_PE_DMA_ERROR = 5
166};
167
168enum OpalPciErrorSeverity {
169 OPAL_EEH_SEV_NO_ERROR = 0,
170 OPAL_EEH_SEV_IOC_DEAD = 1,
171 OPAL_EEH_SEV_PHB_DEAD = 2,
172 OPAL_EEH_SEV_PHB_FENCED = 3,
173 OPAL_EEH_SEV_PE_ER = 4,
174 OPAL_EEH_SEV_INF = 5
175};
176
177enum OpalShpcAction {
178 OPAL_SHPC_GET_LINK_STATE = 0,
179 OPAL_SHPC_GET_SLOT_STATE = 1
180};
181
182enum OpalShpcLinkState {
183 OPAL_SHPC_LINK_DOWN = 0,
184 OPAL_SHPC_LINK_UP = 1
185};
186
187enum OpalMmioWindowType {
188 OPAL_M32_WINDOW_TYPE = 1,
189 OPAL_M64_WINDOW_TYPE = 2,
190 OPAL_IO_WINDOW_TYPE = 3
191};
192
193enum OpalShpcSlotState {
194 OPAL_SHPC_DEV_NOT_PRESENT = 0,
195 OPAL_SHPC_DEV_PRESENT = 1
196};
197
198enum OpalExceptionHandler {
199 OPAL_MACHINE_CHECK_HANDLER = 1,
200 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
201 OPAL_SOFTPATCH_HANDLER = 3
202};
203
204enum OpalPendingState {
205 OPAL_EVENT_OPAL_INTERNAL = 0x1,
206 OPAL_EVENT_NVRAM = 0x2,
207 OPAL_EVENT_RTC = 0x4,
208 OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
209 OPAL_EVENT_CONSOLE_INPUT = 0x10,
210 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
211 OPAL_EVENT_ERROR_LOG = 0x40,
212 OPAL_EVENT_EPOW = 0x80,
213 OPAL_EVENT_LED_STATUS = 0x100,
214 OPAL_EVENT_PCI_ERROR = 0x200
215};
216
217/* Machine check related definitions */
218enum OpalMCE_Version {
219 OpalMCE_V1 = 1,
220};
221
222enum OpalMCE_Severity {
223 OpalMCE_SEV_NO_ERROR = 0,
224 OpalMCE_SEV_WARNING = 1,
225 OpalMCE_SEV_ERROR_SYNC = 2,
226 OpalMCE_SEV_FATAL = 3,
227};
228
229enum OpalMCE_Disposition {
230 OpalMCE_DISPOSITION_RECOVERED = 0,
231 OpalMCE_DISPOSITION_NOT_RECOVERED = 1,
232};
233
234enum OpalMCE_Initiator {
235 OpalMCE_INITIATOR_UNKNOWN = 0,
236 OpalMCE_INITIATOR_CPU = 1,
237};
238
239enum OpalMCE_ErrorType {
240 OpalMCE_ERROR_TYPE_UNKNOWN = 0,
241 OpalMCE_ERROR_TYPE_UE = 1,
242 OpalMCE_ERROR_TYPE_SLB = 2,
243 OpalMCE_ERROR_TYPE_ERAT = 3,
244 OpalMCE_ERROR_TYPE_TLB = 4,
245};
246
247enum OpalMCE_UeErrorType {
248 OpalMCE_UE_ERROR_INDETERMINATE = 0,
249 OpalMCE_UE_ERROR_IFETCH = 1,
250 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
251 OpalMCE_UE_ERROR_LOAD_STORE = 3,
252 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
253};
254
255enum OpalMCE_SlbErrorType {
256 OpalMCE_SLB_ERROR_INDETERMINATE = 0,
257 OpalMCE_SLB_ERROR_PARITY = 1,
258 OpalMCE_SLB_ERROR_MULTIHIT = 2,
259};
260
261enum OpalMCE_EratErrorType {
262 OpalMCE_ERAT_ERROR_INDETERMINATE = 0,
263 OpalMCE_ERAT_ERROR_PARITY = 1,
264 OpalMCE_ERAT_ERROR_MULTIHIT = 2,
265};
266
267enum OpalMCE_TlbErrorType {
268 OpalMCE_TLB_ERROR_INDETERMINATE = 0,
269 OpalMCE_TLB_ERROR_PARITY = 1,
270 OpalMCE_TLB_ERROR_MULTIHIT = 2,
271};
272
273enum OpalThreadStatus {
274 OPAL_THREAD_INACTIVE = 0x0,
275 OPAL_THREAD_STARTED = 0x1,
276 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
277};
278
279enum OpalPciBusCompare {
280 OpalPciBusAny = 0, /* Any bus number match */
281 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */
282 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */
283 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */
284 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */
285 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */
286 OpalPciBusAll = 7, /* Match bus number exactly */
287};
288
289enum OpalDeviceCompare {
290 OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
291 OPAL_COMPARE_RID_DEVICE_NUMBER = 1
292};
293
294enum OpalFuncCompare {
295 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
296 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
297};
298
299enum OpalPeAction {
300 OPAL_UNMAP_PE = 0,
301 OPAL_MAP_PE = 1
302};
303
304enum OpalPeltvAction {
305 OPAL_REMOVE_PE_FROM_DOMAIN = 0,
306 OPAL_ADD_PE_TO_DOMAIN = 1
307};
308
309enum OpalMveEnableAction {
310 OPAL_DISABLE_MVE = 0,
311 OPAL_ENABLE_MVE = 1
312};
313
314enum OpalPciResetAndReinitScope {
315 OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
316 OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
317 OPAL_PCI_IODA_TABLE_RESET = 6,
318};
319
320enum OpalPciResetState {
321 OPAL_DEASSERT_RESET = 0,
322 OPAL_ASSERT_RESET = 1
323};
324
325enum OpalPciMaskAction {
326 OPAL_UNMASK_ERROR_TYPE = 0,
327 OPAL_MASK_ERROR_TYPE = 1
328};
329
330enum OpalSlotLedType {
331 OPAL_SLOT_LED_ID_TYPE = 0,
332 OPAL_SLOT_LED_FAULT_TYPE = 1
333};
334
335enum OpalLedAction {
336 OPAL_TURN_OFF_LED = 0,
337 OPAL_TURN_ON_LED = 1,
338 OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
339};
340
341enum OpalEpowStatus {
342 OPAL_EPOW_NONE = 0,
343 OPAL_EPOW_UPS = 1,
344 OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
345 OPAL_EPOW_OVER_INTERNAL_TEMP = 3
346};
347
348/*
349 * Address cycle types for LPC accesses. These also correspond
350 * to the content of the first cell of the "reg" property for
351 * device nodes on the LPC bus
352 */
353enum OpalLPCAddressType {
354 OPAL_LPC_MEM = 0,
355 OPAL_LPC_IO = 1,
356 OPAL_LPC_FW = 2,
357};
358
359struct opal_machine_check_event {
360 enum OpalMCE_Version version:8; /* 0x00 */
361 uint8_t in_use; /* 0x01 */
362 enum OpalMCE_Severity severity:8; /* 0x02 */
363 enum OpalMCE_Initiator initiator:8; /* 0x03 */
364 enum OpalMCE_ErrorType error_type:8; /* 0x04 */
365 enum OpalMCE_Disposition disposition:8; /* 0x05 */
366 uint8_t reserved_1[2]; /* 0x06 */
367 uint64_t gpr3; /* 0x08 */
368 uint64_t srr0; /* 0x10 */
369 uint64_t srr1; /* 0x18 */
370 union { /* 0x20 */
371 struct {
372 enum OpalMCE_UeErrorType ue_error_type:8;
373 uint8_t effective_address_provided;
374 uint8_t physical_address_provided;
375 uint8_t reserved_1[5];
376 uint64_t effective_address;
377 uint64_t physical_address;
378 uint8_t reserved_2[8];
379 } ue_error;
380
381 struct {
382 enum OpalMCE_SlbErrorType slb_error_type:8;
383 uint8_t effective_address_provided;
384 uint8_t reserved_1[6];
385 uint64_t effective_address;
386 uint8_t reserved_2[16];
387 } slb_error;
388
389 struct {
390 enum OpalMCE_EratErrorType erat_error_type:8;
391 uint8_t effective_address_provided;
392 uint8_t reserved_1[6];
393 uint64_t effective_address;
394 uint8_t reserved_2[16];
395 } erat_error;
396
397 struct {
398 enum OpalMCE_TlbErrorType tlb_error_type:8;
399 uint8_t effective_address_provided;
400 uint8_t reserved_1[6];
401 uint64_t effective_address;
402 uint8_t reserved_2[16];
403 } tlb_error;
404 } u;
405};
406
407enum {
408 OPAL_P7IOC_DIAG_TYPE_NONE = 0,
409 OPAL_P7IOC_DIAG_TYPE_RGC = 1,
410 OPAL_P7IOC_DIAG_TYPE_BI = 2,
411 OPAL_P7IOC_DIAG_TYPE_CI = 3,
412 OPAL_P7IOC_DIAG_TYPE_MISC = 4,
413 OPAL_P7IOC_DIAG_TYPE_I2C = 5,
414 OPAL_P7IOC_DIAG_TYPE_LAST = 6
415};
416
417struct OpalIoP7IOCErrorData {
418 uint16_t type;
419
420 /* GEM */
421 uint64_t gemXfir;
422 uint64_t gemRfir;
423 uint64_t gemRirqfir;
424 uint64_t gemMask;
425 uint64_t gemRwof;
426
427 /* LEM */
428 uint64_t lemFir;
429 uint64_t lemErrMask;
430 uint64_t lemAction0;
431 uint64_t lemAction1;
432 uint64_t lemWof;
433
434 union {
435 struct OpalIoP7IOCRgcErrorData {
436 uint64_t rgcStatus; /* 3E1C10 */
437 uint64_t rgcLdcp; /* 3E1C18 */
438 }rgc;
439 struct OpalIoP7IOCBiErrorData {
440 uint64_t biLdcp0; /* 3C0100, 3C0118 */
441 uint64_t biLdcp1; /* 3C0108, 3C0120 */
442 uint64_t biLdcp2; /* 3C0110, 3C0128 */
443 uint64_t biFenceStatus; /* 3C0130, 3C0130 */
444
445 uint8_t biDownbound; /* BI Downbound or Upbound */
446 }bi;
447 struct OpalIoP7IOCCiErrorData {
448 uint64_t ciPortStatus; /* 3Dn008 */
449 uint64_t ciPortLdcp; /* 3Dn010 */
450
451 uint8_t ciPort; /* Index of CI port: 0/1 */
452 }ci;
453 };
454};
455
456/**
457 * This structure defines the overlay which will be used to store PHB error
458 * data upon request.
459 */
460enum {
461 OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
462};
463
464enum {
465 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
466 OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
467};
468
469enum {
470 OPAL_P7IOC_NUM_PEST_REGS = 128,
471 OPAL_PHB3_NUM_PEST_REGS = 256
472};
473
474struct OpalIoPhbErrorCommon {
475 uint32_t version;
476 uint32_t ioType;
477 uint32_t len;
478};
479
480struct OpalIoP7IOCPhbErrorData {
481 struct OpalIoPhbErrorCommon common;
482
483 uint32_t brdgCtl;
484
485 // P7IOC utl regs
486 uint32_t portStatusReg;
487 uint32_t rootCmplxStatus;
488 uint32_t busAgentStatus;
489
490 // P7IOC cfg regs
491 uint32_t deviceStatus;
492 uint32_t slotStatus;
493 uint32_t linkStatus;
494 uint32_t devCmdStatus;
495 uint32_t devSecStatus;
496
497 // cfg AER regs
498 uint32_t rootErrorStatus;
499 uint32_t uncorrErrorStatus;
500 uint32_t corrErrorStatus;
501 uint32_t tlpHdr1;
502 uint32_t tlpHdr2;
503 uint32_t tlpHdr3;
504 uint32_t tlpHdr4;
505 uint32_t sourceId;
506
507 uint32_t rsv3;
508
509 // Record data about the call to allocate a buffer.
510 uint64_t errorClass;
511 uint64_t correlator;
512
513 //P7IOC MMIO Error Regs
514 uint64_t p7iocPlssr; // n120
515 uint64_t p7iocCsr; // n110
516 uint64_t lemFir; // nC00
517 uint64_t lemErrorMask; // nC18
518 uint64_t lemWOF; // nC40
519 uint64_t phbErrorStatus; // nC80
520 uint64_t phbFirstErrorStatus; // nC88
521 uint64_t phbErrorLog0; // nCC0
522 uint64_t phbErrorLog1; // nCC8
523 uint64_t mmioErrorStatus; // nD00
524 uint64_t mmioFirstErrorStatus; // nD08
525 uint64_t mmioErrorLog0; // nD40
526 uint64_t mmioErrorLog1; // nD48
527 uint64_t dma0ErrorStatus; // nD80
528 uint64_t dma0FirstErrorStatus; // nD88
529 uint64_t dma0ErrorLog0; // nDC0
530 uint64_t dma0ErrorLog1; // nDC8
531 uint64_t dma1ErrorStatus; // nE00
532 uint64_t dma1FirstErrorStatus; // nE08
533 uint64_t dma1ErrorLog0; // nE40
534 uint64_t dma1ErrorLog1; // nE48
535 uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS];
536 uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS];
537};
538
539struct OpalIoPhb3ErrorData {
540 struct OpalIoPhbErrorCommon common;
541
542 uint32_t brdgCtl;
543
544 /* PHB3 UTL regs */
545 uint32_t portStatusReg;
546 uint32_t rootCmplxStatus;
547 uint32_t busAgentStatus;
548
549 /* PHB3 cfg regs */
550 uint32_t deviceStatus;
551 uint32_t slotStatus;
552 uint32_t linkStatus;
553 uint32_t devCmdStatus;
554 uint32_t devSecStatus;
555
556 /* cfg AER regs */
557 uint32_t rootErrorStatus;
558 uint32_t uncorrErrorStatus;
559 uint32_t corrErrorStatus;
560 uint32_t tlpHdr1;
561 uint32_t tlpHdr2;
562 uint32_t tlpHdr3;
563 uint32_t tlpHdr4;
564 uint32_t sourceId;
565
566 uint32_t rsv3;
567
568 /* Record data about the call to allocate a buffer */
569 uint64_t errorClass;
570 uint64_t correlator;
571
572 uint64_t nFir; /* 000 */
573 uint64_t nFirMask; /* 003 */
574 uint64_t nFirWOF; /* 008 */
575
576 /* PHB3 MMIO Error Regs */
577 uint64_t phbPlssr; /* 120 */
578 uint64_t phbCsr; /* 110 */
579 uint64_t lemFir; /* C00 */
580 uint64_t lemErrorMask; /* C18 */
581 uint64_t lemWOF; /* C40 */
582 uint64_t phbErrorStatus; /* C80 */
583 uint64_t phbFirstErrorStatus; /* C88 */
584 uint64_t phbErrorLog0; /* CC0 */
585 uint64_t phbErrorLog1; /* CC8 */
586 uint64_t mmioErrorStatus; /* D00 */
587 uint64_t mmioFirstErrorStatus; /* D08 */
588 uint64_t mmioErrorLog0; /* D40 */
589 uint64_t mmioErrorLog1; /* D48 */
590 uint64_t dma0ErrorStatus; /* D80 */
591 uint64_t dma0FirstErrorStatus; /* D88 */
592 uint64_t dma0ErrorLog0; /* DC0 */
593 uint64_t dma0ErrorLog1; /* DC8 */
594 uint64_t dma1ErrorStatus; /* E00 */
595 uint64_t dma1FirstErrorStatus; /* E08 */
596 uint64_t dma1ErrorLog0; /* E40 */
597 uint64_t dma1ErrorLog1; /* E48 */
598 uint64_t pestA[OPAL_PHB3_NUM_PEST_REGS];
599 uint64_t pestB[OPAL_PHB3_NUM_PEST_REGS];
600};
601
602typedef struct oppanel_line {
603 const char * line;
604 uint64_t line_len;
605} oppanel_line_t;
606
607/* /sys/firmware/opal */
608extern struct kobject *opal_kobj;
609
610/* API functions */
611int64_t opal_console_write(int64_t term_number, __be64 *length,
612 const uint8_t *buffer);
613int64_t opal_console_read(int64_t term_number, __be64 *length,
614 uint8_t *buffer);
615int64_t opal_console_write_buffer_space(int64_t term_number,
616 __be64 *length);
617int64_t opal_rtc_read(__be32 *year_month_day,
618 __be64 *hour_minute_second_millisecond);
619int64_t opal_rtc_write(uint32_t year_month_day,
620 uint64_t hour_minute_second_millisecond);
621int64_t opal_cec_power_down(uint64_t request);
622int64_t opal_cec_reboot(void);
623int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
624int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
625int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
626int64_t opal_poll_events(__be64 *outstanding_event_mask);
627int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
628 uint64_t tce_mem_size);
629int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
630 uint64_t tce_mem_size);
631int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
632 uint64_t offset, uint8_t *data);
633int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
634 uint64_t offset, __be16 *data);
635int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
636 uint64_t offset, __be32 *data);
637int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
638 uint64_t offset, uint8_t data);
639int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
640 uint64_t offset, uint16_t data);
641int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
642 uint64_t offset, uint32_t data);
643int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
644int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
645int64_t opal_register_exception_handler(uint64_t opal_exception,
646 uint64_t handler_address,
647 uint64_t glue_cache_line);
648int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
649 uint8_t *freeze_state,
650 __be16 *pci_error_type,
651 __be64 *phb_status);
652int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
653 uint64_t eeh_action_token);
654int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
655
656
657
658int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
659 uint16_t window_num, uint16_t enable);
660int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
661 uint16_t window_num,
662 uint64_t starting_real_address,
663 uint64_t starting_pci_address,
664 uint16_t segment_size);
665int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
666 uint16_t window_type, uint16_t window_num,
667 uint16_t segment_num);
668int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
669 uint64_t ivt_addr, uint64_t ivt_len,
670 uint64_t reject_array_addr,
671 uint64_t peltv_addr);
672int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
673 uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
674 uint8_t pe_action);
675int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
676 uint8_t state);
677int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
678int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
679 uint32_t state);
680int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
681 uint8_t *p_bit, uint8_t *q_bit);
682int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
683 uint8_t p_bit, uint8_t q_bit);
684int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
685int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
686 uint32_t xive_num);
687int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
688 __be32 *interrupt_source_number);
689int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
690 uint8_t msi_range, __be32 *msi_address,
691 __be32 *message_data);
692int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
693 uint32_t xive_num, uint8_t msi_range,
694 __be64 *msi_address, __be32 *message_data);
695int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
696int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
697int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
698int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
699 uint16_t tce_levels, uint64_t tce_table_addr,
700 uint64_t tce_table_size, uint64_t tce_page_size);
701int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
702 uint16_t dma_window_number, uint64_t pci_start_addr,
703 uint64_t pci_mem_size);
704int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
705
706int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
707 uint64_t diag_buffer_len);
708int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
709 uint64_t diag_buffer_len);
710int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
711 uint64_t diag_buffer_len);
712int64_t opal_pci_fence_phb(uint64_t phb_id);
713int64_t opal_pci_reinit(uint64_t phb_id, uint8_t reinit_scope);
714int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
715int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
716int64_t opal_get_epow_status(__be64 *status);
717int64_t opal_set_system_attention_led(uint8_t led_action);
718int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe,
719 uint16_t *pci_error_type, uint16_t *severity);
720int64_t opal_pci_poll(uint64_t phb_id);
721int64_t opal_return_cpu(void);
722
723int64_t opal_xscom_read(uint32_t gcid, uint32_t pcb_addr, __be64 *val);
724int64_t opal_xscom_write(uint32_t gcid, uint32_t pcb_addr, uint64_t val);
725
726int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
727 uint32_t addr, uint32_t data, uint32_t sz);
728int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
729 uint32_t addr, __be32 *data, uint32_t sz);
730int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
731int64_t opal_manage_flash(uint8_t op);
732int64_t opal_update_flash(uint64_t blk_list);
733
734/* Internal functions */
735extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
736
737extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
738extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
739
740extern void hvc_opal_init_early(void);
741
742/* Internal functions */
743extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
744 int depth, void *data);
745
746extern int opal_notifier_register(struct notifier_block *nb);
747extern void opal_notifier_enable(void);
748extern void opal_notifier_disable(void);
749extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
750
751extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
752extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
753
754extern void hvc_opal_init_early(void);
755
756struct rtc_time;
757extern int opal_set_rtc_time(struct rtc_time *tm);
758extern void opal_get_rtc_time(struct rtc_time *tm);
759extern unsigned long opal_get_boot_time(void);
760extern void opal_nvram_init(void);
761extern void opal_flash_init(void);
762
763extern int opal_machine_check(struct pt_regs *regs);
764
765extern void opal_shutdown(void);
766
767extern void opal_lpc_init(void);
768
769#endif /* __ASSEMBLY__ */
770
771#endif /* __OPAL_H */