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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 2004 Ralf Baechle
7 * Copyright (C) 2004 Maciej W. Rozycki
8 */
9#ifndef __ASM_CPU_FEATURES_H
10#define __ASM_CPU_FEATURES_H
11
12#include <asm/cpu.h>
13#include <asm/cpu-info.h>
14#include <cpu-feature-overrides.h>
15
16/*
17 * SMP assumption: Options of CPU 0 are a superset of all processors.
18 * This is true for all known MIPS systems.
19 */
20#ifndef cpu_has_tlb
21#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
22#endif
23
24/*
25 * For the moment we don't consider R6000 and R8000 so we can assume that
26 * anything that doesn't support R4000-style exceptions and interrupts is
27 * R3000-like. Users should still treat these two macro definitions as
28 * opaque.
29 */
30#ifndef cpu_has_3kex
31#define cpu_has_3kex (!cpu_has_4kex)
32#endif
33#ifndef cpu_has_4kex
34#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
35#endif
36#ifndef cpu_has_3k_cache
37#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
38#endif
39#define cpu_has_6k_cache 0
40#define cpu_has_8k_cache 0
41#ifndef cpu_has_4k_cache
42#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
43#endif
44#ifndef cpu_has_tx39_cache
45#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
46#endif
47#ifndef cpu_has_octeon_cache
48#define cpu_has_octeon_cache 0
49#endif
50#ifndef cpu_has_fpu
51#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
52#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
53#else
54#define raw_cpu_has_fpu cpu_has_fpu
55#endif
56#ifndef cpu_has_32fpr
57#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
58#endif
59#ifndef cpu_has_counter
60#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
61#endif
62#ifndef cpu_has_watch
63#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
64#endif
65#ifndef cpu_has_divec
66#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
67#endif
68#ifndef cpu_has_vce
69#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
70#endif
71#ifndef cpu_has_cache_cdex_p
72#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
73#endif
74#ifndef cpu_has_cache_cdex_s
75#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
76#endif
77#ifndef cpu_has_prefetch
78#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
79#endif
80#ifndef cpu_has_mcheck
81#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
82#endif
83#ifndef cpu_has_ejtag
84#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
85#endif
86#ifndef cpu_has_llsc
87#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
88#endif
89#ifndef kernel_uses_llsc
90#define kernel_uses_llsc cpu_has_llsc
91#endif
92#ifndef cpu_has_mips16
93#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
94#endif
95#ifndef cpu_has_mdmx
96#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
97#endif
98#ifndef cpu_has_mips3d
99#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
100#endif
101#ifndef cpu_has_smartmips
102#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
103#endif
104#ifndef cpu_has_rixi
105#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
106#endif
107#ifndef cpu_has_mmips
108# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
109# define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
110# else
111# define cpu_has_mmips 0
112# endif
113#endif
114#ifndef cpu_has_vtag_icache
115#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
116#endif
117#ifndef cpu_has_dc_aliases
118#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
119#endif
120#ifndef cpu_has_ic_fills_f_dc
121#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
122#endif
123#ifndef cpu_has_pindexed_dcache
124#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
125#endif
126#ifndef cpu_has_local_ebase
127#define cpu_has_local_ebase 1
128#endif
129
130/*
131 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
132 * such as the R10000 have I-Caches that snoop local stores; the embedded ones
133 * don't. For maintaining I-cache coherency this means we need to flush the
134 * D-cache all the way back to whever the I-cache does refills from, so the
135 * I-cache has a chance to see the new data at all. Then we have to flush the
136 * I-cache also.
137 * Note we may have been rescheduled and may no longer be running on the CPU
138 * that did the store so we can't optimize this into only doing the flush on
139 * the local CPU.
140 */
141#ifndef cpu_icache_snoops_remote_store
142#ifdef CONFIG_SMP
143#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
144#else
145#define cpu_icache_snoops_remote_store 1
146#endif
147#endif
148
149#ifndef cpu_has_mips_2
150# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
151#endif
152#ifndef cpu_has_mips_3
153# define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III)
154#endif
155#ifndef cpu_has_mips_4
156# define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
157#endif
158#ifndef cpu_has_mips_5
159# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
160#endif
161#ifndef cpu_has_mips32r1
162# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
163#endif
164#ifndef cpu_has_mips32r2
165# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
166#endif
167#ifndef cpu_has_mips64r1
168# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
169#endif
170#ifndef cpu_has_mips64r2
171# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
172#endif
173
174/*
175 * Shortcuts ...
176 */
177#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2)
178#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)
179#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
180#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
181#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
182 cpu_has_mips64r1 | cpu_has_mips64r2)
183
184#ifndef cpu_has_mips_r2_exec_hazard
185#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
186#endif
187
188/*
189 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
190 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and
191 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
192 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
193 */
194#ifndef cpu_has_clo_clz
195#define cpu_has_clo_clz cpu_has_mips_r
196#endif
197
198#ifndef cpu_has_dsp
199#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
200#endif
201
202#ifndef cpu_has_dsp2
203#define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P)
204#endif
205
206#ifndef cpu_has_mipsmt
207#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
208#endif
209
210#ifndef cpu_has_userlocal
211#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
212#endif
213
214#ifdef CONFIG_32BIT
215# ifndef cpu_has_nofpuex
216# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
217# endif
218# ifndef cpu_has_64bits
219# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
220# endif
221# ifndef cpu_has_64bit_zero_reg
222# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
223# endif
224# ifndef cpu_has_64bit_gp_regs
225# define cpu_has_64bit_gp_regs 0
226# endif
227# ifndef cpu_has_64bit_addresses
228# define cpu_has_64bit_addresses 0
229# endif
230# ifndef cpu_vmbits
231# define cpu_vmbits 31
232# endif
233#endif
234
235#ifdef CONFIG_64BIT
236# ifndef cpu_has_nofpuex
237# define cpu_has_nofpuex 0
238# endif
239# ifndef cpu_has_64bits
240# define cpu_has_64bits 1
241# endif
242# ifndef cpu_has_64bit_zero_reg
243# define cpu_has_64bit_zero_reg 1
244# endif
245# ifndef cpu_has_64bit_gp_regs
246# define cpu_has_64bit_gp_regs 1
247# endif
248# ifndef cpu_has_64bit_addresses
249# define cpu_has_64bit_addresses 1
250# endif
251# ifndef cpu_vmbits
252# define cpu_vmbits cpu_data[0].vmbits
253# define __NEED_VMBITS_PROBE
254# endif
255#endif
256
257#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
258# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
259#elif !defined(cpu_has_vint)
260# define cpu_has_vint 0
261#endif
262
263#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
264# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
265#elif !defined(cpu_has_veic)
266# define cpu_has_veic 0
267#endif
268
269#ifndef cpu_has_inclusive_pcaches
270#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
271#endif
272
273#ifndef cpu_dcache_line_size
274#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
275#endif
276#ifndef cpu_icache_line_size
277#define cpu_icache_line_size() cpu_data[0].icache.linesz
278#endif
279#ifndef cpu_scache_line_size
280#define cpu_scache_line_size() cpu_data[0].scache.linesz
281#endif
282
283#ifndef cpu_hwrena_impl_bits
284#define cpu_hwrena_impl_bits 0
285#endif
286
287#ifndef cpu_has_perf_cntr_intr_bit
288#define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI)
289#endif
290
291#ifndef cpu_has_vz
292#define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ)
293#endif
294
295#endif /* __ASM_CPU_FEATURES_H */