Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> for ST Ericsson.
4 * License terms: GNU General Public License (GPL) version 2
5 */
6#ifndef __AB8500_SYSCTRL_H
7#define __AB8500_SYSCTRL_H
8
9#include <linux/bitops.h>
10
11#ifdef CONFIG_AB8500_CORE
12
13int ab8500_sysctrl_read(u16 reg, u8 *value);
14int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value);
15void ab8500_restart(char mode, const char *cmd);
16
17#else
18
19static inline int ab8500_sysctrl_read(u16 reg, u8 *value)
20{
21 return 0;
22}
23
24static inline int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value)
25{
26 return 0;
27}
28
29#endif /* CONFIG_AB8500_CORE */
30
31static inline int ab8500_sysctrl_set(u16 reg, u8 bits)
32{
33 return ab8500_sysctrl_write(reg, bits, bits);
34}
35
36static inline int ab8500_sysctrl_clear(u16 reg, u8 bits)
37{
38 return ab8500_sysctrl_write(reg, bits, 0);
39}
40
41/* Configuration data for SysClkReq1RfClkBuf - SysClkReq8RfClkBuf */
42struct ab8500_sysctrl_platform_data {
43 u8 initial_req_buf_config[8];
44 u16 (*reboot_reason_code)(const char *cmd);
45};
46
47/* Registers */
48#define AB8500_TURNONSTATUS 0x100
49#define AB8500_RESETSTATUS 0x101
50#define AB8500_PONKEY1PRESSSTATUS 0x102
51#define AB8500_SYSCLKREQSTATUS 0x142
52#define AB8500_STW4500CTRL1 0x180
53#define AB8500_STW4500CTRL2 0x181
54#define AB8500_STW4500CTRL3 0x200
55#define AB8500_MAINWDOGCTRL 0x201
56#define AB8500_MAINWDOGTIMER 0x202
57#define AB8500_LOWBAT 0x203
58#define AB8500_BATTOK 0x204
59#define AB8500_SYSCLKTIMER 0x205
60#define AB8500_SMPSCLKCTRL 0x206
61#define AB8500_SMPSCLKSEL1 0x207
62#define AB8500_SMPSCLKSEL2 0x208
63#define AB8500_SMPSCLKSEL3 0x209
64#define AB8500_SYSULPCLKCONF 0x20A
65#define AB8500_SYSULPCLKCTRL1 0x20B
66#define AB8500_SYSCLKCTRL 0x20C
67#define AB8500_SYSCLKREQ1VALID 0x20D
68#define AB8500_SYSTEMCTRLSUP 0x20F
69#define AB8500_SYSCLKREQ1RFCLKBUF 0x210
70#define AB8500_SYSCLKREQ2RFCLKBUF 0x211
71#define AB8500_SYSCLKREQ3RFCLKBUF 0x212
72#define AB8500_SYSCLKREQ4RFCLKBUF 0x213
73#define AB8500_SYSCLKREQ5RFCLKBUF 0x214
74#define AB8500_SYSCLKREQ6RFCLKBUF 0x215
75#define AB8500_SYSCLKREQ7RFCLKBUF 0x216
76#define AB8500_SYSCLKREQ8RFCLKBUF 0x217
77#define AB8500_DITHERCLKCTRL 0x220
78#define AB8500_SWATCTRL 0x230
79#define AB8500_HIQCLKCTRL 0x232
80#define AB8500_VSIMSYSCLKCTRL 0x233
81#define AB9540_SYSCLK12BUFCTRL 0x234
82#define AB9540_SYSCLK12CONFCTRL 0x235
83#define AB9540_SYSCLK12BUFCTRL2 0x236
84#define AB9540_SYSCLK12BUF1VALID 0x237
85#define AB9540_SYSCLK12BUF2VALID 0x238
86#define AB9540_SYSCLK12BUF3VALID 0x239
87#define AB9540_SYSCLK12BUF4VALID 0x23A
88
89/* Bits */
90#define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
91#define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1)
92#define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2)
93#define AB8500_TURNONSTATUS_RTCALARM BIT(3)
94#define AB8500_TURNONSTATUS_MAINCHDET BIT(4)
95#define AB8500_TURNONSTATUS_VBUSDET BIT(5)
96#define AB8500_TURNONSTATUS_USBIDDETECT BIT(6)
97
98#define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0)
99#define AB8500_RESETSTATUS_SWRESETN4500NSTATUS BIT(2)
100
101#define AB8500_PONKEY1PRESSSTATUS_PONKEY1PRESSTIME_MASK 0x7F
102#define AB8500_PONKEY1PRESSSTATUS_PONKEY1PRESSTIME_SHIFT 0
103
104#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ1STATUS BIT(0)
105#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ2STATUS BIT(1)
106#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ3STATUS BIT(2)
107#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ4STATUS BIT(3)
108#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ5STATUS BIT(4)
109#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ6STATUS BIT(5)
110#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ7STATUS BIT(6)
111#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ8STATUS BIT(7)
112
113#define AB8500_STW4500CTRL1_SWOFF BIT(0)
114#define AB8500_STW4500CTRL1_SWRESET4500N BIT(1)
115#define AB8500_STW4500CTRL1_THDB8500SWOFF BIT(2)
116
117#define AB8500_STW4500CTRL2_RESETNVAUX1VALID BIT(0)
118#define AB8500_STW4500CTRL2_RESETNVAUX2VALID BIT(1)
119#define AB8500_STW4500CTRL2_RESETNVAUX3VALID BIT(2)
120#define AB8500_STW4500CTRL2_RESETNVMODVALID BIT(3)
121#define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY1VALID BIT(4)
122#define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY2VALID BIT(5)
123#define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY3VALID BIT(6)
124#define AB8500_STW4500CTRL2_RESETNVSMPS1VALID BIT(7)
125
126#define AB8500_STW4500CTRL3_CLK32KOUT2DIS BIT(0)
127#define AB8500_STW4500CTRL3_RESETAUDN BIT(1)
128#define AB8500_STW4500CTRL3_RESETDENCN BIT(2)
129#define AB8500_STW4500CTRL3_THSDENA BIT(3)
130
131#define AB8500_MAINWDOGCTRL_MAINWDOGENA BIT(0)
132#define AB8500_MAINWDOGCTRL_MAINWDOGKICK BIT(1)
133#define AB8500_MAINWDOGCTRL_WDEXPTURNONVALID BIT(4)
134
135#define AB8500_MAINWDOGTIMER_MAINWDOGTIMER_MASK 0x7F
136#define AB8500_MAINWDOGTIMER_MAINWDOGTIMER_SHIFT 0
137
138#define AB8500_LOWBAT_LOWBATENA BIT(0)
139#define AB8500_LOWBAT_LOWBAT_MASK 0x7E
140#define AB8500_LOWBAT_LOWBAT_SHIFT 1
141
142#define AB8500_BATTOK_BATTOKSEL0THF_MASK 0x0F
143#define AB8500_BATTOK_BATTOKSEL0THF_SHIFT 0
144#define AB8500_BATTOK_BATTOKSEL1THF_MASK 0xF0
145#define AB8500_BATTOK_BATTOKSEL1THF_SHIFT 4
146
147#define AB8500_SYSCLKTIMER_SYSCLKTIMER_MASK 0x0F
148#define AB8500_SYSCLKTIMER_SYSCLKTIMER_SHIFT 0
149#define AB8500_SYSCLKTIMER_SYSCLKTIMERADJ_MASK 0xF0
150#define AB8500_SYSCLKTIMER_SYSCLKTIMERADJ_SHIFT 4
151
152#define AB8500_SMPSCLKCTRL_SMPSCLKINTSEL_MASK 0x03
153#define AB8500_SMPSCLKCTRL_SMPSCLKINTSEL_SHIFT 0
154#define AB8500_SMPSCLKCTRL_3M2CLKINTENA BIT(2)
155
156#define AB8500_SMPSCLKSEL1_VARMCLKSEL_MASK 0x07
157#define AB8500_SMPSCLKSEL1_VARMCLKSEL_SHIFT 0
158#define AB8500_SMPSCLKSEL1_VAPECLKSEL_MASK 0x38
159#define AB8500_SMPSCLKSEL1_VAPECLKSEL_SHIFT 3
160
161#define AB8500_SMPSCLKSEL2_VMODCLKSEL_MASK 0x07
162#define AB8500_SMPSCLKSEL2_VMODCLKSEL_SHIFT 0
163#define AB8500_SMPSCLKSEL2_VSMPS1CLKSEL_MASK 0x38
164#define AB8500_SMPSCLKSEL2_VSMPS1CLKSEL_SHIFT 3
165
166#define AB8500_SMPSCLKSEL3_VSMPS2CLKSEL_MASK 0x07
167#define AB8500_SMPSCLKSEL3_VSMPS2CLKSEL_SHIFT 0
168#define AB8500_SMPSCLKSEL3_VSMPS3CLKSEL_MASK 0x38
169#define AB8500_SMPSCLKSEL3_VSMPS3CLKSEL_SHIFT 3
170
171#define AB8500_SYSULPCLKCONF_ULPCLKCONF_MASK 0x03
172#define AB8500_SYSULPCLKCONF_ULPCLKCONF_SHIFT 0
173#define AB8500_SYSULPCLKCONF_CLK27MHZSTRE BIT(2)
174#define AB8500_SYSULPCLKCONF_TVOUTCLKDELN BIT(3)
175#define AB8500_SYSULPCLKCONF_TVOUTCLKINV BIT(4)
176#define AB8500_SYSULPCLKCONF_ULPCLKSTRE BIT(5)
177#define AB8500_SYSULPCLKCONF_CLK27MHZBUFENA BIT(6)
178#define AB8500_SYSULPCLKCONF_CLK27MHZPDENA BIT(7)
179
180#define AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_MASK 0x03
181#define AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_SHIFT 0
182#define AB8500_SYSULPCLKCTRL1_ULPCLKREQ BIT(2)
183#define AB8500_SYSULPCLKCTRL1_4500SYSCLKREQ BIT(3)
184#define AB8500_SYSULPCLKCTRL1_AUDIOCLKENA BIT(4)
185#define AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ BIT(5)
186#define AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ BIT(6)
187#define AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ BIT(7)
188
189#define AB8500_SYSCLKCTRL_TVOUTPLLENA BIT(0)
190#define AB8500_SYSCLKCTRL_TVOUTCLKENA BIT(1)
191#define AB8500_SYSCLKCTRL_USBCLKENA BIT(2)
192
193#define AB8500_SYSCLKREQ1VALID_SYSCLKREQ1VALID BIT(0)
194#define AB8500_SYSCLKREQ1VALID_ULPCLKREQ1VALID BIT(1)
195#define AB8500_SYSCLKREQ1VALID_USBSYSCLKREQ1VALID BIT(2)
196
197#define AB8500_SYSTEMCTRLSUP_EXTSUP12LPNCLKSEL_MASK 0x03
198#define AB8500_SYSTEMCTRLSUP_EXTSUP12LPNCLKSEL_SHIFT 0
199#define AB8500_SYSTEMCTRLSUP_EXTSUP3LPNCLKSEL_MASK 0x0C
200#define AB8500_SYSTEMCTRLSUP_EXTSUP3LPNCLKSEL_SHIFT 2
201#define AB8500_SYSTEMCTRLSUP_INTDB8500NOD BIT(4)
202
203#define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF2 BIT(2)
204#define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF3 BIT(3)
205#define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF4 BIT(4)
206
207#define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF2 BIT(2)
208#define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF3 BIT(3)
209#define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF4 BIT(4)
210
211#define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF2 BIT(2)
212#define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF3 BIT(3)
213#define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF4 BIT(4)
214
215#define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF2 BIT(2)
216#define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF3 BIT(3)
217#define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF4 BIT(4)
218
219#define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF2 BIT(2)
220#define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF3 BIT(3)
221#define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF4 BIT(4)
222
223#define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF2 BIT(2)
224#define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF3 BIT(3)
225#define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF4 BIT(4)
226
227#define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF2 BIT(2)
228#define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF3 BIT(3)
229#define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF4 BIT(4)
230
231#define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF2 BIT(2)
232#define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF3 BIT(3)
233#define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF4 BIT(4)
234
235#define AB8500_DITHERCLKCTRL_VARMDITHERENA BIT(0)
236#define AB8500_DITHERCLKCTRL_VSMPS3DITHERENA BIT(1)
237#define AB8500_DITHERCLKCTRL_VSMPS1DITHERENA BIT(2)
238#define AB8500_DITHERCLKCTRL_VSMPS2DITHERENA BIT(3)
239#define AB8500_DITHERCLKCTRL_VMODDITHERENA BIT(4)
240#define AB8500_DITHERCLKCTRL_VAPEDITHERENA BIT(5)
241#define AB8500_DITHERCLKCTRL_DITHERDEL_MASK 0xC0
242#define AB8500_DITHERCLKCTRL_DITHERDEL_SHIFT 6
243
244#define AB8500_SWATCTRL_UPDATERF BIT(0)
245#define AB8500_SWATCTRL_SWATENABLE BIT(1)
246#define AB8500_SWATCTRL_RFOFFTIMER_MASK 0x1C
247#define AB8500_SWATCTRL_RFOFFTIMER_SHIFT 2
248#define AB8500_SWATCTRL_SWATBIT5 BIT(6)
249
250#define AB8500_HIQCLKCTRL_SYSCLKREQ1HIQENAVALID BIT(0)
251#define AB8500_HIQCLKCTRL_SYSCLKREQ2HIQENAVALID BIT(1)
252#define AB8500_HIQCLKCTRL_SYSCLKREQ3HIQENAVALID BIT(2)
253#define AB8500_HIQCLKCTRL_SYSCLKREQ4HIQENAVALID BIT(3)
254#define AB8500_HIQCLKCTRL_SYSCLKREQ5HIQENAVALID BIT(4)
255#define AB8500_HIQCLKCTRL_SYSCLKREQ6HIQENAVALID BIT(5)
256#define AB8500_HIQCLKCTRL_SYSCLKREQ7HIQENAVALID BIT(6)
257#define AB8500_HIQCLKCTRL_SYSCLKREQ8HIQENAVALID BIT(7)
258
259#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ1VALID BIT(0)
260#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ2VALID BIT(1)
261#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ3VALID BIT(2)
262#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ4VALID BIT(3)
263#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ5VALID BIT(4)
264#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ6VALID BIT(5)
265#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ7VALID BIT(6)
266#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ8VALID BIT(7)
267
268#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1ENA BIT(0)
269#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2ENA BIT(1)
270#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3ENA BIT(2)
271#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4ENA BIT(3)
272#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFENA_MASK 0x0F
273#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1STRE BIT(4)
274#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2STRE BIT(5)
275#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3STRE BIT(6)
276#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4STRE BIT(7)
277#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFSTRE_MASK 0xF0
278
279#define AB9540_SYSCLK12CONFCTRL_PLL26TO38ENA BIT(0)
280#define AB9540_SYSCLK12CONFCTRL_SYSCLK12USBMUXSEL BIT(1)
281#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL0 BIT(2)
282#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL1 BIT(3)
283#define AB9540_SYSCLK12CONFCTRL_SYSCLK12BUFMUX BIT(4)
284#define AB9540_SYSCLK12CONFCTRL_SYSCLK12PLLMUX BIT(5)
285#define AB9540_SYSCLK12CONFCTRL_SYSCLK2MUXVALID BIT(6)
286
287#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF1PDENA BIT(0)
288#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF2PDENA BIT(1)
289#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF3PDENA BIT(2)
290#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF4PDENA BIT(3)
291
292#define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_MASK 0xFF
293#define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_SHIFT 0
294
295#define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_MASK 0xFF
296#define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_SHIFT 0
297
298#define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_MASK 0xFF
299#define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_SHIFT 0
300
301#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_MASK 0xFF
302#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_SHIFT 0
303
304#define AB8500_ENABLE_WD 0x1
305#define AB8500_KICK_WD 0x2
306#define AB8500_WD_RESTART_ON_EXPIRE 0x10
307
308#endif /* __AB8500_SYSCTRL_H */