tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Freescale eSDHC controller driver generics for OF and pltfm.
3 *
4 * Copyright (c) 2007 Freescale Semiconductor, Inc.
5 * Copyright (c) 2009 MontaVista Software, Inc.
6 * Copyright (c) 2010 Pengutronix e.K.
7 * Author: Wolfram Sang <w.sang@pengutronix.de>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 */
13
14#ifndef _DRIVERS_MMC_SDHCI_ESDHC_H
15#define _DRIVERS_MMC_SDHCI_ESDHC_H
16
17/*
18 * Ops and quirks for the Freescale eSDHC controller.
19 */
20
21#define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
22 SDHCI_QUIRK_NO_BUSY_IRQ | \
23 SDHCI_QUIRK_NONSTANDARD_CLOCK | \
24 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
25 SDHCI_QUIRK_PIO_NEEDS_DELAY | \
26 SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
27
28#define ESDHC_SYSTEM_CONTROL 0x2c
29#define ESDHC_CLOCK_MASK 0x0000fff0
30#define ESDHC_PREDIV_SHIFT 8
31#define ESDHC_DIVIDER_SHIFT 4
32#define ESDHC_CLOCK_PEREN 0x00000004
33#define ESDHC_CLOCK_HCKEN 0x00000002
34#define ESDHC_CLOCK_IPGEN 0x00000001
35
36/* pltfm-specific */
37#define ESDHC_HOST_CONTROL_LE 0x20
38
39/*
40 * P2020 interpretation of the SDHCI_HOST_CONTROL register
41 */
42#define ESDHC_CTRL_4BITBUS (0x1 << 1)
43#define ESDHC_CTRL_8BITBUS (0x2 << 1)
44#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
45
46/* OF-specific */
47#define ESDHC_DMA_SYSCTL 0x40c
48#define ESDHC_DMA_SNOOP 0x00000040
49
50#define ESDHC_HOST_CONTROL_RES 0x05
51
52static inline void esdhc_set_clock(struct sdhci_host *host, unsigned int clock,
53 unsigned int host_clock)
54{
55 int pre_div = 2;
56 int div = 1;
57 u32 temp;
58
59 if (clock == 0)
60 goto out;
61
62 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
63 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
64 | ESDHC_CLOCK_MASK);
65 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
66
67 while (host_clock / pre_div / 16 > clock && pre_div < 256)
68 pre_div *= 2;
69
70 while (host_clock / pre_div / div > clock && div < 16)
71 div++;
72
73 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
74 clock, host_clock / pre_div / div);
75
76 pre_div >>= 1;
77 div--;
78
79 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
80 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
81 | (div << ESDHC_DIVIDER_SHIFT)
82 | (pre_div << ESDHC_PREDIV_SHIFT));
83 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
84 mdelay(1);
85out:
86 host->clock = clock;
87}
88
89#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */