tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* Copyright (C) 2003-2005 SBE, Inc.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
16#include <linux/io.h>
17#include <linux/hdlc.h>
18#include "pmcc4_sysdep.h"
19#include "sbecom_inline_linux.h"
20#include "libsbew.h"
21#include "pmcc4.h"
22#include "comet.h"
23#include "comet_tables.h"
24
25#ifdef SBE_INCLUDE_SYMBOLS
26#define STATIC
27#else
28#define STATIC static
29#endif
30
31
32extern int cxt1e1_log_level;
33
34#define COMET_NUM_SAMPLES 24 /* Number of entries in the waveform table */
35#define COMET_NUM_UNITS 5 /* Number of points per entry in table */
36
37/* forward references */
38STATIC void SetPwrLevel(comet_t *comet);
39STATIC void WrtRcvEqualizerTbl(ci_t *ci, comet_t *comet, u_int32_t *table);
40STATIC void WrtXmtWaveformTbl(ci_t *ci, comet_t *comet, u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS]);
41
42
43void *TWV_table[12] = {
44 TWVLongHaul0DB, TWVLongHaul7_5DB, TWVLongHaul15DB, TWVLongHaul22_5DB,
45 TWVShortHaul0, TWVShortHaul1, TWVShortHaul2, TWVShortHaul3,
46 TWVShortHaul4, TWVShortHaul5,
47 /** PORT POINT - 75 Ohm not supported **/
48 TWV_E1_75Ohm,
49 TWV_E1_120Ohm
50};
51
52
53static int
54lbo_tbl_lkup(int t1, int lbo) {
55 /* error switches to default */
56 if ((lbo < CFG_LBO_LH0) || (lbo > CFG_LBO_E120)) {
57 if (t1)
58 /* default T1 waveform table */
59 lbo = CFG_LBO_LH0;
60 else
61 /* default E1 waveform table */
62 lbo = CFG_LBO_E120;
63 }
64 /* make index ZERO relative */
65 return lbo - 1;
66}
67
68void init_comet(void *ci, comet_t *comet, u_int32_t port_mode, int clockmaster,
69 u_int8_t moreParams)
70{
71 u_int8_t isT1mode;
72 /* T1 default */
73 u_int8_t tix = CFG_LBO_LH0;
74 isT1mode = IS_FRAME_ANY_T1(port_mode);
75 /* T1 or E1 */
76 if (isT1mode) {
77 /* Select T1 Mode & PIO output enabled */
78 pci_write_32((u_int32_t *) &comet->gbl_cfg, 0xa0);
79 /* default T1 waveform table */
80 tix = lbo_tbl_lkup(isT1mode, CFG_LBO_LH0);
81 } else {
82 /* Select E1 Mode & PIO output enabled */
83 pci_write_32((u_int32_t *) &comet->gbl_cfg, 0x81);
84 /* default E1 waveform table */
85 tix = lbo_tbl_lkup(isT1mode, CFG_LBO_E120);
86 }
87
88 if (moreParams & CFG_LBO_MASK)
89 /* dial-in requested waveform table */
90 tix = lbo_tbl_lkup(isT1mode, moreParams & CFG_LBO_MASK);
91 /* Tx line Intfc cfg Set for analog & no special patterns */
92 /* Transmit Line Interface Config. */
93 pci_write_32((u_int32_t *) &comet->tx_line_cfg, 0x00);
94 /* master test Ignore Test settings for now */
95 /* making sure it's Default value */
96 pci_write_32((u_int32_t *) &comet->mtest, 0x00);
97 /* Turn on Center (CENT) and everything else off */
98 /* RJAT cfg */
99 pci_write_32((u_int32_t *) &comet->rjat_cfg, 0x10);
100 /* Set Jitter Attenuation to recommend T1 values */
101 if (isT1mode) {
102 /* RJAT Divider N1 Control */
103 pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0x2F);
104 /* RJAT Divider N2 Control */
105 pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0x2F);
106 } else {
107 /* RJAT Divider N1 Control */
108 pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0xFF);
109 /* RJAT Divider N2 Control */
110 pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0xFF);
111 }
112
113 /* Turn on Center (CENT) and everything else off */
114 /* TJAT Config. */
115 pci_write_32((u_int32_t *) &comet->tjat_cfg, 0x10);
116
117 /* Do not bypass jitter attenuation and bypass elastic store */
118 /* rx opts */
119 pci_write_32((u_int32_t *) &comet->rx_opt, 0x00);
120
121 /* TJAT ctrl & TJAT divider ctrl */
122 /* Set Jitter Attenuation to recommended T1 values */
123 if (isT1mode) {
124 /* TJAT Divider N1 Control */
125 pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0x2F);
126 /* TJAT Divider N2 Control */
127 pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0x2F);
128 } else {
129 /* TJAT Divider N1 Control */
130 pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0xFF);
131 /* TJAT Divider N2 Control */
132 pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0xFF);
133 }
134
135 /* 1c: rx ELST cfg 20: tx ELST cfg 28&38: rx&tx data link ctrl */
136
137 /* Select 193-bit frame format */
138 if (isT1mode) {
139 pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x00);
140 pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x00);
141 } else {
142 /* Select 256-bit frame format */
143 pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x03);
144 pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x03);
145 /* disable T1 data link receive */
146 pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x00);
147 /* disable T1 data link transmit */
148 pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x00);
149 }
150
151 /* the following is a default value */
152 /* Enable 8 out of 10 validation */
153 /* t1RBOC enable(BOC:BitOriented Code) */
154 pci_write_32((u_int32_t *) &comet->t1_rboc_ena, 0x00);
155 if (isT1mode)
156 {
157
158 /* IBCD cfg: aka Inband Code Detection ** loopback code length set to */
159 /* 6 bit down, 5 bit up (assert) */
160 pci_write_32((u_int32_t *) &comet->ibcd_cfg, 0x04);
161 /* line loopback activate pattern */
162 pci_write_32((u_int32_t *) &comet->ibcd_act, 0x08);
163 /* deactivate code pattern (i.e.001) */
164 pci_write_32((u_int32_t *) &comet->ibcd_deact, 0x24);
165 }
166 /* 10: CDRC cfg 28&38: rx&tx data link 1 ctrl 48: t1 frmr cfg */
167 /* 50: SIGX cfg, COSS (change of signaling state) 54: XBAS cfg */
168 /* 60: t1 ALMI cfg */
169 /* Configure Line Coding */
170
171 switch (port_mode)
172 {
173 /* 1 - T1 B8ZS */
174 case CFG_FRAME_SF:
175 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
176 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
177 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
178 /* 5:B8ZS */
179 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x20);
180 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
181 break;
182 /* 2 - T1 B8ZS */
183 case CFG_FRAME_ESF:
184 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
185 /* Bit 5: T1 DataLink Enable */
186 pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20);
187 /* 5: T1 DataLink Enable */
188 pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20);
189 /* 4:ESF 5:ESFFA */
190 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30);
191 /* 2:ESF */
192 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04);
193 /* 4:ESF 5:B8ZS */
194 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x30);
195 /* 4:ESF */
196 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10);
197 break;
198 /* 3 - HDB3 */
199 case CFG_FRAME_E1PLAIN:
200 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
201 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
202 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0);
203 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
204 break;
205 /* 4 - HDB3 */
206 case CFG_FRAME_E1CAS:
207 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
208 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
209 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x60);
210 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
211 break;
212 /* 5 - HDB3 */
213 case CFG_FRAME_E1CRC:
214 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
215 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
216 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x10);
217 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
218 break;
219 /* 6 - HDB3 */
220 case CFG_FRAME_E1CRC_CAS:
221 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
222 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
223 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x70);
224 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
225 break;
226 /* 7 - T1 AMI */
227 case CFG_FRAME_SF_AMI:
228 /* Enable AMI Line Decoding */
229 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
230 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
231 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0);
232 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
233 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
234 break;
235 /* 8 - T1 AMI */
236 case CFG_FRAME_ESF_AMI:
237 /* Enable AMI Line Decoding */
238 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
239 /* 5: T1 DataLink Enable */
240 pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20);
241 /* 5: T1 DataLink Enable */
242 pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20);
243 /* Bit 4:ESF 5:ESFFA */
244 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30);
245 /* 2:ESF */
246 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04);
247 /* 4:ESF */
248 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x10);
249 /* 4:ESF */
250 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10);
251 break;
252 /* 9 - AMI */
253 case CFG_FRAME_E1PLAIN_AMI:
254 /* Enable AMI Line Decoding */
255 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
256 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
257 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x80);
258 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
259 break;
260 /* 10 - AMI */
261 case CFG_FRAME_E1CAS_AMI:
262 /* Enable AMI Line Decoding */
263 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
264 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
265 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xe0);
266 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
267 break;
268 /* 11 - AMI */
269 case CFG_FRAME_E1CRC_AMI:
270 /* Enable AMI Line Decoding */
271 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
272 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
273 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x90);
274 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
275 break;
276 /* 12 - AMI */
277 case CFG_FRAME_E1CRC_CAS_AMI:
278 /* Enable AMI Line Decoding */
279 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
280 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
281 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xf0);
282 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
283 break;
284 } /* end switch */
285
286 /***
287 * Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0)
288 * CMODE=1: Clock slave mode with BRCLK as an input,
289 * DE=0: Use falling edge of BRCLK for data,
290 * FE=0: Use falling edge of BRCLK for frame,
291 * CMS=0: Use backplane freq,
292 * RATE[1:0]=0,0: T1
293 ***/
294
295
296 /* 0x30: "BRIF cfg"; 0x20 is 'CMODE', 0x03 is (bit) rate */
297 /* note "rate bits can only be set once after reset" */
298 if (clockmaster)
299 {
300 /* CMODE == clockMode, 0=clock master (so all 3 others should be slave) */
301 /* rate = 1.544 Mb/s */
302 if (isT1mode)
303 /* Comet 0 Master Mode(CMODE=0) */
304 pci_write_32((u_int32_t *) &comet->brif_cfg, 0x00);
305 /* rate = 2.048 Mb/s */
306 else
307 /* Comet 0 Master Mode(CMODE=0) */
308 pci_write_32((u_int32_t *) &comet->brif_cfg, 0x01);
309
310 /* 31: BRIF frame pulse cfg 06: tx timing options */
311
312 /* Master Mode i.e.FPMODE=0 (@0x20) */
313 pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x00);
314 if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL)
315 {
316 if (cxt1e1_log_level >= LOG_SBEBUG12)
317 pr_info(">> %s: clockmaster internal clock\n", __func__);
318 /* internal oscillator */
319 pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
320 } else {
321 /* external clock source */
322 if (cxt1e1_log_level >= LOG_SBEBUG12)
323 pr_info(">> %s: clockmaster external clock\n", __func__);
324 /* loop timing(external) */
325 pci_write_32((u_int32_t *) &comet->tx_time, 0x09);
326 }
327
328 } else {
329 /* slave */
330 if (isT1mode)
331 /* Slave Mode(CMODE=1, see above) */
332 pci_write_32((u_int32_t *) &comet->brif_cfg, 0x20);
333 else
334 /* Slave Mode(CMODE=1)*/
335 pci_write_32((u_int32_t *) &comet->brif_cfg, 0x21);
336 /* Slave Mode i.e. FPMODE=1 (@0x20) */
337 pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x20);
338 if (cxt1e1_log_level >= LOG_SBEBUG12)
339 pr_info(">> %s: clockslave internal clock\n", __func__);
340 /* oscillator timing */
341 pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
342 }
343
344 /* 32: BRIF parity F-bit cfg */
345 /* Totem-pole operation */
346 /* Receive Backplane Parity/F-bit */
347 pci_write_32((u_int32_t *) &comet->brif_pfcfg, 0x01);
348
349 /* dc: RLPS equalizer V ref */
350 /* Configuration */
351 if (isT1mode)
352 /* RLPS Equalizer Voltage */
353 pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x2c);
354 else
355 /* RLPS Equalizer Voltage */
356 pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x34);
357
358 /* Reserved bit set and SQUELCH enabled */
359 /* f8: RLPS cfg & status f9: RLPS ALOS detect/clear threshold */
360 /* RLPS Configuration Status */
361 pci_write_32((u_int32_t *) &comet->rlps_cfgsts, 0x11);
362 if (isT1mode)
363 /* ? */
364 pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x55);
365 else
366 /* ? */
367 pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x22);
368
369
370 /* Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0) */
371 /* CMODE=0: Clock slave mode with BTCLK as an input, DE=1: Use rising */
372 /* edge of BTCLK for data, FE=1: Use rising edge of BTCLK for frame, */
373 /* CMS=0: Use backplane freq, RATE[1:0]=0,0: T1 */
374 /*** Transmit side is always an Input, Slave Clock*/
375 /* 40: BTIF cfg 41: loop timing(external) */
376 /*BTIF frame pulse cfg */
377 if (isT1mode)
378 /* BTIF Configuration Reg. */
379 pci_write_32((u_int32_t *) &comet->btif_cfg, 0x38);
380 else
381 /* BTIF Configuration Reg. */
382 pci_write_32((u_int32_t *) &comet->btif_cfg, 0x39);
383 /* BTIF Frame Pulse Config. */
384 pci_write_32((u_int32_t *) &comet->btif_fpcfg, 0x01);
385
386 /* 0a: master diag 06: tx timing options */
387 /* if set Comet to loop back */
388
389 /* Comets set to normal */
390 pci_write_32((u_int32_t *) &comet->mdiag, 0x00);
391
392 /* BTCLK driven by TCLKI internally (crystal driven) and Xmt Elasted */
393 /* Store is enabled. */
394
395 WrtXmtWaveformTbl(ci, comet, TWV_table[tix]);
396 if (isT1mode)
397 WrtRcvEqualizerTbl((ci_t *) ci, comet, &T1_Equalizer[0]);
398 else
399 WrtRcvEqualizerTbl((ci_t *) ci, comet, &E1_Equalizer[0]);
400 SetPwrLevel(comet);
401}
402
403/*
404** Name: WrtXmtWaveform
405** Description: Formulate the Data for the Pulse Waveform Storage
406** Write register, (F2), from the sample and unit inputs.
407** Write the data to the Pulse Waveform Storage Data register.
408** Returns: Nothing
409*/
410STATIC void
411WrtXmtWaveform(ci_t *ci, comet_t *comet, u_int32_t sample, u_int32_t unit, u_int8_t data)
412{
413 u_int8_t WaveformAddr;
414
415 WaveformAddr = (sample << 3) + (unit & 7);
416 pci_write_32((u_int32_t *) &comet->xlpg_pwave_addr, WaveformAddr);
417 /* for write order preservation when Optimizing driver */
418 pci_flush_write(ci);
419 pci_write_32((u_int32_t *) &comet->xlpg_pwave_data, 0x7F & data);
420}
421
422/*
423** Name: WrtXmtWaveformTbl
424** Description: Fill in the Transmit Waveform Values
425** for driving the transmitter DAC.
426** Returns: Nothing
427*/
428STATIC void
429WrtXmtWaveformTbl(ci_t *ci, comet_t *comet,
430 u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS])
431{
432 u_int32_t sample, unit;
433
434 for (sample = 0; sample < COMET_NUM_SAMPLES; sample++)
435 {
436 for (unit = 0; unit < COMET_NUM_UNITS; unit++)
437 WrtXmtWaveform(ci, comet, sample, unit, table[sample][unit]);
438 }
439
440 /* Enable transmitter and set output amplitude */
441 pci_write_32((u_int32_t *) &comet->xlpg_cfg, table[COMET_NUM_SAMPLES][0]);
442}
443
444
445/*
446** Name: WrtXmtWaveform
447** Description: Fill in the Receive Equalizer RAM from the desired
448** table.
449** Returns: Nothing
450**
451** Remarks: Per PM4351 Device Errata, Receive Equalizer RAM Initialization
452** is coded with early setup of indirect address.
453*/
454
455STATIC void
456WrtRcvEqualizerTbl(ci_t *ci, comet_t *comet, u_int32_t *table)
457{
458 u_int32_t ramaddr;
459 volatile u_int32_t value;
460
461 for (ramaddr = 0; ramaddr < 256; ramaddr++) {
462 /*** the following lines are per Errata 7, 2.5 ***/
463 {
464 /* Set up for a read operation */
465 pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0x80);
466 /* for write order preservation when Optimizing driver */
467 pci_flush_write(ci);
468 /* write the addr, initiate a read */
469 pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr);
470 /* for write order preservation when Optimizing driver */
471 pci_flush_write(ci);
472 /*
473 * wait 3 line rate clock cycles to ensure address bits are
474 * captured by T1/E1 clock
475 */
476
477 /* 683ns * 3 = 1366 ns, approx 2us (but use 4us) */
478 OS_uwait(4, "wret");
479 }
480
481 value = *table++;
482 pci_write_32((u_int32_t *) &comet->rlps_idata3, (u_int8_t) (value >> 24));
483 pci_write_32((u_int32_t *) &comet->rlps_idata2, (u_int8_t) (value >> 16));
484 pci_write_32((u_int32_t *) &comet->rlps_idata1, (u_int8_t) (value >> 8));
485 pci_write_32((u_int32_t *) &comet->rlps_idata0, (u_int8_t) value);
486 /* for write order preservation when Optimizing driver */
487 pci_flush_write(ci);
488
489 /* Storing RAM address, causes RAM to be updated */
490
491 /* Set up for a write operation */
492 pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0);
493 /* for write order preservation when optimizing driver */
494 pci_flush_write(ci);
495 /* write the addr, initiate a read */
496 pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr);
497 /* for write order preservation when optimizing driver */
498 pci_flush_write(ci);
499
500 /*
501 * wait 3 line rate clock cycles to ensure address bits are captured
502 * by T1/E1 clock
503 */
504 /* 683ns * 3 = 1366 ns, approx 2us (but use 4us) */
505 OS_uwait(4, "wret");
506 }
507
508 /* Enable Equalizer & set it to use 256 periods */
509 pci_write_32((u_int32_t *) &comet->rlps_eq_cfg, 0xCB);
510}
511
512
513/*
514** Name: SetPwrLevel
515** Description: Implement power level setting algorithm described below
516** Returns: Nothing
517*/
518
519STATIC void
520SetPwrLevel(comet_t *comet)
521{
522 volatile u_int32_t temp;
523
524/*
525** Algorithm to Balance the Power Distribution of Ttip Tring
526**
527** Zero register F6
528** Write 0x01 to register F4
529** Write another 0x01 to register F4
530** Read register F4
531** Remove the 0x01 bit by Anding register F4 with 0xFE
532** Write the resultant value to register F4
533** Repeat these steps for register F5
534** Write 0x01 to register F6
535*/
536 /* XLPG Fuse Data Select */
537 pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x00);
538 /* XLPG Analog Test Positive control */
539 pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
540 pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
541 temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_pctl) & 0xfe;
542 pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, temp);
543 pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
544 pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
545 /* XLPG Analog Test Negative control */
546 temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_nctl) & 0xfe;
547 pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, temp);
548 /* XLPG */
549 pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x01);
550}
551
552
553/*
554** Name: SetCometOps
555** Description: Set up the selected Comet's clock edge drive for both
556** the transmit out the analog side and receive to the
557** backplane side.
558** Returns: Nothing
559*/
560#if 0
561STATIC void
562SetCometOps(comet_t *comet)
563{
564 volatile u_int8_t rd_value;
565
566 if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2))
567 {
568 /* read the BRIF Configuration */
569 rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);
570 rd_value &= ~0x20;
571 pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
572 /* read the BRIF Frame Pulse Configuration */
573 rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg);
574 rd_value &= ~0x20;
575 pci_write_32((u_int32_t *) &comet->brif_fpcfg, (u_int8_t) rd_value);
576 } else {
577 /* read the BRIF Configuration */
578 rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);
579 rd_value |= 0x20;
580 pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
581 /* read the BRIF Frame Pulse Configuration */
582 rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg);
583 rd_value |= 0x20;
584 pci_write_32(u_int32_t *) & comet->brif_fpcfg, (u_int8_t) rd_value);
585 }
586}
587#endif
588
589/*** End-of-File ***/