tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * SH-X3 prototype CPU pinmux
3 *
4 * Copyright (C) 2010 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/init.h>
11#include <linux/kernel.h>
12#include <cpu/shx3.h>
13
14#include "sh_pfc.h"
15
16enum {
17 PINMUX_RESERVED = 0,
18
19 PINMUX_DATA_BEGIN,
20 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
21 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
22 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
23 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
24 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
25 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
26 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
27 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
28 PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
29 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
30 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
31 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
32 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
33 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
34
35 PH5_DATA, PH4_DATA,
36 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
37 PINMUX_DATA_END,
38
39 PINMUX_INPUT_BEGIN,
40 PA7_IN, PA6_IN, PA5_IN, PA4_IN,
41 PA3_IN, PA2_IN, PA1_IN, PA0_IN,
42 PB7_IN, PB6_IN, PB5_IN, PB4_IN,
43 PB3_IN, PB2_IN, PB1_IN, PB0_IN,
44 PC7_IN, PC6_IN, PC5_IN, PC4_IN,
45 PC3_IN, PC2_IN, PC1_IN, PC0_IN,
46 PD7_IN, PD6_IN, PD5_IN, PD4_IN,
47 PD3_IN, PD2_IN, PD1_IN, PD0_IN,
48 PE7_IN, PE6_IN, PE5_IN, PE4_IN,
49 PE3_IN, PE2_IN, PE1_IN, PE0_IN,
50 PF7_IN, PF6_IN, PF5_IN, PF4_IN,
51 PF3_IN, PF2_IN, PF1_IN, PF0_IN,
52 PG7_IN, PG6_IN, PG5_IN, PG4_IN,
53 PG3_IN, PG2_IN, PG1_IN, PG0_IN,
54
55 PH5_IN, PH4_IN,
56 PH3_IN, PH2_IN, PH1_IN, PH0_IN,
57 PINMUX_INPUT_END,
58
59 PINMUX_INPUT_PULLUP_BEGIN,
60 PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU,
61 PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU,
62 PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU,
63 PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU,
64 PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU,
65 PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU,
66 PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU,
67 PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU,
68 PE7_IN_PU, PE6_IN_PU, PE5_IN_PU, PE4_IN_PU,
69 PE3_IN_PU, PE2_IN_PU, PE1_IN_PU, PE0_IN_PU,
70 PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU,
71 PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU,
72 PG7_IN_PU, PG6_IN_PU, PG5_IN_PU, PG4_IN_PU,
73 PG3_IN_PU, PG2_IN_PU, PG1_IN_PU, PG0_IN_PU,
74
75 PH5_IN_PU, PH4_IN_PU,
76 PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU,
77 PINMUX_INPUT_PULLUP_END,
78
79 PINMUX_OUTPUT_BEGIN,
80 PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
81 PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
82 PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
83 PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
84 PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
85 PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
86 PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
87 PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
88 PE7_OUT, PE6_OUT, PE5_OUT, PE4_OUT,
89 PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT,
90 PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
91 PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
92 PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT,
93 PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT,
94
95 PH5_OUT, PH4_OUT,
96 PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
97 PINMUX_OUTPUT_END,
98
99 PINMUX_FUNCTION_BEGIN,
100 PA7_FN, PA6_FN, PA5_FN, PA4_FN,
101 PA3_FN, PA2_FN, PA1_FN, PA0_FN,
102 PB7_FN, PB6_FN, PB5_FN, PB4_FN,
103 PB3_FN, PB2_FN, PB1_FN, PB0_FN,
104 PC7_FN, PC6_FN, PC5_FN, PC4_FN,
105 PC3_FN, PC2_FN, PC1_FN, PC0_FN,
106 PD7_FN, PD6_FN, PD5_FN, PD4_FN,
107 PD3_FN, PD2_FN, PD1_FN, PD0_FN,
108 PE7_FN, PE6_FN, PE5_FN, PE4_FN,
109 PE3_FN, PE2_FN, PE1_FN, PE0_FN,
110 PF7_FN, PF6_FN, PF5_FN, PF4_FN,
111 PF3_FN, PF2_FN, PF1_FN, PF0_FN,
112 PG7_FN, PG6_FN, PG5_FN, PG4_FN,
113 PG3_FN, PG2_FN, PG1_FN, PG0_FN,
114
115 PH5_FN, PH4_FN,
116 PH3_FN, PH2_FN, PH1_FN, PH0_FN,
117 PINMUX_FUNCTION_END,
118
119 PINMUX_MARK_BEGIN,
120
121 D31_MARK, D30_MARK, D29_MARK, D28_MARK, D27_MARK, D26_MARK,
122 D25_MARK, D24_MARK, D23_MARK, D22_MARK, D21_MARK, D20_MARK,
123 D19_MARK, D18_MARK, D17_MARK, D16_MARK,
124
125 BACK_MARK, BREQ_MARK,
126 WE3_MARK, WE2_MARK,
127 CS6_MARK, CS5_MARK, CS4_MARK,
128 CLKOUTENB_MARK,
129
130 DACK3_MARK, DACK2_MARK, DACK1_MARK, DACK0_MARK,
131 DREQ3_MARK, DREQ2_MARK, DREQ1_MARK, DREQ0_MARK,
132
133 IRQ3_MARK, IRQ2_MARK, IRQ1_MARK, IRQ0_MARK,
134
135 DRAK3_MARK, DRAK2_MARK, DRAK1_MARK, DRAK0_MARK,
136
137 SCK3_MARK, SCK2_MARK, SCK1_MARK, SCK0_MARK,
138 IRL3_MARK, IRL2_MARK, IRL1_MARK, IRL0_MARK,
139 TXD3_MARK, TXD2_MARK, TXD1_MARK, TXD0_MARK,
140 RXD3_MARK, RXD2_MARK, RXD1_MARK, RXD0_MARK,
141
142 CE2B_MARK, CE2A_MARK, IOIS16_MARK,
143 STATUS1_MARK, STATUS0_MARK,
144
145 IRQOUT_MARK,
146
147 PINMUX_MARK_END,
148};
149
150static const pinmux_enum_t shx3_pinmux_data[] = {
151
152 /* PA GPIO */
153 PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
154 PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU),
155 PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU),
156 PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU),
157 PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU),
158 PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU),
159 PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU),
160 PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU),
161
162 /* PB GPIO */
163 PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU),
164 PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU),
165 PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU),
166 PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU),
167 PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU),
168 PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU),
169 PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU),
170 PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU),
171
172 /* PC GPIO */
173 PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU),
174 PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU),
175 PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU),
176 PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU),
177 PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU),
178 PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU),
179 PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU),
180 PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU),
181
182 /* PD GPIO */
183 PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU),
184 PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU),
185 PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU),
186 PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU),
187 PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU),
188 PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU),
189 PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU),
190 PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU),
191
192 /* PE GPIO */
193 PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU),
194 PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU),
195 PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT, PE5_IN_PU),
196 PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT, PE4_IN_PU),
197 PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT, PE3_IN_PU),
198 PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT, PE2_IN_PU),
199 PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT, PE1_IN_PU),
200 PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT, PE0_IN_PU),
201
202 /* PF GPIO */
203 PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU),
204 PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU),
205 PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU),
206 PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU),
207 PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU),
208 PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU),
209 PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU),
210 PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU),
211
212 /* PG GPIO */
213 PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU),
214 PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU),
215 PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU),
216 PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT, PG4_IN_PU),
217 PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT, PG3_IN_PU),
218 PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT, PG2_IN_PU),
219 PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT, PG1_IN_PU),
220 PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT, PG0_IN_PU),
221
222 /* PH GPIO */
223 PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU),
224 PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU),
225 PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU),
226 PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU),
227 PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU),
228 PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU),
229
230 /* PA FN */
231 PINMUX_DATA(D31_MARK, PA7_FN),
232 PINMUX_DATA(D30_MARK, PA6_FN),
233 PINMUX_DATA(D29_MARK, PA5_FN),
234 PINMUX_DATA(D28_MARK, PA4_FN),
235 PINMUX_DATA(D27_MARK, PA3_FN),
236 PINMUX_DATA(D26_MARK, PA2_FN),
237 PINMUX_DATA(D25_MARK, PA1_FN),
238 PINMUX_DATA(D24_MARK, PA0_FN),
239
240 /* PB FN */
241 PINMUX_DATA(D23_MARK, PB7_FN),
242 PINMUX_DATA(D22_MARK, PB6_FN),
243 PINMUX_DATA(D21_MARK, PB5_FN),
244 PINMUX_DATA(D20_MARK, PB4_FN),
245 PINMUX_DATA(D19_MARK, PB3_FN),
246 PINMUX_DATA(D18_MARK, PB2_FN),
247 PINMUX_DATA(D17_MARK, PB1_FN),
248 PINMUX_DATA(D16_MARK, PB0_FN),
249
250 /* PC FN */
251 PINMUX_DATA(BACK_MARK, PC7_FN),
252 PINMUX_DATA(BREQ_MARK, PC6_FN),
253 PINMUX_DATA(WE3_MARK, PC5_FN),
254 PINMUX_DATA(WE2_MARK, PC4_FN),
255 PINMUX_DATA(CS6_MARK, PC3_FN),
256 PINMUX_DATA(CS5_MARK, PC2_FN),
257 PINMUX_DATA(CS4_MARK, PC1_FN),
258 PINMUX_DATA(CLKOUTENB_MARK, PC0_FN),
259
260 /* PD FN */
261 PINMUX_DATA(DACK3_MARK, PD7_FN),
262 PINMUX_DATA(DACK2_MARK, PD6_FN),
263 PINMUX_DATA(DACK1_MARK, PD5_FN),
264 PINMUX_DATA(DACK0_MARK, PD4_FN),
265 PINMUX_DATA(DREQ3_MARK, PD3_FN),
266 PINMUX_DATA(DREQ2_MARK, PD2_FN),
267 PINMUX_DATA(DREQ1_MARK, PD1_FN),
268 PINMUX_DATA(DREQ0_MARK, PD0_FN),
269
270 /* PE FN */
271 PINMUX_DATA(IRQ3_MARK, PE7_FN),
272 PINMUX_DATA(IRQ2_MARK, PE6_FN),
273 PINMUX_DATA(IRQ1_MARK, PE5_FN),
274 PINMUX_DATA(IRQ0_MARK, PE4_FN),
275 PINMUX_DATA(DRAK3_MARK, PE3_FN),
276 PINMUX_DATA(DRAK2_MARK, PE2_FN),
277 PINMUX_DATA(DRAK1_MARK, PE1_FN),
278 PINMUX_DATA(DRAK0_MARK, PE0_FN),
279
280 /* PF FN */
281 PINMUX_DATA(SCK3_MARK, PF7_FN),
282 PINMUX_DATA(SCK2_MARK, PF6_FN),
283 PINMUX_DATA(SCK1_MARK, PF5_FN),
284 PINMUX_DATA(SCK0_MARK, PF4_FN),
285 PINMUX_DATA(IRL3_MARK, PF3_FN),
286 PINMUX_DATA(IRL2_MARK, PF2_FN),
287 PINMUX_DATA(IRL1_MARK, PF1_FN),
288 PINMUX_DATA(IRL0_MARK, PF0_FN),
289
290 /* PG FN */
291 PINMUX_DATA(TXD3_MARK, PG7_FN),
292 PINMUX_DATA(TXD2_MARK, PG6_FN),
293 PINMUX_DATA(TXD1_MARK, PG5_FN),
294 PINMUX_DATA(TXD0_MARK, PG4_FN),
295 PINMUX_DATA(RXD3_MARK, PG3_FN),
296 PINMUX_DATA(RXD2_MARK, PG2_FN),
297 PINMUX_DATA(RXD1_MARK, PG1_FN),
298 PINMUX_DATA(RXD0_MARK, PG0_FN),
299
300 /* PH FN */
301 PINMUX_DATA(CE2B_MARK, PH5_FN),
302 PINMUX_DATA(CE2A_MARK, PH4_FN),
303 PINMUX_DATA(IOIS16_MARK, PH3_FN),
304 PINMUX_DATA(STATUS1_MARK, PH2_FN),
305 PINMUX_DATA(STATUS0_MARK, PH1_FN),
306 PINMUX_DATA(IRQOUT_MARK, PH0_FN),
307};
308
309static struct sh_pfc_pin shx3_pinmux_pins[] = {
310 /* PA */
311 PINMUX_GPIO(GPIO_PA7, PA7_DATA),
312 PINMUX_GPIO(GPIO_PA6, PA6_DATA),
313 PINMUX_GPIO(GPIO_PA5, PA5_DATA),
314 PINMUX_GPIO(GPIO_PA4, PA4_DATA),
315 PINMUX_GPIO(GPIO_PA3, PA3_DATA),
316 PINMUX_GPIO(GPIO_PA2, PA2_DATA),
317 PINMUX_GPIO(GPIO_PA1, PA1_DATA),
318 PINMUX_GPIO(GPIO_PA0, PA0_DATA),
319
320 /* PB */
321 PINMUX_GPIO(GPIO_PB7, PB7_DATA),
322 PINMUX_GPIO(GPIO_PB6, PB6_DATA),
323 PINMUX_GPIO(GPIO_PB5, PB5_DATA),
324 PINMUX_GPIO(GPIO_PB4, PB4_DATA),
325 PINMUX_GPIO(GPIO_PB3, PB3_DATA),
326 PINMUX_GPIO(GPIO_PB2, PB2_DATA),
327 PINMUX_GPIO(GPIO_PB1, PB1_DATA),
328 PINMUX_GPIO(GPIO_PB0, PB0_DATA),
329
330 /* PC */
331 PINMUX_GPIO(GPIO_PC7, PC7_DATA),
332 PINMUX_GPIO(GPIO_PC6, PC6_DATA),
333 PINMUX_GPIO(GPIO_PC5, PC5_DATA),
334 PINMUX_GPIO(GPIO_PC4, PC4_DATA),
335 PINMUX_GPIO(GPIO_PC3, PC3_DATA),
336 PINMUX_GPIO(GPIO_PC2, PC2_DATA),
337 PINMUX_GPIO(GPIO_PC1, PC1_DATA),
338 PINMUX_GPIO(GPIO_PC0, PC0_DATA),
339
340 /* PD */
341 PINMUX_GPIO(GPIO_PD7, PD7_DATA),
342 PINMUX_GPIO(GPIO_PD6, PD6_DATA),
343 PINMUX_GPIO(GPIO_PD5, PD5_DATA),
344 PINMUX_GPIO(GPIO_PD4, PD4_DATA),
345 PINMUX_GPIO(GPIO_PD3, PD3_DATA),
346 PINMUX_GPIO(GPIO_PD2, PD2_DATA),
347 PINMUX_GPIO(GPIO_PD1, PD1_DATA),
348 PINMUX_GPIO(GPIO_PD0, PD0_DATA),
349
350 /* PE */
351 PINMUX_GPIO(GPIO_PE7, PE7_DATA),
352 PINMUX_GPIO(GPIO_PE6, PE6_DATA),
353 PINMUX_GPIO(GPIO_PE5, PE5_DATA),
354 PINMUX_GPIO(GPIO_PE4, PE4_DATA),
355 PINMUX_GPIO(GPIO_PE3, PE3_DATA),
356 PINMUX_GPIO(GPIO_PE2, PE2_DATA),
357 PINMUX_GPIO(GPIO_PE1, PE1_DATA),
358 PINMUX_GPIO(GPIO_PE0, PE0_DATA),
359
360 /* PF */
361 PINMUX_GPIO(GPIO_PF7, PF7_DATA),
362 PINMUX_GPIO(GPIO_PF6, PF6_DATA),
363 PINMUX_GPIO(GPIO_PF5, PF5_DATA),
364 PINMUX_GPIO(GPIO_PF4, PF4_DATA),
365 PINMUX_GPIO(GPIO_PF3, PF3_DATA),
366 PINMUX_GPIO(GPIO_PF2, PF2_DATA),
367 PINMUX_GPIO(GPIO_PF1, PF1_DATA),
368 PINMUX_GPIO(GPIO_PF0, PF0_DATA),
369
370 /* PG */
371 PINMUX_GPIO(GPIO_PG7, PG7_DATA),
372 PINMUX_GPIO(GPIO_PG6, PG6_DATA),
373 PINMUX_GPIO(GPIO_PG5, PG5_DATA),
374 PINMUX_GPIO(GPIO_PG4, PG4_DATA),
375 PINMUX_GPIO(GPIO_PG3, PG3_DATA),
376 PINMUX_GPIO(GPIO_PG2, PG2_DATA),
377 PINMUX_GPIO(GPIO_PG1, PG1_DATA),
378 PINMUX_GPIO(GPIO_PG0, PG0_DATA),
379
380 /* PH */
381 PINMUX_GPIO(GPIO_PH5, PH5_DATA),
382 PINMUX_GPIO(GPIO_PH4, PH4_DATA),
383 PINMUX_GPIO(GPIO_PH3, PH3_DATA),
384 PINMUX_GPIO(GPIO_PH2, PH2_DATA),
385 PINMUX_GPIO(GPIO_PH1, PH1_DATA),
386 PINMUX_GPIO(GPIO_PH0, PH0_DATA),
387};
388
389#define PINMUX_FN_BASE ARRAY_SIZE(shx3_pinmux_pins)
390
391static const struct pinmux_func shx3_pinmux_func_gpios[] = {
392 /* FN */
393 GPIO_FN(D31),
394 GPIO_FN(D30),
395 GPIO_FN(D29),
396 GPIO_FN(D28),
397 GPIO_FN(D27),
398 GPIO_FN(D26),
399 GPIO_FN(D25),
400 GPIO_FN(D24),
401 GPIO_FN(D23),
402 GPIO_FN(D22),
403 GPIO_FN(D21),
404 GPIO_FN(D20),
405 GPIO_FN(D19),
406 GPIO_FN(D18),
407 GPIO_FN(D17),
408 GPIO_FN(D16),
409 GPIO_FN(BACK),
410 GPIO_FN(BREQ),
411 GPIO_FN(WE3),
412 GPIO_FN(WE2),
413 GPIO_FN(CS6),
414 GPIO_FN(CS5),
415 GPIO_FN(CS4),
416 GPIO_FN(CLKOUTENB),
417 GPIO_FN(DACK3),
418 GPIO_FN(DACK2),
419 GPIO_FN(DACK1),
420 GPIO_FN(DACK0),
421 GPIO_FN(DREQ3),
422 GPIO_FN(DREQ2),
423 GPIO_FN(DREQ1),
424 GPIO_FN(DREQ0),
425 GPIO_FN(IRQ3),
426 GPIO_FN(IRQ2),
427 GPIO_FN(IRQ1),
428 GPIO_FN(IRQ0),
429 GPIO_FN(DRAK3),
430 GPIO_FN(DRAK2),
431 GPIO_FN(DRAK1),
432 GPIO_FN(DRAK0),
433 GPIO_FN(SCK3),
434 GPIO_FN(SCK2),
435 GPIO_FN(SCK1),
436 GPIO_FN(SCK0),
437 GPIO_FN(IRL3),
438 GPIO_FN(IRL2),
439 GPIO_FN(IRL1),
440 GPIO_FN(IRL0),
441 GPIO_FN(TXD3),
442 GPIO_FN(TXD2),
443 GPIO_FN(TXD1),
444 GPIO_FN(TXD0),
445 GPIO_FN(RXD3),
446 GPIO_FN(RXD2),
447 GPIO_FN(RXD1),
448 GPIO_FN(RXD0),
449 GPIO_FN(CE2B),
450 GPIO_FN(CE2A),
451 GPIO_FN(IOIS16),
452 GPIO_FN(STATUS1),
453 GPIO_FN(STATUS0),
454 GPIO_FN(IRQOUT),
455};
456
457static const struct pinmux_cfg_reg shx3_pinmux_config_regs[] = {
458 { PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) {
459 PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
460 PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
461 PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU,
462 PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU,
463 PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU,
464 PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU,
465 PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU,
466 PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU,
467 PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU,
468 PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU,
469 PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU,
470 PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU,
471 PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU,
472 PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU,
473 PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU,
474 PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU, },
475 },
476 { PINMUX_CFG_REG("PCDCR", 0xffc70004, 32, 2) {
477 PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU,
478 PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU,
479 PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU,
480 PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU,
481 PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU,
482 PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU,
483 PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU,
484 PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU,
485 PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU,
486 PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU,
487 PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU,
488 PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU,
489 PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU,
490 PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU,
491 PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU,
492 PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU, },
493 },
494 { PINMUX_CFG_REG("PEFCR", 0xffc70008, 32, 2) {
495 PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU,
496 PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU,
497 PE5_FN, PE5_OUT, PE5_IN, PE5_IN_PU,
498 PE4_FN, PE4_OUT, PE4_IN, PE4_IN_PU,
499 PE3_FN, PE3_OUT, PE3_IN, PE3_IN_PU,
500 PE2_FN, PE2_OUT, PE2_IN, PE2_IN_PU,
501 PE1_FN, PE1_OUT, PE1_IN, PE1_IN_PU,
502 PE0_FN, PE0_OUT, PE0_IN, PE0_IN_PU,
503 PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU,
504 PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU,
505 PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU,
506 PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU,
507 PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU,
508 PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU,
509 PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU,
510 PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU, },
511 },
512 { PINMUX_CFG_REG("PGHCR", 0xffc7000c, 32, 2) {
513 PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU,
514 PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU,
515 PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU,
516 PG4_FN, PG4_OUT, PG4_IN, PG4_IN_PU,
517 PG3_FN, PG3_OUT, PG3_IN, PG3_IN_PU,
518 PG2_FN, PG2_OUT, PG2_IN, PG2_IN_PU,
519 PG1_FN, PG1_OUT, PG1_IN, PG1_IN_PU,
520 PG0_FN, PG0_OUT, PG0_IN, PG0_IN_PU,
521 0, 0, 0, 0,
522 0, 0, 0, 0,
523 PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU,
524 PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU,
525 PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU,
526 PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU,
527 PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU,
528 PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU, },
529 },
530 { },
531};
532
533static const struct pinmux_data_reg shx3_pinmux_data_regs[] = {
534 { PINMUX_DATA_REG("PABDR", 0xffc70010, 32) {
535 0, 0, 0, 0, 0, 0, 0, 0,
536 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
537 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
538 0, 0, 0, 0, 0, 0, 0, 0,
539 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
540 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, },
541 },
542 { PINMUX_DATA_REG("PCDDR", 0xffc70014, 32) {
543 0, 0, 0, 0, 0, 0, 0, 0,
544 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
545 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
546 0, 0, 0, 0, 0, 0, 0, 0,
547 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
548 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, },
549 },
550 { PINMUX_DATA_REG("PEFDR", 0xffc70018, 32) {
551 0, 0, 0, 0, 0, 0, 0, 0,
552 PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
553 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
554 0, 0, 0, 0, 0, 0, 0, 0,
555 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
556 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, },
557 },
558 { PINMUX_DATA_REG("PGHDR", 0xffc7001c, 32) {
559 0, 0, 0, 0, 0, 0, 0, 0,
560 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
561 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
562 0, 0, 0, 0, 0, 0, 0, 0,
563 0, 0, PH5_DATA, PH4_DATA,
564 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, },
565 },
566 { },
567};
568
569const struct sh_pfc_soc_info shx3_pinmux_info = {
570 .name = "shx3_pfc",
571 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
572 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
573 PINMUX_INPUT_PULLUP_END },
574 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
575 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
576 .pins = shx3_pinmux_pins,
577 .nr_pins = ARRAY_SIZE(shx3_pinmux_pins),
578 .func_gpios = shx3_pinmux_func_gpios,
579 .nr_func_gpios = ARRAY_SIZE(shx3_pinmux_func_gpios),
580 .gpio_data = shx3_pinmux_data,
581 .gpio_data_size = ARRAY_SIZE(shx3_pinmux_data),
582 .cfg_regs = shx3_pinmux_config_regs,
583 .data_regs = shx3_pinmux_data_regs,
584};