tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX4_QP_H
34#define MLX4_QP_H
35
36#include <linux/types.h>
37
38#include <linux/mlx4/device.h>
39
40#define MLX4_INVALID_LKEY 0x100
41
42enum mlx4_qp_optpar {
43 MLX4_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
44 MLX4_QP_OPTPAR_RRE = 1 << 1,
45 MLX4_QP_OPTPAR_RAE = 1 << 2,
46 MLX4_QP_OPTPAR_RWE = 1 << 3,
47 MLX4_QP_OPTPAR_PKEY_INDEX = 1 << 4,
48 MLX4_QP_OPTPAR_Q_KEY = 1 << 5,
49 MLX4_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
50 MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
51 MLX4_QP_OPTPAR_SRA_MAX = 1 << 8,
52 MLX4_QP_OPTPAR_RRA_MAX = 1 << 9,
53 MLX4_QP_OPTPAR_PM_STATE = 1 << 10,
54 MLX4_QP_OPTPAR_RETRY_COUNT = 1 << 12,
55 MLX4_QP_OPTPAR_RNR_RETRY = 1 << 13,
56 MLX4_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
57 MLX4_QP_OPTPAR_SCHED_QUEUE = 1 << 16,
58 MLX4_QP_OPTPAR_COUNTER_INDEX = 1 << 20
59};
60
61enum mlx4_qp_state {
62 MLX4_QP_STATE_RST = 0,
63 MLX4_QP_STATE_INIT = 1,
64 MLX4_QP_STATE_RTR = 2,
65 MLX4_QP_STATE_RTS = 3,
66 MLX4_QP_STATE_SQER = 4,
67 MLX4_QP_STATE_SQD = 5,
68 MLX4_QP_STATE_ERR = 6,
69 MLX4_QP_STATE_SQ_DRAINING = 7,
70 MLX4_QP_NUM_STATE
71};
72
73enum {
74 MLX4_QP_ST_RC = 0x0,
75 MLX4_QP_ST_UC = 0x1,
76 MLX4_QP_ST_RD = 0x2,
77 MLX4_QP_ST_UD = 0x3,
78 MLX4_QP_ST_XRC = 0x6,
79 MLX4_QP_ST_MLX = 0x7
80};
81
82enum {
83 MLX4_QP_PM_MIGRATED = 0x3,
84 MLX4_QP_PM_ARMED = 0x0,
85 MLX4_QP_PM_REARM = 0x1
86};
87
88enum {
89 /* params1 */
90 MLX4_QP_BIT_SRE = 1 << 15,
91 MLX4_QP_BIT_SWE = 1 << 14,
92 MLX4_QP_BIT_SAE = 1 << 13,
93 /* params2 */
94 MLX4_QP_BIT_RRE = 1 << 15,
95 MLX4_QP_BIT_RWE = 1 << 14,
96 MLX4_QP_BIT_RAE = 1 << 13,
97 MLX4_QP_BIT_RIC = 1 << 4,
98};
99
100enum {
101 MLX4_RSS_HASH_XOR = 0,
102 MLX4_RSS_HASH_TOP = 1,
103
104 MLX4_RSS_UDP_IPV6 = 1 << 0,
105 MLX4_RSS_UDP_IPV4 = 1 << 1,
106 MLX4_RSS_TCP_IPV6 = 1 << 2,
107 MLX4_RSS_IPV6 = 1 << 3,
108 MLX4_RSS_TCP_IPV4 = 1 << 4,
109 MLX4_RSS_IPV4 = 1 << 5,
110
111 /* offset of mlx4_rss_context within mlx4_qp_context.pri_path */
112 MLX4_RSS_OFFSET_IN_QPC_PRI_PATH = 0x24,
113 /* offset of being RSS indirection QP within mlx4_qp_context.flags */
114 MLX4_RSS_QPC_FLAG_OFFSET = 13,
115};
116
117struct mlx4_rss_context {
118 __be32 base_qpn;
119 __be32 default_qpn;
120 u16 reserved;
121 u8 hash_fn;
122 u8 flags;
123 __be32 rss_key[10];
124 __be32 base_qpn_udp;
125};
126
127struct mlx4_qp_path {
128 u8 fl;
129 u8 vlan_control;
130 u8 disable_pkey_check;
131 u8 pkey_index;
132 u8 counter_index;
133 u8 grh_mylmc;
134 __be16 rlid;
135 u8 ackto;
136 u8 mgid_index;
137 u8 static_rate;
138 u8 hop_limit;
139 __be32 tclass_flowlabel;
140 u8 rgid[16];
141 u8 sched_queue;
142 u8 vlan_index;
143 u8 feup;
144 u8 fvl_rx;
145 u8 reserved4[2];
146 u8 dmac[6];
147};
148
149enum { /* fl */
150 MLX4_FL_CV = 1 << 6,
151 MLX4_FL_ETH_HIDE_CQE_VLAN = 1 << 2
152};
153enum { /* vlan_control */
154 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED = 1 << 6,
155 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED = 1 << 5, /* 802.1p priority tag */
156 MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED = 1 << 4,
157 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED = 1 << 2,
158 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED = 1 << 1, /* 802.1p priority tag */
159 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED = 1 << 0
160};
161
162enum { /* feup */
163 MLX4_FEUP_FORCE_ETH_UP = 1 << 6, /* force Eth UP */
164 MLX4_FSM_FORCE_ETH_SRC_MAC = 1 << 5, /* force Source MAC */
165 MLX4_FVL_FORCE_ETH_VLAN = 1 << 3 /* force Eth vlan */
166};
167
168enum { /* fvl_rx */
169 MLX4_FVL_RX_FORCE_ETH_VLAN = 1 << 0 /* enforce Eth rx vlan */
170};
171
172struct mlx4_qp_context {
173 __be32 flags;
174 __be32 pd;
175 u8 mtu_msgmax;
176 u8 rq_size_stride;
177 u8 sq_size_stride;
178 u8 rlkey;
179 __be32 usr_page;
180 __be32 local_qpn;
181 __be32 remote_qpn;
182 struct mlx4_qp_path pri_path;
183 struct mlx4_qp_path alt_path;
184 __be32 params1;
185 u32 reserved1;
186 __be32 next_send_psn;
187 __be32 cqn_send;
188 u32 reserved2[2];
189 __be32 last_acked_psn;
190 __be32 ssn;
191 __be32 params2;
192 __be32 rnr_nextrecvpsn;
193 __be32 xrcd;
194 __be32 cqn_recv;
195 __be64 db_rec_addr;
196 __be32 qkey;
197 __be32 srqn;
198 __be32 msn;
199 __be16 rq_wqe_counter;
200 __be16 sq_wqe_counter;
201 u32 reserved3[2];
202 __be32 param3;
203 __be32 nummmcpeers_basemkey;
204 u8 log_page_size;
205 u8 reserved4[2];
206 u8 mtt_base_addr_h;
207 __be32 mtt_base_addr_l;
208 u32 reserved5[10];
209};
210
211struct mlx4_update_qp_context {
212 __be64 qp_mask;
213 __be64 primary_addr_path_mask;
214 __be64 secondary_addr_path_mask;
215 u64 reserved1;
216 struct mlx4_qp_context qp_context;
217 u64 reserved2[58];
218};
219
220enum {
221 MLX4_UPD_QP_MASK_PM_STATE = 32,
222 MLX4_UPD_QP_MASK_VSD = 33,
223};
224
225enum {
226 MLX4_UPD_QP_PATH_MASK_PKEY_INDEX = 0 + 32,
227 MLX4_UPD_QP_PATH_MASK_FSM = 1 + 32,
228 MLX4_UPD_QP_PATH_MASK_MAC_INDEX = 2 + 32,
229 MLX4_UPD_QP_PATH_MASK_FVL = 3 + 32,
230 MLX4_UPD_QP_PATH_MASK_CV = 4 + 32,
231 MLX4_UPD_QP_PATH_MASK_VLAN_INDEX = 5 + 32,
232 MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN = 6 + 32,
233 MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED = 7 + 32,
234 MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P = 8 + 32,
235 MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED = 9 + 32,
236 MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED = 10 + 32,
237 MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P = 11 + 32,
238 MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED = 12 + 32,
239 MLX4_UPD_QP_PATH_MASK_FEUP = 13 + 32,
240 MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE = 14 + 32,
241 MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX = 15 + 32,
242 MLX4_UPD_QP_PATH_MASK_FVL_RX = 16 + 32,
243};
244
245enum { /* param3 */
246 MLX4_STRIP_VLAN = 1 << 30
247};
248
249/* Which firmware version adds support for NEC (NoErrorCompletion) bit */
250#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
251
252enum {
253 MLX4_WQE_CTRL_NEC = 1 << 29,
254 MLX4_WQE_CTRL_FENCE = 1 << 6,
255 MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2,
256 MLX4_WQE_CTRL_SOLICITED = 1 << 1,
257 MLX4_WQE_CTRL_IP_CSUM = 1 << 4,
258 MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5,
259 MLX4_WQE_CTRL_INS_VLAN = 1 << 6,
260 MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7,
261 MLX4_WQE_CTRL_FORCE_LOOPBACK = 1 << 0,
262};
263
264struct mlx4_wqe_ctrl_seg {
265 __be32 owner_opcode;
266 __be16 vlan_tag;
267 u8 ins_vlan;
268 u8 fence_size;
269 /*
270 * High 24 bits are SRC remote buffer; low 8 bits are flags:
271 * [7] SO (strong ordering)
272 * [5] TCP/UDP checksum
273 * [4] IP checksum
274 * [3:2] C (generate completion queue entry)
275 * [1] SE (solicited event)
276 * [0] FL (force loopback)
277 */
278 union {
279 __be32 srcrb_flags;
280 __be16 srcrb_flags16[2];
281 };
282 /*
283 * imm is immediate data for send/RDMA write w/ immediate;
284 * also invalidation key for send with invalidate; input
285 * modifier for WQEs on CCQs.
286 */
287 __be32 imm;
288};
289
290enum {
291 MLX4_WQE_MLX_VL15 = 1 << 17,
292 MLX4_WQE_MLX_SLR = 1 << 16
293};
294
295struct mlx4_wqe_mlx_seg {
296 u8 owner;
297 u8 reserved1[2];
298 u8 opcode;
299 __be16 sched_prio;
300 u8 reserved2;
301 u8 size;
302 /*
303 * [17] VL15
304 * [16] SLR
305 * [15:12] static rate
306 * [11:8] SL
307 * [4] ICRC
308 * [3:2] C
309 * [0] FL (force loopback)
310 */
311 __be32 flags;
312 __be16 rlid;
313 u16 reserved3;
314};
315
316struct mlx4_wqe_datagram_seg {
317 __be32 av[8];
318 __be32 dqpn;
319 __be32 qkey;
320 __be16 vlan;
321 u8 mac[6];
322};
323
324struct mlx4_wqe_lso_seg {
325 __be32 mss_hdr_size;
326 __be32 header[0];
327};
328
329enum mlx4_wqe_bind_seg_flags2 {
330 MLX4_WQE_BIND_ZERO_BASED = (1 << 30),
331 MLX4_WQE_BIND_TYPE_2 = (1 << 31),
332};
333
334struct mlx4_wqe_bind_seg {
335 __be32 flags1;
336 __be32 flags2;
337 __be32 new_rkey;
338 __be32 lkey;
339 __be64 addr;
340 __be64 length;
341};
342
343enum {
344 MLX4_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
345 MLX4_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
346 MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ = 1 << 29,
347 MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE = 1 << 30,
348 MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC = 1 << 31
349};
350
351struct mlx4_wqe_fmr_seg {
352 __be32 flags;
353 __be32 mem_key;
354 __be64 buf_list;
355 __be64 start_addr;
356 __be64 reg_len;
357 __be32 offset;
358 __be32 page_size;
359 u32 reserved[2];
360};
361
362struct mlx4_wqe_fmr_ext_seg {
363 u8 flags;
364 u8 reserved;
365 __be16 app_mask;
366 __be16 wire_app_tag;
367 __be16 mem_app_tag;
368 __be32 wire_ref_tag_base;
369 __be32 mem_ref_tag_base;
370};
371
372struct mlx4_wqe_local_inval_seg {
373 u64 reserved1;
374 __be32 mem_key;
375 u32 reserved2;
376 u64 reserved3[2];
377};
378
379struct mlx4_wqe_raddr_seg {
380 __be64 raddr;
381 __be32 rkey;
382 u32 reserved;
383};
384
385struct mlx4_wqe_atomic_seg {
386 __be64 swap_add;
387 __be64 compare;
388};
389
390struct mlx4_wqe_masked_atomic_seg {
391 __be64 swap_add;
392 __be64 compare;
393 __be64 swap_add_mask;
394 __be64 compare_mask;
395};
396
397struct mlx4_wqe_data_seg {
398 __be32 byte_count;
399 __be32 lkey;
400 __be64 addr;
401};
402
403enum {
404 MLX4_INLINE_ALIGN = 64,
405 MLX4_INLINE_SEG = 1 << 31,
406};
407
408struct mlx4_wqe_inline_seg {
409 __be32 byte_count;
410};
411
412int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
413 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
414 struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
415 int sqd_event, struct mlx4_qp *qp);
416
417int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
418 struct mlx4_qp_context *context);
419
420int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
421 struct mlx4_qp_context *context,
422 struct mlx4_qp *qp, enum mlx4_qp_state *qp_state);
423
424static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
425{
426 return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1));
427}
428
429void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp);
430
431#endif /* MLX4_QP_H */