tjh.dev / kernel
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kernel / include / linux / mfd / palmas.h
at v3.11-rc2 2869 lines 113 kB view raw
1/* 2 * TI Palmas 3 * 4 * Copyright 2011-2013 Texas Instruments Inc. 5 * 6 * Author: Graeme Gregory <gg@slimlogic.co.uk> 7 * Author: Ian Lartey <ian@slimlogic.co.uk> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 */ 15 16#ifndef __LINUX_MFD_PALMAS_H 17#define __LINUX_MFD_PALMAS_H 18 19#include <linux/usb/otg.h> 20#include <linux/leds.h> 21#include <linux/regmap.h> 22#include <linux/regulator/driver.h> 23#include <linux/extcon.h> 24#include <linux/usb/phy_companion.h> 25 26#define PALMAS_NUM_CLIENTS 3 27 28/* The ID_REVISION NUMBERS */ 29#define PALMAS_CHIP_OLD_ID 0x0000 30#define PALMAS_CHIP_ID 0xC035 31#define PALMAS_CHIP_CHARGER_ID 0xC036 32 33#define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \ 34 ((a) == PALMAS_CHIP_ID)) 35#define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID) 36 37/** 38 * Palmas PMIC feature types 39 * 40 * PALMAS_PMIC_FEATURE_SMPS10_BOOST - used when the PMIC provides SMPS10_BOOST 41 * regulator. 42 * 43 * PALMAS_PMIC_HAS(b, f) - macro to check if a bandgap device is capable of a 44 * specific feature (above) or not. Return non-zero, if yes. 45 */ 46#define PALMAS_PMIC_FEATURE_SMPS10_BOOST BIT(0) 47#define PALMAS_PMIC_HAS(b, f) \ 48 ((b)->features & PALMAS_PMIC_FEATURE_ ## f) 49 50struct palmas_pmic; 51struct palmas_gpadc; 52struct palmas_resource; 53struct palmas_usb; 54 55enum palmas_usb_state { 56 PALMAS_USB_STATE_DISCONNECT, 57 PALMAS_USB_STATE_VBUS, 58 PALMAS_USB_STATE_ID, 59}; 60 61struct palmas { 62 struct device *dev; 63 64 struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS]; 65 struct regmap *regmap[PALMAS_NUM_CLIENTS]; 66 67 /* Stored chip id */ 68 int id; 69 70 unsigned int features; 71 /* IRQ Data */ 72 int irq; 73 u32 irq_mask; 74 struct mutex irq_lock; 75 struct regmap_irq_chip_data *irq_data; 76 77 /* Child Devices */ 78 struct palmas_pmic *pmic; 79 struct palmas_gpadc *gpadc; 80 struct palmas_resource *resource; 81 struct palmas_usb *usb; 82 83 /* GPIO MUXing */ 84 u8 gpio_muxed; 85 u8 led_muxed; 86 u8 pwm_muxed; 87}; 88 89struct palmas_gpadc_platform_data { 90 /* Channel 3 current source is only enabled during conversion */ 91 int ch3_current; 92 93 /* Channel 0 current source can be used for battery detection. 94 * If used for battery detection this will cause a permanent current 95 * consumption depending on current level set here. 96 */ 97 int ch0_current; 98 99 /* default BAT_REMOVAL_DAT setting on device probe */ 100 int bat_removal; 101 102 /* Sets the START_POLARITY bit in the RT_CTRL register */ 103 int start_polarity; 104}; 105 106struct palmas_reg_init { 107 /* warm_rest controls the voltage levels after a warm reset 108 * 109 * 0: reload default values from OTP on warm reset 110 * 1: maintain voltage from VSEL on warm reset 111 */ 112 int warm_reset; 113 114 /* roof_floor controls whether the regulator uses the i2c style 115 * of DVS or uses the method where a GPIO or other control method is 116 * attached to the NSLEEP/ENABLE1/ENABLE2 pins 117 * 118 * For SMPS 119 * 120 * 0: i2c selection of voltage 121 * 1: pin selection of voltage. 122 * 123 * For LDO unused 124 */ 125 int roof_floor; 126 127 /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in 128 * the data sheet. 129 * 130 * For SMPS 131 * 132 * 0: Off 133 * 1: AUTO 134 * 2: ECO 135 * 3: Forced PWM 136 * 137 * For LDO 138 * 139 * 0: Off 140 * 1: On 141 */ 142 int mode_sleep; 143 144 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE 145 * register. Set this is the default voltage set in OTP needs 146 * to be overridden. 147 */ 148 u8 vsel; 149 150}; 151 152enum palmas_regulators { 153 /* SMPS regulators */ 154 PALMAS_REG_SMPS12, 155 PALMAS_REG_SMPS123, 156 PALMAS_REG_SMPS3, 157 PALMAS_REG_SMPS45, 158 PALMAS_REG_SMPS457, 159 PALMAS_REG_SMPS6, 160 PALMAS_REG_SMPS7, 161 PALMAS_REG_SMPS8, 162 PALMAS_REG_SMPS9, 163 PALMAS_REG_SMPS10, 164 /* LDO regulators */ 165 PALMAS_REG_LDO1, 166 PALMAS_REG_LDO2, 167 PALMAS_REG_LDO3, 168 PALMAS_REG_LDO4, 169 PALMAS_REG_LDO5, 170 PALMAS_REG_LDO6, 171 PALMAS_REG_LDO7, 172 PALMAS_REG_LDO8, 173 PALMAS_REG_LDO9, 174 PALMAS_REG_LDOLN, 175 PALMAS_REG_LDOUSB, 176 /* External regulators */ 177 PALMAS_REG_REGEN1, 178 PALMAS_REG_REGEN2, 179 PALMAS_REG_REGEN3, 180 PALMAS_REG_SYSEN1, 181 PALMAS_REG_SYSEN2, 182 /* Total number of regulators */ 183 PALMAS_NUM_REGS, 184}; 185 186struct palmas_pmic_platform_data { 187 /* An array of pointers to regulator init data indexed by regulator 188 * ID 189 */ 190 struct regulator_init_data *reg_data[PALMAS_NUM_REGS]; 191 192 /* An array of pointers to structures containing sleep mode and DVS 193 * configuration for regulators indexed by ID 194 */ 195 struct palmas_reg_init *reg_init[PALMAS_NUM_REGS]; 196 197 /* use LDO6 for vibrator control */ 198 int ldo6_vibrator; 199 200 /* Enable tracking mode of LDO8 */ 201 bool enable_ldo8_tracking; 202}; 203 204struct palmas_usb_platform_data { 205 /* Do we enable the wakeup comparator on probe */ 206 int wakeup; 207}; 208 209struct palmas_resource_platform_data { 210 int regen1_mode_sleep; 211 int regen2_mode_sleep; 212 int sysen1_mode_sleep; 213 int sysen2_mode_sleep; 214 215 /* bitfield to be loaded to NSLEEP_RES_ASSIGN */ 216 u8 nsleep_res; 217 /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */ 218 u8 nsleep_smps; 219 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */ 220 u8 nsleep_ldo1; 221 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */ 222 u8 nsleep_ldo2; 223 224 /* bitfield to be loaded to ENABLE1_RES_ASSIGN */ 225 u8 enable1_res; 226 /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */ 227 u8 enable1_smps; 228 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */ 229 u8 enable1_ldo1; 230 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */ 231 u8 enable1_ldo2; 232 233 /* bitfield to be loaded to ENABLE2_RES_ASSIGN */ 234 u8 enable2_res; 235 /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */ 236 u8 enable2_smps; 237 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */ 238 u8 enable2_ldo1; 239 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */ 240 u8 enable2_ldo2; 241}; 242 243struct palmas_clk_platform_data { 244 int clk32kg_mode_sleep; 245 int clk32kgaudio_mode_sleep; 246}; 247 248struct palmas_platform_data { 249 int irq_flags; 250 int gpio_base; 251 252 /* bit value to be loaded to the POWER_CTRL register */ 253 u8 power_ctrl; 254 255 /* 256 * boolean to select if we want to configure muxing here 257 * then the two value to load into the registers if true 258 */ 259 int mux_from_pdata; 260 u8 pad1, pad2; 261 262 struct palmas_pmic_platform_data *pmic_pdata; 263 struct palmas_gpadc_platform_data *gpadc_pdata; 264 struct palmas_usb_platform_data *usb_pdata; 265 struct palmas_resource_platform_data *resource_pdata; 266 struct palmas_clk_platform_data *clk_pdata; 267}; 268 269struct palmas_gpadc_calibration { 270 s32 gain; 271 s32 gain_error; 272 s32 offset_error; 273}; 274 275struct palmas_gpadc { 276 struct device *dev; 277 struct palmas *palmas; 278 279 int ch3_current; 280 int ch0_current; 281 282 int gpadc_force; 283 284 int bat_removal; 285 286 struct mutex reading_lock; 287 struct completion irq_complete; 288 289 int eoc_sw_irq; 290 291 struct palmas_gpadc_calibration *palmas_cal_tbl; 292 293 int conv0_channel; 294 int conv1_channel; 295 int rt_channel; 296}; 297 298struct palmas_gpadc_result { 299 s32 raw_code; 300 s32 corrected_code; 301 s32 result; 302}; 303 304#define PALMAS_MAX_CHANNELS 16 305 306/* Define the palmas IRQ numbers */ 307enum palmas_irqs { 308 /* INT1 registers */ 309 PALMAS_CHARG_DET_N_VBUS_OVV_IRQ, 310 PALMAS_PWRON_IRQ, 311 PALMAS_LONG_PRESS_KEY_IRQ, 312 PALMAS_RPWRON_IRQ, 313 PALMAS_PWRDOWN_IRQ, 314 PALMAS_HOTDIE_IRQ, 315 PALMAS_VSYS_MON_IRQ, 316 PALMAS_VBAT_MON_IRQ, 317 /* INT2 registers */ 318 PALMAS_RTC_ALARM_IRQ, 319 PALMAS_RTC_TIMER_IRQ, 320 PALMAS_WDT_IRQ, 321 PALMAS_BATREMOVAL_IRQ, 322 PALMAS_RESET_IN_IRQ, 323 PALMAS_FBI_BB_IRQ, 324 PALMAS_SHORT_IRQ, 325 PALMAS_VAC_ACOK_IRQ, 326 /* INT3 registers */ 327 PALMAS_GPADC_AUTO_0_IRQ, 328 PALMAS_GPADC_AUTO_1_IRQ, 329 PALMAS_GPADC_EOC_SW_IRQ, 330 PALMAS_GPADC_EOC_RT_IRQ, 331 PALMAS_ID_OTG_IRQ, 332 PALMAS_ID_IRQ, 333 PALMAS_VBUS_OTG_IRQ, 334 PALMAS_VBUS_IRQ, 335 /* INT4 registers */ 336 PALMAS_GPIO_0_IRQ, 337 PALMAS_GPIO_1_IRQ, 338 PALMAS_GPIO_2_IRQ, 339 PALMAS_GPIO_3_IRQ, 340 PALMAS_GPIO_4_IRQ, 341 PALMAS_GPIO_5_IRQ, 342 PALMAS_GPIO_6_IRQ, 343 PALMAS_GPIO_7_IRQ, 344 /* Total Number IRQs */ 345 PALMAS_NUM_IRQ, 346}; 347 348struct palmas_pmic { 349 struct palmas *palmas; 350 struct device *dev; 351 struct regulator_desc desc[PALMAS_NUM_REGS]; 352 struct regulator_dev *rdev[PALMAS_NUM_REGS]; 353 struct mutex mutex; 354 355 int smps123; 356 int smps457; 357 358 int range[PALMAS_REG_SMPS10]; 359 unsigned int ramp_delay[PALMAS_REG_SMPS10]; 360 unsigned int current_reg_mode[PALMAS_REG_SMPS10]; 361}; 362 363struct palmas_resource { 364 struct palmas *palmas; 365 struct device *dev; 366}; 367 368struct palmas_usb { 369 struct palmas *palmas; 370 struct device *dev; 371 372 struct extcon_dev edev; 373 374 /* used to set vbus, in atomic path */ 375 struct work_struct set_vbus_work; 376 377 int id_otg_irq; 378 int id_irq; 379 int vbus_otg_irq; 380 int vbus_irq; 381 382 int vbus_enable; 383 384 enum palmas_usb_state linkstat; 385}; 386 387#define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator) 388 389enum usb_irq_events { 390 /* Wakeup events from INT3 */ 391 PALMAS_USB_ID_WAKEPUP, 392 PALMAS_USB_VBUS_WAKEUP, 393 394 /* ID_OTG_EVENTS */ 395 PALMAS_USB_ID_GND, 396 N_PALMAS_USB_ID_GND, 397 PALMAS_USB_ID_C, 398 N_PALMAS_USB_ID_C, 399 PALMAS_USB_ID_B, 400 N_PALMAS_USB_ID_B, 401 PALMAS_USB_ID_A, 402 N_PALMAS_USB_ID_A, 403 PALMAS_USB_ID_FLOAT, 404 N_PALMAS_USB_ID_FLOAT, 405 406 /* VBUS_OTG_EVENTS */ 407 PALMAS_USB_VB_SESS_END, 408 N_PALMAS_USB_VB_SESS_END, 409 PALMAS_USB_VB_SESS_VLD, 410 N_PALMAS_USB_VB_SESS_VLD, 411 PALMAS_USB_VA_SESS_VLD, 412 N_PALMAS_USB_VA_SESS_VLD, 413 PALMAS_USB_VA_VBUS_VLD, 414 N_PALMAS_USB_VA_VBUS_VLD, 415 PALMAS_USB_VADP_SNS, 416 N_PALMAS_USB_VADP_SNS, 417 PALMAS_USB_VADP_PRB, 418 N_PALMAS_USB_VADP_PRB, 419 PALMAS_USB_VOTG_SESS_VLD, 420 N_PALMAS_USB_VOTG_SESS_VLD, 421}; 422 423/* defines so we can store the mux settings */ 424#define PALMAS_GPIO_0_MUXED (1 << 0) 425#define PALMAS_GPIO_1_MUXED (1 << 1) 426#define PALMAS_GPIO_2_MUXED (1 << 2) 427#define PALMAS_GPIO_3_MUXED (1 << 3) 428#define PALMAS_GPIO_4_MUXED (1 << 4) 429#define PALMAS_GPIO_5_MUXED (1 << 5) 430#define PALMAS_GPIO_6_MUXED (1 << 6) 431#define PALMAS_GPIO_7_MUXED (1 << 7) 432 433#define PALMAS_LED1_MUXED (1 << 0) 434#define PALMAS_LED2_MUXED (1 << 1) 435 436#define PALMAS_PWM1_MUXED (1 << 0) 437#define PALMAS_PWM2_MUXED (1 << 1) 438 439/* helper macro to get correct slave number */ 440#define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1) 441#define PALMAS_BASE_TO_REG(x, y) ((x & 0xff) + y) 442 443/* Base addresses of IP blocks in Palmas */ 444#define PALMAS_SMPS_DVS_BASE 0x20 445#define PALMAS_RTC_BASE 0x100 446#define PALMAS_VALIDITY_BASE 0x118 447#define PALMAS_SMPS_BASE 0x120 448#define PALMAS_LDO_BASE 0x150 449#define PALMAS_DVFS_BASE 0x180 450#define PALMAS_PMU_CONTROL_BASE 0x1A0 451#define PALMAS_RESOURCE_BASE 0x1D4 452#define PALMAS_PU_PD_OD_BASE 0x1F4 453#define PALMAS_LED_BASE 0x200 454#define PALMAS_INTERRUPT_BASE 0x210 455#define PALMAS_USB_OTG_BASE 0x250 456#define PALMAS_VIBRATOR_BASE 0x270 457#define PALMAS_GPIO_BASE 0x280 458#define PALMAS_USB_BASE 0x290 459#define PALMAS_GPADC_BASE 0x2C0 460#define PALMAS_TRIM_GPADC_BASE 0x3CD 461 462/* Registers for function RTC */ 463#define PALMAS_SECONDS_REG 0x0 464#define PALMAS_MINUTES_REG 0x1 465#define PALMAS_HOURS_REG 0x2 466#define PALMAS_DAYS_REG 0x3 467#define PALMAS_MONTHS_REG 0x4 468#define PALMAS_YEARS_REG 0x5 469#define PALMAS_WEEKS_REG 0x6 470#define PALMAS_ALARM_SECONDS_REG 0x8 471#define PALMAS_ALARM_MINUTES_REG 0x9 472#define PALMAS_ALARM_HOURS_REG 0xA 473#define PALMAS_ALARM_DAYS_REG 0xB 474#define PALMAS_ALARM_MONTHS_REG 0xC 475#define PALMAS_ALARM_YEARS_REG 0xD 476#define PALMAS_RTC_CTRL_REG 0x10 477#define PALMAS_RTC_STATUS_REG 0x11 478#define PALMAS_RTC_INTERRUPTS_REG 0x12 479#define PALMAS_RTC_COMP_LSB_REG 0x13 480#define PALMAS_RTC_COMP_MSB_REG 0x14 481#define PALMAS_RTC_RES_PROG_REG 0x15 482#define PALMAS_RTC_RESET_STATUS_REG 0x16 483 484/* Bit definitions for SECONDS_REG */ 485#define PALMAS_SECONDS_REG_SEC1_MASK 0x70 486#define PALMAS_SECONDS_REG_SEC1_SHIFT 4 487#define PALMAS_SECONDS_REG_SEC0_MASK 0x0f 488#define PALMAS_SECONDS_REG_SEC0_SHIFT 0 489 490/* Bit definitions for MINUTES_REG */ 491#define PALMAS_MINUTES_REG_MIN1_MASK 0x70 492#define PALMAS_MINUTES_REG_MIN1_SHIFT 4 493#define PALMAS_MINUTES_REG_MIN0_MASK 0x0f 494#define PALMAS_MINUTES_REG_MIN0_SHIFT 0 495 496/* Bit definitions for HOURS_REG */ 497#define PALMAS_HOURS_REG_PM_NAM 0x80 498#define PALMAS_HOURS_REG_PM_NAM_SHIFT 7 499#define PALMAS_HOURS_REG_HOUR1_MASK 0x30 500#define PALMAS_HOURS_REG_HOUR1_SHIFT 4 501#define PALMAS_HOURS_REG_HOUR0_MASK 0x0f 502#define PALMAS_HOURS_REG_HOUR0_SHIFT 0 503 504/* Bit definitions for DAYS_REG */ 505#define PALMAS_DAYS_REG_DAY1_MASK 0x30 506#define PALMAS_DAYS_REG_DAY1_SHIFT 4 507#define PALMAS_DAYS_REG_DAY0_MASK 0x0f 508#define PALMAS_DAYS_REG_DAY0_SHIFT 0 509 510/* Bit definitions for MONTHS_REG */ 511#define PALMAS_MONTHS_REG_MONTH1 0x10 512#define PALMAS_MONTHS_REG_MONTH1_SHIFT 4 513#define PALMAS_MONTHS_REG_MONTH0_MASK 0x0f 514#define PALMAS_MONTHS_REG_MONTH0_SHIFT 0 515 516/* Bit definitions for YEARS_REG */ 517#define PALMAS_YEARS_REG_YEAR1_MASK 0xf0 518#define PALMAS_YEARS_REG_YEAR1_SHIFT 4 519#define PALMAS_YEARS_REG_YEAR0_MASK 0x0f 520#define PALMAS_YEARS_REG_YEAR0_SHIFT 0 521 522/* Bit definitions for WEEKS_REG */ 523#define PALMAS_WEEKS_REG_WEEK_MASK 0x07 524#define PALMAS_WEEKS_REG_WEEK_SHIFT 0 525 526/* Bit definitions for ALARM_SECONDS_REG */ 527#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70 528#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 4 529#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0f 530#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0 531 532/* Bit definitions for ALARM_MINUTES_REG */ 533#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70 534#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 4 535#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0f 536#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0 537 538/* Bit definitions for ALARM_HOURS_REG */ 539#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80 540#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 7 541#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30 542#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 4 543#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0f 544#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0 545 546/* Bit definitions for ALARM_DAYS_REG */ 547#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30 548#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 4 549#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0f 550#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0 551 552/* Bit definitions for ALARM_MONTHS_REG */ 553#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10 554#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 4 555#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0f 556#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0 557 558/* Bit definitions for ALARM_YEARS_REG */ 559#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0 560#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 4 561#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0f 562#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0 563 564/* Bit definitions for RTC_CTRL_REG */ 565#define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80 566#define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 7 567#define PALMAS_RTC_CTRL_REG_GET_TIME 0x40 568#define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 6 569#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20 570#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 5 571#define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10 572#define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 4 573#define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08 574#define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 3 575#define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04 576#define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 2 577#define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02 578#define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 1 579#define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01 580#define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0 581 582/* Bit definitions for RTC_STATUS_REG */ 583#define PALMAS_RTC_STATUS_REG_POWER_UP 0x80 584#define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 7 585#define PALMAS_RTC_STATUS_REG_ALARM 0x40 586#define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 6 587#define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20 588#define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 5 589#define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10 590#define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 4 591#define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08 592#define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 3 593#define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04 594#define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 2 595#define PALMAS_RTC_STATUS_REG_RUN 0x02 596#define PALMAS_RTC_STATUS_REG_RUN_SHIFT 1 597 598/* Bit definitions for RTC_INTERRUPTS_REG */ 599#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10 600#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 4 601#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08 602#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 3 603#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04 604#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 2 605#define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03 606#define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0 607 608/* Bit definitions for RTC_COMP_LSB_REG */ 609#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xff 610#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0 611 612/* Bit definitions for RTC_COMP_MSB_REG */ 613#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xff 614#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0 615 616/* Bit definitions for RTC_RES_PROG_REG */ 617#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3f 618#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0 619 620/* Bit definitions for RTC_RESET_STATUS_REG */ 621#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01 622#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0 623 624/* Registers for function BACKUP */ 625#define PALMAS_BACKUP0 0x0 626#define PALMAS_BACKUP1 0x1 627#define PALMAS_BACKUP2 0x2 628#define PALMAS_BACKUP3 0x3 629#define PALMAS_BACKUP4 0x4 630#define PALMAS_BACKUP5 0x5 631#define PALMAS_BACKUP6 0x6 632#define PALMAS_BACKUP7 0x7 633 634/* Bit definitions for BACKUP0 */ 635#define PALMAS_BACKUP0_BACKUP_MASK 0xff 636#define PALMAS_BACKUP0_BACKUP_SHIFT 0 637 638/* Bit definitions for BACKUP1 */ 639#define PALMAS_BACKUP1_BACKUP_MASK 0xff 640#define PALMAS_BACKUP1_BACKUP_SHIFT 0 641 642/* Bit definitions for BACKUP2 */ 643#define PALMAS_BACKUP2_BACKUP_MASK 0xff 644#define PALMAS_BACKUP2_BACKUP_SHIFT 0 645 646/* Bit definitions for BACKUP3 */ 647#define PALMAS_BACKUP3_BACKUP_MASK 0xff 648#define PALMAS_BACKUP3_BACKUP_SHIFT 0 649 650/* Bit definitions for BACKUP4 */ 651#define PALMAS_BACKUP4_BACKUP_MASK 0xff 652#define PALMAS_BACKUP4_BACKUP_SHIFT 0 653 654/* Bit definitions for BACKUP5 */ 655#define PALMAS_BACKUP5_BACKUP_MASK 0xff 656#define PALMAS_BACKUP5_BACKUP_SHIFT 0 657 658/* Bit definitions for BACKUP6 */ 659#define PALMAS_BACKUP6_BACKUP_MASK 0xff 660#define PALMAS_BACKUP6_BACKUP_SHIFT 0 661 662/* Bit definitions for BACKUP7 */ 663#define PALMAS_BACKUP7_BACKUP_MASK 0xff 664#define PALMAS_BACKUP7_BACKUP_SHIFT 0 665 666/* Registers for function SMPS */ 667#define PALMAS_SMPS12_CTRL 0x0 668#define PALMAS_SMPS12_TSTEP 0x1 669#define PALMAS_SMPS12_FORCE 0x2 670#define PALMAS_SMPS12_VOLTAGE 0x3 671#define PALMAS_SMPS3_CTRL 0x4 672#define PALMAS_SMPS3_VOLTAGE 0x7 673#define PALMAS_SMPS45_CTRL 0x8 674#define PALMAS_SMPS45_TSTEP 0x9 675#define PALMAS_SMPS45_FORCE 0xA 676#define PALMAS_SMPS45_VOLTAGE 0xB 677#define PALMAS_SMPS6_CTRL 0xC 678#define PALMAS_SMPS6_TSTEP 0xD 679#define PALMAS_SMPS6_FORCE 0xE 680#define PALMAS_SMPS6_VOLTAGE 0xF 681#define PALMAS_SMPS7_CTRL 0x10 682#define PALMAS_SMPS7_VOLTAGE 0x13 683#define PALMAS_SMPS8_CTRL 0x14 684#define PALMAS_SMPS8_TSTEP 0x15 685#define PALMAS_SMPS8_FORCE 0x16 686#define PALMAS_SMPS8_VOLTAGE 0x17 687#define PALMAS_SMPS9_CTRL 0x18 688#define PALMAS_SMPS9_VOLTAGE 0x1B 689#define PALMAS_SMPS10_CTRL 0x1C 690#define PALMAS_SMPS10_STATUS 0x1F 691#define PALMAS_SMPS_CTRL 0x24 692#define PALMAS_SMPS_PD_CTRL 0x25 693#define PALMAS_SMPS_DITHER_EN 0x26 694#define PALMAS_SMPS_THERMAL_EN 0x27 695#define PALMAS_SMPS_THERMAL_STATUS 0x28 696#define PALMAS_SMPS_SHORT_STATUS 0x29 697#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A 698#define PALMAS_SMPS_POWERGOOD_MASK1 0x2B 699#define PALMAS_SMPS_POWERGOOD_MASK2 0x2C 700 701/* Bit definitions for SMPS12_CTRL */ 702#define PALMAS_SMPS12_CTRL_WR_S 0x80 703#define PALMAS_SMPS12_CTRL_WR_S_SHIFT 7 704#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40 705#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 6 706#define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30 707#define PALMAS_SMPS12_CTRL_STATUS_SHIFT 4 708#define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c 709#define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 2 710#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03 711#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0 712 713/* Bit definitions for SMPS12_TSTEP */ 714#define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03 715#define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0 716 717/* Bit definitions for SMPS12_FORCE */ 718#define PALMAS_SMPS12_FORCE_CMD 0x80 719#define PALMAS_SMPS12_FORCE_CMD_SHIFT 7 720#define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7f 721#define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0 722 723/* Bit definitions for SMPS12_VOLTAGE */ 724#define PALMAS_SMPS12_VOLTAGE_RANGE 0x80 725#define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 7 726#define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7f 727#define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0 728 729/* Bit definitions for SMPS3_CTRL */ 730#define PALMAS_SMPS3_CTRL_WR_S 0x80 731#define PALMAS_SMPS3_CTRL_WR_S_SHIFT 7 732#define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30 733#define PALMAS_SMPS3_CTRL_STATUS_SHIFT 4 734#define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c 735#define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 2 736#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03 737#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0 738 739/* Bit definitions for SMPS3_VOLTAGE */ 740#define PALMAS_SMPS3_VOLTAGE_RANGE 0x80 741#define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 7 742#define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7f 743#define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0 744 745/* Bit definitions for SMPS45_CTRL */ 746#define PALMAS_SMPS45_CTRL_WR_S 0x80 747#define PALMAS_SMPS45_CTRL_WR_S_SHIFT 7 748#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40 749#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 6 750#define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30 751#define PALMAS_SMPS45_CTRL_STATUS_SHIFT 4 752#define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c 753#define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 2 754#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03 755#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0 756 757/* Bit definitions for SMPS45_TSTEP */ 758#define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03 759#define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0 760 761/* Bit definitions for SMPS45_FORCE */ 762#define PALMAS_SMPS45_FORCE_CMD 0x80 763#define PALMAS_SMPS45_FORCE_CMD_SHIFT 7 764#define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7f 765#define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0 766 767/* Bit definitions for SMPS45_VOLTAGE */ 768#define PALMAS_SMPS45_VOLTAGE_RANGE 0x80 769#define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 7 770#define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7f 771#define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0 772 773/* Bit definitions for SMPS6_CTRL */ 774#define PALMAS_SMPS6_CTRL_WR_S 0x80 775#define PALMAS_SMPS6_CTRL_WR_S_SHIFT 7 776#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40 777#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 6 778#define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30 779#define PALMAS_SMPS6_CTRL_STATUS_SHIFT 4 780#define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c 781#define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 2 782#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03 783#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0 784 785/* Bit definitions for SMPS6_TSTEP */ 786#define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03 787#define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0 788 789/* Bit definitions for SMPS6_FORCE */ 790#define PALMAS_SMPS6_FORCE_CMD 0x80 791#define PALMAS_SMPS6_FORCE_CMD_SHIFT 7 792#define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7f 793#define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0 794 795/* Bit definitions for SMPS6_VOLTAGE */ 796#define PALMAS_SMPS6_VOLTAGE_RANGE 0x80 797#define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 7 798#define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7f 799#define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0 800 801/* Bit definitions for SMPS7_CTRL */ 802#define PALMAS_SMPS7_CTRL_WR_S 0x80 803#define PALMAS_SMPS7_CTRL_WR_S_SHIFT 7 804#define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30 805#define PALMAS_SMPS7_CTRL_STATUS_SHIFT 4 806#define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c 807#define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 2 808#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03 809#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0 810 811/* Bit definitions for SMPS7_VOLTAGE */ 812#define PALMAS_SMPS7_VOLTAGE_RANGE 0x80 813#define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 7 814#define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7f 815#define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0 816 817/* Bit definitions for SMPS8_CTRL */ 818#define PALMAS_SMPS8_CTRL_WR_S 0x80 819#define PALMAS_SMPS8_CTRL_WR_S_SHIFT 7 820#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40 821#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 6 822#define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30 823#define PALMAS_SMPS8_CTRL_STATUS_SHIFT 4 824#define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c 825#define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 2 826#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03 827#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0 828 829/* Bit definitions for SMPS8_TSTEP */ 830#define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03 831#define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0 832 833/* Bit definitions for SMPS8_FORCE */ 834#define PALMAS_SMPS8_FORCE_CMD 0x80 835#define PALMAS_SMPS8_FORCE_CMD_SHIFT 7 836#define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7f 837#define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0 838 839/* Bit definitions for SMPS8_VOLTAGE */ 840#define PALMAS_SMPS8_VOLTAGE_RANGE 0x80 841#define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 7 842#define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7f 843#define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0 844 845/* Bit definitions for SMPS9_CTRL */ 846#define PALMAS_SMPS9_CTRL_WR_S 0x80 847#define PALMAS_SMPS9_CTRL_WR_S_SHIFT 7 848#define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30 849#define PALMAS_SMPS9_CTRL_STATUS_SHIFT 4 850#define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c 851#define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 2 852#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03 853#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0 854 855/* Bit definitions for SMPS9_VOLTAGE */ 856#define PALMAS_SMPS9_VOLTAGE_RANGE 0x80 857#define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 7 858#define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7f 859#define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0 860 861/* Bit definitions for SMPS10_CTRL */ 862#define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0 863#define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 4 864#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0f 865#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0 866 867/* Bit definitions for SMPS10_STATUS */ 868#define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0f 869#define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0 870 871/* Bit definitions for SMPS_CTRL */ 872#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20 873#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 5 874#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10 875#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 4 876#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c 877#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 2 878#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03 879#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0 880 881/* Bit definitions for SMPS_PD_CTRL */ 882#define PALMAS_SMPS_PD_CTRL_SMPS9 0x40 883#define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 6 884#define PALMAS_SMPS_PD_CTRL_SMPS8 0x20 885#define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 5 886#define PALMAS_SMPS_PD_CTRL_SMPS7 0x10 887#define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 4 888#define PALMAS_SMPS_PD_CTRL_SMPS6 0x08 889#define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 3 890#define PALMAS_SMPS_PD_CTRL_SMPS45 0x04 891#define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 2 892#define PALMAS_SMPS_PD_CTRL_SMPS3 0x02 893#define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 1 894#define PALMAS_SMPS_PD_CTRL_SMPS12 0x01 895#define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0 896 897/* Bit definitions for SMPS_THERMAL_EN */ 898#define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40 899#define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 6 900#define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20 901#define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 5 902#define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08 903#define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 3 904#define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04 905#define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 2 906#define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01 907#define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0 908 909/* Bit definitions for SMPS_THERMAL_STATUS */ 910#define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40 911#define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 6 912#define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20 913#define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 5 914#define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08 915#define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 3 916#define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04 917#define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 2 918#define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01 919#define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0 920 921/* Bit definitions for SMPS_SHORT_STATUS */ 922#define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80 923#define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 7 924#define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40 925#define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 6 926#define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20 927#define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 5 928#define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10 929#define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 4 930#define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08 931#define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 3 932#define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04 933#define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 2 934#define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02 935#define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 1 936#define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01 937#define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0 938 939/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ 940#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40 941#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 6 942#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20 943#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 5 944#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10 945#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 4 946#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08 947#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 3 948#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04 949#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 2 950#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02 951#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 1 952#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01 953#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0 954 955/* Bit definitions for SMPS_POWERGOOD_MASK1 */ 956#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80 957#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 7 958#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40 959#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 6 960#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20 961#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 5 962#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10 963#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 4 964#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08 965#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 3 966#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04 967#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 2 968#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02 969#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 1 970#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01 971#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0 972 973/* Bit definitions for SMPS_POWERGOOD_MASK2 */ 974#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80 975#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7 976#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04 977#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 2 978#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02 979#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 1 980#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01 981#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0 982 983/* Registers for function LDO */ 984#define PALMAS_LDO1_CTRL 0x0 985#define PALMAS_LDO1_VOLTAGE 0x1 986#define PALMAS_LDO2_CTRL 0x2 987#define PALMAS_LDO2_VOLTAGE 0x3 988#define PALMAS_LDO3_CTRL 0x4 989#define PALMAS_LDO3_VOLTAGE 0x5 990#define PALMAS_LDO4_CTRL 0x6 991#define PALMAS_LDO4_VOLTAGE 0x7 992#define PALMAS_LDO5_CTRL 0x8 993#define PALMAS_LDO5_VOLTAGE 0x9 994#define PALMAS_LDO6_CTRL 0xA 995#define PALMAS_LDO6_VOLTAGE 0xB 996#define PALMAS_LDO7_CTRL 0xC 997#define PALMAS_LDO7_VOLTAGE 0xD 998#define PALMAS_LDO8_CTRL 0xE 999#define PALMAS_LDO8_VOLTAGE 0xF 1000#define PALMAS_LDO9_CTRL 0x10 1001#define PALMAS_LDO9_VOLTAGE 0x11 1002#define PALMAS_LDOLN_CTRL 0x12 1003#define PALMAS_LDOLN_VOLTAGE 0x13 1004#define PALMAS_LDOUSB_CTRL 0x14 1005#define PALMAS_LDOUSB_VOLTAGE 0x15 1006#define PALMAS_LDO_CTRL 0x1A 1007#define PALMAS_LDO_PD_CTRL1 0x1B 1008#define PALMAS_LDO_PD_CTRL2 0x1C 1009#define PALMAS_LDO_SHORT_STATUS1 0x1D 1010#define PALMAS_LDO_SHORT_STATUS2 0x1E 1011 1012/* Bit definitions for LDO1_CTRL */ 1013#define PALMAS_LDO1_CTRL_WR_S 0x80 1014#define PALMAS_LDO1_CTRL_WR_S_SHIFT 7 1015#define PALMAS_LDO1_CTRL_STATUS 0x10 1016#define PALMAS_LDO1_CTRL_STATUS_SHIFT 4 1017#define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04 1018#define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 2 1019#define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01 1020#define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0 1021 1022/* Bit definitions for LDO1_VOLTAGE */ 1023#define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3f 1024#define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0 1025 1026/* Bit definitions for LDO2_CTRL */ 1027#define PALMAS_LDO2_CTRL_WR_S 0x80 1028#define PALMAS_LDO2_CTRL_WR_S_SHIFT 7 1029#define PALMAS_LDO2_CTRL_STATUS 0x10 1030#define PALMAS_LDO2_CTRL_STATUS_SHIFT 4 1031#define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04 1032#define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 2 1033#define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01 1034#define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0 1035 1036/* Bit definitions for LDO2_VOLTAGE */ 1037#define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3f 1038#define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0 1039 1040/* Bit definitions for LDO3_CTRL */ 1041#define PALMAS_LDO3_CTRL_WR_S 0x80 1042#define PALMAS_LDO3_CTRL_WR_S_SHIFT 7 1043#define PALMAS_LDO3_CTRL_STATUS 0x10 1044#define PALMAS_LDO3_CTRL_STATUS_SHIFT 4 1045#define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04 1046#define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 2 1047#define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01 1048#define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0 1049 1050/* Bit definitions for LDO3_VOLTAGE */ 1051#define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3f 1052#define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0 1053 1054/* Bit definitions for LDO4_CTRL */ 1055#define PALMAS_LDO4_CTRL_WR_S 0x80 1056#define PALMAS_LDO4_CTRL_WR_S_SHIFT 7 1057#define PALMAS_LDO4_CTRL_STATUS 0x10 1058#define PALMAS_LDO4_CTRL_STATUS_SHIFT 4 1059#define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04 1060#define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 2 1061#define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01 1062#define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0 1063 1064/* Bit definitions for LDO4_VOLTAGE */ 1065#define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3f 1066#define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0 1067 1068/* Bit definitions for LDO5_CTRL */ 1069#define PALMAS_LDO5_CTRL_WR_S 0x80 1070#define PALMAS_LDO5_CTRL_WR_S_SHIFT 7 1071#define PALMAS_LDO5_CTRL_STATUS 0x10 1072#define PALMAS_LDO5_CTRL_STATUS_SHIFT 4 1073#define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04 1074#define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 2 1075#define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01 1076#define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0 1077 1078/* Bit definitions for LDO5_VOLTAGE */ 1079#define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3f 1080#define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0 1081 1082/* Bit definitions for LDO6_CTRL */ 1083#define PALMAS_LDO6_CTRL_WR_S 0x80 1084#define PALMAS_LDO6_CTRL_WR_S_SHIFT 7 1085#define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40 1086#define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 6 1087#define PALMAS_LDO6_CTRL_STATUS 0x10 1088#define PALMAS_LDO6_CTRL_STATUS_SHIFT 4 1089#define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04 1090#define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 2 1091#define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01 1092#define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0 1093 1094/* Bit definitions for LDO6_VOLTAGE */ 1095#define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3f 1096#define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0 1097 1098/* Bit definitions for LDO7_CTRL */ 1099#define PALMAS_LDO7_CTRL_WR_S 0x80 1100#define PALMAS_LDO7_CTRL_WR_S_SHIFT 7 1101#define PALMAS_LDO7_CTRL_STATUS 0x10 1102#define PALMAS_LDO7_CTRL_STATUS_SHIFT 4 1103#define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04 1104#define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 2 1105#define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01 1106#define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0 1107 1108/* Bit definitions for LDO7_VOLTAGE */ 1109#define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3f 1110#define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0 1111 1112/* Bit definitions for LDO8_CTRL */ 1113#define PALMAS_LDO8_CTRL_WR_S 0x80 1114#define PALMAS_LDO8_CTRL_WR_S_SHIFT 7 1115#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40 1116#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 6 1117#define PALMAS_LDO8_CTRL_STATUS 0x10 1118#define PALMAS_LDO8_CTRL_STATUS_SHIFT 4 1119#define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04 1120#define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 2 1121#define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01 1122#define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0 1123 1124/* Bit definitions for LDO8_VOLTAGE */ 1125#define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3f 1126#define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0 1127 1128/* Bit definitions for LDO9_CTRL */ 1129#define PALMAS_LDO9_CTRL_WR_S 0x80 1130#define PALMAS_LDO9_CTRL_WR_S_SHIFT 7 1131#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40 1132#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 6 1133#define PALMAS_LDO9_CTRL_STATUS 0x10 1134#define PALMAS_LDO9_CTRL_STATUS_SHIFT 4 1135#define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04 1136#define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 2 1137#define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01 1138#define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0 1139 1140/* Bit definitions for LDO9_VOLTAGE */ 1141#define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3f 1142#define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0 1143 1144/* Bit definitions for LDOLN_CTRL */ 1145#define PALMAS_LDOLN_CTRL_WR_S 0x80 1146#define PALMAS_LDOLN_CTRL_WR_S_SHIFT 7 1147#define PALMAS_LDOLN_CTRL_STATUS 0x10 1148#define PALMAS_LDOLN_CTRL_STATUS_SHIFT 4 1149#define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04 1150#define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 2 1151#define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01 1152#define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0 1153 1154/* Bit definitions for LDOLN_VOLTAGE */ 1155#define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3f 1156#define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0 1157 1158/* Bit definitions for LDOUSB_CTRL */ 1159#define PALMAS_LDOUSB_CTRL_WR_S 0x80 1160#define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 7 1161#define PALMAS_LDOUSB_CTRL_STATUS 0x10 1162#define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 4 1163#define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04 1164#define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 2 1165#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01 1166#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0 1167 1168/* Bit definitions for LDOUSB_VOLTAGE */ 1169#define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3f 1170#define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0 1171 1172/* Bit definitions for LDO_CTRL */ 1173#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01 1174#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0 1175 1176/* Bit definitions for LDO_PD_CTRL1 */ 1177#define PALMAS_LDO_PD_CTRL1_LDO8 0x80 1178#define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 7 1179#define PALMAS_LDO_PD_CTRL1_LDO7 0x40 1180#define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 6 1181#define PALMAS_LDO_PD_CTRL1_LDO6 0x20 1182#define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 5 1183#define PALMAS_LDO_PD_CTRL1_LDO5 0x10 1184#define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 4 1185#define PALMAS_LDO_PD_CTRL1_LDO4 0x08 1186#define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 3 1187#define PALMAS_LDO_PD_CTRL1_LDO3 0x04 1188#define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 2 1189#define PALMAS_LDO_PD_CTRL1_LDO2 0x02 1190#define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 1 1191#define PALMAS_LDO_PD_CTRL1_LDO1 0x01 1192#define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0 1193 1194/* Bit definitions for LDO_PD_CTRL2 */ 1195#define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04 1196#define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 2 1197#define PALMAS_LDO_PD_CTRL2_LDOLN 0x02 1198#define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 1 1199#define PALMAS_LDO_PD_CTRL2_LDO9 0x01 1200#define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0 1201 1202/* Bit definitions for LDO_SHORT_STATUS1 */ 1203#define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80 1204#define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 7 1205#define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40 1206#define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 6 1207#define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20 1208#define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 5 1209#define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10 1210#define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 4 1211#define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08 1212#define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 3 1213#define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04 1214#define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 2 1215#define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02 1216#define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 1 1217#define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01 1218#define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0 1219 1220/* Bit definitions for LDO_SHORT_STATUS2 */ 1221#define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08 1222#define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 3 1223#define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04 1224#define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 2 1225#define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02 1226#define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 1 1227#define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01 1228#define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0 1229 1230/* Registers for function PMU_CONTROL */ 1231#define PALMAS_DEV_CTRL 0x0 1232#define PALMAS_POWER_CTRL 0x1 1233#define PALMAS_VSYS_LO 0x2 1234#define PALMAS_VSYS_MON 0x3 1235#define PALMAS_VBAT_MON 0x4 1236#define PALMAS_WATCHDOG 0x5 1237#define PALMAS_BOOT_STATUS 0x6 1238#define PALMAS_BATTERY_BOUNCE 0x7 1239#define PALMAS_BACKUP_BATTERY_CTRL 0x8 1240#define PALMAS_LONG_PRESS_KEY 0x9 1241#define PALMAS_OSC_THERM_CTRL 0xA 1242#define PALMAS_BATDEBOUNCING 0xB 1243#define PALMAS_SWOFF_HWRST 0xF 1244#define PALMAS_SWOFF_COLDRST 0x10 1245#define PALMAS_SWOFF_STATUS 0x11 1246#define PALMAS_PMU_CONFIG 0x12 1247#define PALMAS_SPARE 0x14 1248#define PALMAS_PMU_SECONDARY_INT 0x15 1249#define PALMAS_SW_REVISION 0x17 1250#define PALMAS_EXT_CHRG_CTRL 0x18 1251#define PALMAS_PMU_SECONDARY_INT2 0x19 1252 1253/* Bit definitions for DEV_CTRL */ 1254#define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c 1255#define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 2 1256#define PALMAS_DEV_CTRL_SW_RST 0x02 1257#define PALMAS_DEV_CTRL_SW_RST_SHIFT 1 1258#define PALMAS_DEV_CTRL_DEV_ON 0x01 1259#define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0 1260 1261/* Bit definitions for POWER_CTRL */ 1262#define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04 1263#define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 2 1264#define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02 1265#define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 1 1266#define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01 1267#define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0 1268 1269/* Bit definitions for VSYS_LO */ 1270#define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1f 1271#define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0 1272 1273/* Bit definitions for VSYS_MON */ 1274#define PALMAS_VSYS_MON_ENABLE 0x80 1275#define PALMAS_VSYS_MON_ENABLE_SHIFT 7 1276#define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3f 1277#define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0 1278 1279/* Bit definitions for VBAT_MON */ 1280#define PALMAS_VBAT_MON_ENABLE 0x80 1281#define PALMAS_VBAT_MON_ENABLE_SHIFT 7 1282#define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3f 1283#define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0 1284 1285/* Bit definitions for WATCHDOG */ 1286#define PALMAS_WATCHDOG_LOCK 0x20 1287#define PALMAS_WATCHDOG_LOCK_SHIFT 5 1288#define PALMAS_WATCHDOG_ENABLE 0x10 1289#define PALMAS_WATCHDOG_ENABLE_SHIFT 4 1290#define PALMAS_WATCHDOG_MODE 0x08 1291#define PALMAS_WATCHDOG_MODE_SHIFT 3 1292#define PALMAS_WATCHDOG_TIMER_MASK 0x07 1293#define PALMAS_WATCHDOG_TIMER_SHIFT 0 1294 1295/* Bit definitions for BOOT_STATUS */ 1296#define PALMAS_BOOT_STATUS_BOOT1 0x02 1297#define PALMAS_BOOT_STATUS_BOOT1_SHIFT 1 1298#define PALMAS_BOOT_STATUS_BOOT0 0x01 1299#define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0 1300 1301/* Bit definitions for BATTERY_BOUNCE */ 1302#define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3f 1303#define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0 1304 1305/* Bit definitions for BACKUP_BATTERY_CTRL */ 1306#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80 1307#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 7 1308#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40 1309#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 6 1310#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20 1311#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 5 1312#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10 1313#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 4 1314#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08 1315#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 3 1316#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06 1317#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 1 1318#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01 1319#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0 1320 1321/* Bit definitions for LONG_PRESS_KEY */ 1322#define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80 1323#define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 7 1324#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10 1325#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 4 1326#define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c 1327#define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 2 1328#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03 1329#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0 1330 1331/* Bit definitions for OSC_THERM_CTRL */ 1332#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80 1333#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 7 1334#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40 1335#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 6 1336#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20 1337#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 5 1338#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10 1339#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 4 1340#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c 1341#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 2 1342#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02 1343#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 1 1344#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01 1345#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0 1346 1347/* Bit definitions for BATDEBOUNCING */ 1348#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80 1349#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 7 1350#define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78 1351#define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 3 1352#define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07 1353#define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0 1354 1355/* Bit definitions for SWOFF_HWRST */ 1356#define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80 1357#define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 7 1358#define PALMAS_SWOFF_HWRST_PWRDOWN 0x40 1359#define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 6 1360#define PALMAS_SWOFF_HWRST_WTD 0x20 1361#define PALMAS_SWOFF_HWRST_WTD_SHIFT 5 1362#define PALMAS_SWOFF_HWRST_TSHUT 0x10 1363#define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 4 1364#define PALMAS_SWOFF_HWRST_RESET_IN 0x08 1365#define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 3 1366#define PALMAS_SWOFF_HWRST_SW_RST 0x04 1367#define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 2 1368#define PALMAS_SWOFF_HWRST_VSYS_LO 0x02 1369#define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 1 1370#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01 1371#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0 1372 1373/* Bit definitions for SWOFF_COLDRST */ 1374#define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80 1375#define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 7 1376#define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40 1377#define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 6 1378#define PALMAS_SWOFF_COLDRST_WTD 0x20 1379#define PALMAS_SWOFF_COLDRST_WTD_SHIFT 5 1380#define PALMAS_SWOFF_COLDRST_TSHUT 0x10 1381#define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 4 1382#define PALMAS_SWOFF_COLDRST_RESET_IN 0x08 1383#define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 3 1384#define PALMAS_SWOFF_COLDRST_SW_RST 0x04 1385#define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 2 1386#define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02 1387#define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 1 1388#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01 1389#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0 1390 1391/* Bit definitions for SWOFF_STATUS */ 1392#define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80 1393#define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 7 1394#define PALMAS_SWOFF_STATUS_PWRDOWN 0x40 1395#define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 6 1396#define PALMAS_SWOFF_STATUS_WTD 0x20 1397#define PALMAS_SWOFF_STATUS_WTD_SHIFT 5 1398#define PALMAS_SWOFF_STATUS_TSHUT 0x10 1399#define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 4 1400#define PALMAS_SWOFF_STATUS_RESET_IN 0x08 1401#define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 3 1402#define PALMAS_SWOFF_STATUS_SW_RST 0x04 1403#define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 2 1404#define PALMAS_SWOFF_STATUS_VSYS_LO 0x02 1405#define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 1 1406#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01 1407#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0 1408 1409/* Bit definitions for PMU_CONFIG */ 1410#define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40 1411#define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 6 1412#define PALMAS_PMU_CONFIG_SPARE_MASK 0x30 1413#define PALMAS_PMU_CONFIG_SPARE_SHIFT 4 1414#define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c 1415#define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 2 1416#define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02 1417#define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 1 1418#define PALMAS_PMU_CONFIG_AUTODEVON 0x01 1419#define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0 1420 1421/* Bit definitions for SPARE */ 1422#define PALMAS_SPARE_SPARE_MASK 0xf8 1423#define PALMAS_SPARE_SPARE_SHIFT 3 1424#define PALMAS_SPARE_REGEN3_OD 0x04 1425#define PALMAS_SPARE_REGEN3_OD_SHIFT 2 1426#define PALMAS_SPARE_REGEN2_OD 0x02 1427#define PALMAS_SPARE_REGEN2_OD_SHIFT 1 1428#define PALMAS_SPARE_REGEN1_OD 0x01 1429#define PALMAS_SPARE_REGEN1_OD_SHIFT 0 1430 1431/* Bit definitions for PMU_SECONDARY_INT */ 1432#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80 1433#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 7 1434#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40 1435#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 6 1436#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20 1437#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 5 1438#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10 1439#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 4 1440#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08 1441#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 3 1442#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04 1443#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 2 1444#define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02 1445#define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 1 1446#define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01 1447#define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0 1448 1449/* Bit definitions for SW_REVISION */ 1450#define PALMAS_SW_REVISION_SW_REVISION_MASK 0xff 1451#define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0 1452 1453/* Bit definitions for EXT_CHRG_CTRL */ 1454#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80 1455#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 7 1456#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40 1457#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 6 1458#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08 1459#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 3 1460#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04 1461#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 2 1462#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02 1463#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 1 1464#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01 1465#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0 1466 1467/* Bit definitions for PMU_SECONDARY_INT2 */ 1468#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20 1469#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 5 1470#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10 1471#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 4 1472#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02 1473#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 1 1474#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01 1475#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0 1476 1477/* Registers for function RESOURCE */ 1478#define PALMAS_CLK32KG_CTRL 0x0 1479#define PALMAS_CLK32KGAUDIO_CTRL 0x1 1480#define PALMAS_REGEN1_CTRL 0x2 1481#define PALMAS_REGEN2_CTRL 0x3 1482#define PALMAS_SYSEN1_CTRL 0x4 1483#define PALMAS_SYSEN2_CTRL 0x5 1484#define PALMAS_NSLEEP_RES_ASSIGN 0x6 1485#define PALMAS_NSLEEP_SMPS_ASSIGN 0x7 1486#define PALMAS_NSLEEP_LDO_ASSIGN1 0x8 1487#define PALMAS_NSLEEP_LDO_ASSIGN2 0x9 1488#define PALMAS_ENABLE1_RES_ASSIGN 0xA 1489#define PALMAS_ENABLE1_SMPS_ASSIGN 0xB 1490#define PALMAS_ENABLE1_LDO_ASSIGN1 0xC 1491#define PALMAS_ENABLE1_LDO_ASSIGN2 0xD 1492#define PALMAS_ENABLE2_RES_ASSIGN 0xE 1493#define PALMAS_ENABLE2_SMPS_ASSIGN 0xF 1494#define PALMAS_ENABLE2_LDO_ASSIGN1 0x10 1495#define PALMAS_ENABLE2_LDO_ASSIGN2 0x11 1496#define PALMAS_REGEN3_CTRL 0x12 1497 1498/* Bit definitions for CLK32KG_CTRL */ 1499#define PALMAS_CLK32KG_CTRL_STATUS 0x10 1500#define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 4 1501#define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04 1502#define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 2 1503#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01 1504#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0 1505 1506/* Bit definitions for CLK32KGAUDIO_CTRL */ 1507#define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10 1508#define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 4 1509#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08 1510#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 3 1511#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04 1512#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 2 1513#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01 1514#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0 1515 1516/* Bit definitions for REGEN1_CTRL */ 1517#define PALMAS_REGEN1_CTRL_STATUS 0x10 1518#define PALMAS_REGEN1_CTRL_STATUS_SHIFT 4 1519#define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04 1520#define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 2 1521#define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01 1522#define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0 1523 1524/* Bit definitions for REGEN2_CTRL */ 1525#define PALMAS_REGEN2_CTRL_STATUS 0x10 1526#define PALMAS_REGEN2_CTRL_STATUS_SHIFT 4 1527#define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04 1528#define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 2 1529#define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01 1530#define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0 1531 1532/* Bit definitions for SYSEN1_CTRL */ 1533#define PALMAS_SYSEN1_CTRL_STATUS 0x10 1534#define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 4 1535#define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04 1536#define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 2 1537#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01 1538#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0 1539 1540/* Bit definitions for SYSEN2_CTRL */ 1541#define PALMAS_SYSEN2_CTRL_STATUS 0x10 1542#define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 4 1543#define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04 1544#define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 2 1545#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01 1546#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0 1547 1548/* Bit definitions for NSLEEP_RES_ASSIGN */ 1549#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40 1550#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 6 1551#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20 1552#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 1553#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10 1554#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 4 1555#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08 1556#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 3 1557#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04 1558#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 2 1559#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02 1560#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 1 1561#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01 1562#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0 1563 1564/* Bit definitions for NSLEEP_SMPS_ASSIGN */ 1565#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80 1566#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 7 1567#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40 1568#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 6 1569#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20 1570#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 5 1571#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10 1572#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 4 1573#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08 1574#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 3 1575#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04 1576#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 2 1577#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02 1578#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 1 1579#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01 1580#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0 1581 1582/* Bit definitions for NSLEEP_LDO_ASSIGN1 */ 1583#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80 1584#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 7 1585#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40 1586#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 6 1587#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20 1588#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 5 1589#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10 1590#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 4 1591#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08 1592#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 3 1593#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04 1594#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 2 1595#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02 1596#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 1 1597#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01 1598#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0 1599 1600/* Bit definitions for NSLEEP_LDO_ASSIGN2 */ 1601#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04 1602#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 2 1603#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02 1604#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 1 1605#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01 1606#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0 1607 1608/* Bit definitions for ENABLE1_RES_ASSIGN */ 1609#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40 1610#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 6 1611#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20 1612#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 1613#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10 1614#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 4 1615#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08 1616#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 3 1617#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04 1618#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 2 1619#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02 1620#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 1 1621#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01 1622#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0 1623 1624/* Bit definitions for ENABLE1_SMPS_ASSIGN */ 1625#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80 1626#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 7 1627#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40 1628#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 6 1629#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20 1630#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 5 1631#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10 1632#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 4 1633#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08 1634#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 3 1635#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04 1636#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 2 1637#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02 1638#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 1 1639#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01 1640#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0 1641 1642/* Bit definitions for ENABLE1_LDO_ASSIGN1 */ 1643#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80 1644#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 7 1645#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40 1646#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 6 1647#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20 1648#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 5 1649#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10 1650#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 4 1651#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08 1652#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 3 1653#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04 1654#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 2 1655#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02 1656#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 1 1657#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01 1658#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0 1659 1660/* Bit definitions for ENABLE1_LDO_ASSIGN2 */ 1661#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04 1662#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 2 1663#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02 1664#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 1 1665#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01 1666#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0 1667 1668/* Bit definitions for ENABLE2_RES_ASSIGN */ 1669#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40 1670#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 6 1671#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20 1672#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 1673#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10 1674#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 4 1675#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08 1676#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 3 1677#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04 1678#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 2 1679#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02 1680#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 1 1681#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01 1682#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0 1683 1684/* Bit definitions for ENABLE2_SMPS_ASSIGN */ 1685#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80 1686#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 7 1687#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40 1688#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 6 1689#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20 1690#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 5 1691#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10 1692#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 4 1693#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08 1694#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 3 1695#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04 1696#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 2 1697#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02 1698#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 1 1699#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01 1700#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0 1701 1702/* Bit definitions for ENABLE2_LDO_ASSIGN1 */ 1703#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80 1704#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 7 1705#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40 1706#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 6 1707#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20 1708#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 5 1709#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10 1710#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 4 1711#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08 1712#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 3 1713#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04 1714#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 2 1715#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02 1716#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 1 1717#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01 1718#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0 1719 1720/* Bit definitions for ENABLE2_LDO_ASSIGN2 */ 1721#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04 1722#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 2 1723#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02 1724#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 1 1725#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01 1726#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0 1727 1728/* Bit definitions for REGEN3_CTRL */ 1729#define PALMAS_REGEN3_CTRL_STATUS 0x10 1730#define PALMAS_REGEN3_CTRL_STATUS_SHIFT 4 1731#define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04 1732#define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 2 1733#define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01 1734#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0 1735 1736/* Registers for function PAD_CONTROL */ 1737#define PALMAS_PU_PD_INPUT_CTRL1 0x0 1738#define PALMAS_PU_PD_INPUT_CTRL2 0x1 1739#define PALMAS_PU_PD_INPUT_CTRL3 0x2 1740#define PALMAS_OD_OUTPUT_CTRL 0x4 1741#define PALMAS_POLARITY_CTRL 0x5 1742#define PALMAS_PRIMARY_SECONDARY_PAD1 0x6 1743#define PALMAS_PRIMARY_SECONDARY_PAD2 0x7 1744#define PALMAS_I2C_SPI 0x8 1745#define PALMAS_PU_PD_INPUT_CTRL4 0x9 1746#define PALMAS_PRIMARY_SECONDARY_PAD3 0xA 1747 1748/* Bit definitions for PU_PD_INPUT_CTRL1 */ 1749#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40 1750#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 6 1751#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20 1752#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 5 1753#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10 1754#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 4 1755#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04 1756#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 2 1757#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02 1758#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 1 1759 1760/* Bit definitions for PU_PD_INPUT_CTRL2 */ 1761#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20 1762#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 5 1763#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10 1764#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 4 1765#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08 1766#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 3 1767#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04 1768#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 2 1769#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02 1770#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 1 1771#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01 1772#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0 1773 1774/* Bit definitions for PU_PD_INPUT_CTRL3 */ 1775#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40 1776#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 6 1777#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10 1778#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 4 1779#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04 1780#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 2 1781#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01 1782#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0 1783 1784/* Bit definitions for OD_OUTPUT_CTRL */ 1785#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80 1786#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 7 1787#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40 1788#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 6 1789#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20 1790#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 5 1791#define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08 1792#define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 3 1793 1794/* Bit definitions for POLARITY_CTRL */ 1795#define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80 1796#define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 7 1797#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40 1798#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 6 1799#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20 1800#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 5 1801#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10 1802#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 4 1803#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08 1804#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 3 1805#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04 1806#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 2 1807#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02 1808#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 1 1809#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01 1810#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0 1811 1812/* Bit definitions for PRIMARY_SECONDARY_PAD1 */ 1813#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80 1814#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 7 1815#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60 1816#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 5 1817#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18 1818#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 3 1819#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04 1820#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 2 1821#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02 1822#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 1 1823#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01 1824#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0 1825 1826/* Bit definitions for PRIMARY_SECONDARY_PAD2 */ 1827#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30 1828#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 4 1829#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08 1830#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 3 1831#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06 1832#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 1 1833#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01 1834#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0 1835 1836/* Bit definitions for I2C_SPI */ 1837#define PALMAS_I2C_SPI_I2C2OTP_EN 0x80 1838#define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 7 1839#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40 1840#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 6 1841#define PALMAS_I2C_SPI_ID_I2C2 0x20 1842#define PALMAS_I2C_SPI_ID_I2C2_SHIFT 5 1843#define PALMAS_I2C_SPI_I2C_SPI 0x10 1844#define PALMAS_I2C_SPI_I2C_SPI_SHIFT 4 1845#define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0f 1846#define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0 1847 1848/* Bit definitions for PU_PD_INPUT_CTRL4 */ 1849#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40 1850#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 6 1851#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10 1852#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 4 1853#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04 1854#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 2 1855#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01 1856#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0 1857 1858/* Bit definitions for PRIMARY_SECONDARY_PAD3 */ 1859#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02 1860#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 1 1861#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01 1862#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0 1863 1864/* Registers for function LED_PWM */ 1865#define PALMAS_LED_PERIOD_CTRL 0x0 1866#define PALMAS_LED_CTRL 0x1 1867#define PALMAS_PWM_CTRL1 0x2 1868#define PALMAS_PWM_CTRL2 0x3 1869 1870/* Bit definitions for LED_PERIOD_CTRL */ 1871#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38 1872#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 3 1873#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07 1874#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0 1875 1876/* Bit definitions for LED_CTRL */ 1877#define PALMAS_LED_CTRL_LED_2_SEQ 0x20 1878#define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 5 1879#define PALMAS_LED_CTRL_LED_1_SEQ 0x10 1880#define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 4 1881#define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c 1882#define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 2 1883#define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03 1884#define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0 1885 1886/* Bit definitions for PWM_CTRL1 */ 1887#define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02 1888#define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 1 1889#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01 1890#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0 1891 1892/* Bit definitions for PWM_CTRL2 */ 1893#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xff 1894#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0 1895 1896/* Registers for function INTERRUPT */ 1897#define PALMAS_INT1_STATUS 0x0 1898#define PALMAS_INT1_MASK 0x1 1899#define PALMAS_INT1_LINE_STATE 0x2 1900#define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x3 1901#define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x4 1902#define PALMAS_INT2_STATUS 0x5 1903#define PALMAS_INT2_MASK 0x6 1904#define PALMAS_INT2_LINE_STATE 0x7 1905#define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x8 1906#define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x9 1907#define PALMAS_INT3_STATUS 0xA 1908#define PALMAS_INT3_MASK 0xB 1909#define PALMAS_INT3_LINE_STATE 0xC 1910#define PALMAS_INT3_EDGE_DETECT1_RESERVED 0xD 1911#define PALMAS_INT3_EDGE_DETECT2_RESERVED 0xE 1912#define PALMAS_INT4_STATUS 0xF 1913#define PALMAS_INT4_MASK 0x10 1914#define PALMAS_INT4_LINE_STATE 0x11 1915#define PALMAS_INT4_EDGE_DETECT1 0x12 1916#define PALMAS_INT4_EDGE_DETECT2 0x13 1917#define PALMAS_INT_CTRL 0x14 1918 1919/* Bit definitions for INT1_STATUS */ 1920#define PALMAS_INT1_STATUS_VBAT_MON 0x80 1921#define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 7 1922#define PALMAS_INT1_STATUS_VSYS_MON 0x40 1923#define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 6 1924#define PALMAS_INT1_STATUS_HOTDIE 0x20 1925#define PALMAS_INT1_STATUS_HOTDIE_SHIFT 5 1926#define PALMAS_INT1_STATUS_PWRDOWN 0x10 1927#define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 4 1928#define PALMAS_INT1_STATUS_RPWRON 0x08 1929#define PALMAS_INT1_STATUS_RPWRON_SHIFT 3 1930#define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04 1931#define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 2 1932#define PALMAS_INT1_STATUS_PWRON 0x02 1933#define PALMAS_INT1_STATUS_PWRON_SHIFT 1 1934#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01 1935#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0 1936 1937/* Bit definitions for INT1_MASK */ 1938#define PALMAS_INT1_MASK_VBAT_MON 0x80 1939#define PALMAS_INT1_MASK_VBAT_MON_SHIFT 7 1940#define PALMAS_INT1_MASK_VSYS_MON 0x40 1941#define PALMAS_INT1_MASK_VSYS_MON_SHIFT 6 1942#define PALMAS_INT1_MASK_HOTDIE 0x20 1943#define PALMAS_INT1_MASK_HOTDIE_SHIFT 5 1944#define PALMAS_INT1_MASK_PWRDOWN 0x10 1945#define PALMAS_INT1_MASK_PWRDOWN_SHIFT 4 1946#define PALMAS_INT1_MASK_RPWRON 0x08 1947#define PALMAS_INT1_MASK_RPWRON_SHIFT 3 1948#define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04 1949#define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 2 1950#define PALMAS_INT1_MASK_PWRON 0x02 1951#define PALMAS_INT1_MASK_PWRON_SHIFT 1 1952#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01 1953#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0 1954 1955/* Bit definitions for INT1_LINE_STATE */ 1956#define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80 1957#define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 7 1958#define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40 1959#define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 6 1960#define PALMAS_INT1_LINE_STATE_HOTDIE 0x20 1961#define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 5 1962#define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10 1963#define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 4 1964#define PALMAS_INT1_LINE_STATE_RPWRON 0x08 1965#define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 3 1966#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04 1967#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 2 1968#define PALMAS_INT1_LINE_STATE_PWRON 0x02 1969#define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 1 1970#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01 1971#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0 1972 1973/* Bit definitions for INT2_STATUS */ 1974#define PALMAS_INT2_STATUS_VAC_ACOK 0x80 1975#define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 7 1976#define PALMAS_INT2_STATUS_SHORT 0x40 1977#define PALMAS_INT2_STATUS_SHORT_SHIFT 6 1978#define PALMAS_INT2_STATUS_FBI_BB 0x20 1979#define PALMAS_INT2_STATUS_FBI_BB_SHIFT 5 1980#define PALMAS_INT2_STATUS_RESET_IN 0x10 1981#define PALMAS_INT2_STATUS_RESET_IN_SHIFT 4 1982#define PALMAS_INT2_STATUS_BATREMOVAL 0x08 1983#define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 3 1984#define PALMAS_INT2_STATUS_WDT 0x04 1985#define PALMAS_INT2_STATUS_WDT_SHIFT 2 1986#define PALMAS_INT2_STATUS_RTC_TIMER 0x02 1987#define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 1 1988#define PALMAS_INT2_STATUS_RTC_ALARM 0x01 1989#define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0 1990 1991/* Bit definitions for INT2_MASK */ 1992#define PALMAS_INT2_MASK_VAC_ACOK 0x80 1993#define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 7 1994#define PALMAS_INT2_MASK_SHORT 0x40 1995#define PALMAS_INT2_MASK_SHORT_SHIFT 6 1996#define PALMAS_INT2_MASK_FBI_BB 0x20 1997#define PALMAS_INT2_MASK_FBI_BB_SHIFT 5 1998#define PALMAS_INT2_MASK_RESET_IN 0x10 1999#define PALMAS_INT2_MASK_RESET_IN_SHIFT 4 2000#define PALMAS_INT2_MASK_BATREMOVAL 0x08 2001#define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 3 2002#define PALMAS_INT2_MASK_WDT 0x04 2003#define PALMAS_INT2_MASK_WDT_SHIFT 2 2004#define PALMAS_INT2_MASK_RTC_TIMER 0x02 2005#define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 1 2006#define PALMAS_INT2_MASK_RTC_ALARM 0x01 2007#define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0 2008 2009/* Bit definitions for INT2_LINE_STATE */ 2010#define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80 2011#define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 7 2012#define PALMAS_INT2_LINE_STATE_SHORT 0x40 2013#define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 6 2014#define PALMAS_INT2_LINE_STATE_FBI_BB 0x20 2015#define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 5 2016#define PALMAS_INT2_LINE_STATE_RESET_IN 0x10 2017#define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 4 2018#define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08 2019#define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 3 2020#define PALMAS_INT2_LINE_STATE_WDT 0x04 2021#define PALMAS_INT2_LINE_STATE_WDT_SHIFT 2 2022#define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02 2023#define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 1 2024#define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01 2025#define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0 2026 2027/* Bit definitions for INT3_STATUS */ 2028#define PALMAS_INT3_STATUS_VBUS 0x80 2029#define PALMAS_INT3_STATUS_VBUS_SHIFT 7 2030#define PALMAS_INT3_STATUS_VBUS_OTG 0x40 2031#define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 6 2032#define PALMAS_INT3_STATUS_ID 0x20 2033#define PALMAS_INT3_STATUS_ID_SHIFT 5 2034#define PALMAS_INT3_STATUS_ID_OTG 0x10 2035#define PALMAS_INT3_STATUS_ID_OTG_SHIFT 4 2036#define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08 2037#define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 3 2038#define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04 2039#define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 2 2040#define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02 2041#define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 1 2042#define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01 2043#define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0 2044 2045/* Bit definitions for INT3_MASK */ 2046#define PALMAS_INT3_MASK_VBUS 0x80 2047#define PALMAS_INT3_MASK_VBUS_SHIFT 7 2048#define PALMAS_INT3_MASK_VBUS_OTG 0x40 2049#define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 6 2050#define PALMAS_INT3_MASK_ID 0x20 2051#define PALMAS_INT3_MASK_ID_SHIFT 5 2052#define PALMAS_INT3_MASK_ID_OTG 0x10 2053#define PALMAS_INT3_MASK_ID_OTG_SHIFT 4 2054#define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08 2055#define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 3 2056#define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04 2057#define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 2 2058#define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02 2059#define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 1 2060#define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01 2061#define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0 2062 2063/* Bit definitions for INT3_LINE_STATE */ 2064#define PALMAS_INT3_LINE_STATE_VBUS 0x80 2065#define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 7 2066#define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40 2067#define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 6 2068#define PALMAS_INT3_LINE_STATE_ID 0x20 2069#define PALMAS_INT3_LINE_STATE_ID_SHIFT 5 2070#define PALMAS_INT3_LINE_STATE_ID_OTG 0x10 2071#define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 4 2072#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08 2073#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 3 2074#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04 2075#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 2 2076#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02 2077#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 1 2078#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01 2079#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0 2080 2081/* Bit definitions for INT4_STATUS */ 2082#define PALMAS_INT4_STATUS_GPIO_7 0x80 2083#define PALMAS_INT4_STATUS_GPIO_7_SHIFT 7 2084#define PALMAS_INT4_STATUS_GPIO_6 0x40 2085#define PALMAS_INT4_STATUS_GPIO_6_SHIFT 6 2086#define PALMAS_INT4_STATUS_GPIO_5 0x20 2087#define PALMAS_INT4_STATUS_GPIO_5_SHIFT 5 2088#define PALMAS_INT4_STATUS_GPIO_4 0x10 2089#define PALMAS_INT4_STATUS_GPIO_4_SHIFT 4 2090#define PALMAS_INT4_STATUS_GPIO_3 0x08 2091#define PALMAS_INT4_STATUS_GPIO_3_SHIFT 3 2092#define PALMAS_INT4_STATUS_GPIO_2 0x04 2093#define PALMAS_INT4_STATUS_GPIO_2_SHIFT 2 2094#define PALMAS_INT4_STATUS_GPIO_1 0x02 2095#define PALMAS_INT4_STATUS_GPIO_1_SHIFT 1 2096#define PALMAS_INT4_STATUS_GPIO_0 0x01 2097#define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0 2098 2099/* Bit definitions for INT4_MASK */ 2100#define PALMAS_INT4_MASK_GPIO_7 0x80 2101#define PALMAS_INT4_MASK_GPIO_7_SHIFT 7 2102#define PALMAS_INT4_MASK_GPIO_6 0x40 2103#define PALMAS_INT4_MASK_GPIO_6_SHIFT 6 2104#define PALMAS_INT4_MASK_GPIO_5 0x20 2105#define PALMAS_INT4_MASK_GPIO_5_SHIFT 5 2106#define PALMAS_INT4_MASK_GPIO_4 0x10 2107#define PALMAS_INT4_MASK_GPIO_4_SHIFT 4 2108#define PALMAS_INT4_MASK_GPIO_3 0x08 2109#define PALMAS_INT4_MASK_GPIO_3_SHIFT 3 2110#define PALMAS_INT4_MASK_GPIO_2 0x04 2111#define PALMAS_INT4_MASK_GPIO_2_SHIFT 2 2112#define PALMAS_INT4_MASK_GPIO_1 0x02 2113#define PALMAS_INT4_MASK_GPIO_1_SHIFT 1 2114#define PALMAS_INT4_MASK_GPIO_0 0x01 2115#define PALMAS_INT4_MASK_GPIO_0_SHIFT 0 2116 2117/* Bit definitions for INT4_LINE_STATE */ 2118#define PALMAS_INT4_LINE_STATE_GPIO_7 0x80 2119#define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 7 2120#define PALMAS_INT4_LINE_STATE_GPIO_6 0x40 2121#define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 6 2122#define PALMAS_INT4_LINE_STATE_GPIO_5 0x20 2123#define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 5 2124#define PALMAS_INT4_LINE_STATE_GPIO_4 0x10 2125#define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 4 2126#define PALMAS_INT4_LINE_STATE_GPIO_3 0x08 2127#define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 3 2128#define PALMAS_INT4_LINE_STATE_GPIO_2 0x04 2129#define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 2 2130#define PALMAS_INT4_LINE_STATE_GPIO_1 0x02 2131#define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 1 2132#define PALMAS_INT4_LINE_STATE_GPIO_0 0x01 2133#define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0 2134 2135/* Bit definitions for INT4_EDGE_DETECT1 */ 2136#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80 2137#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 7 2138#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40 2139#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 6 2140#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20 2141#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 5 2142#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10 2143#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 4 2144#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08 2145#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 3 2146#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04 2147#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 2 2148#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02 2149#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 1 2150#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01 2151#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0 2152 2153/* Bit definitions for INT4_EDGE_DETECT2 */ 2154#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80 2155#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 7 2156#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40 2157#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 6 2158#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20 2159#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 5 2160#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10 2161#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 4 2162#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08 2163#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 3 2164#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04 2165#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 2 2166#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02 2167#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 1 2168#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01 2169#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0 2170 2171/* Bit definitions for INT_CTRL */ 2172#define PALMAS_INT_CTRL_INT_PENDING 0x04 2173#define PALMAS_INT_CTRL_INT_PENDING_SHIFT 2 2174#define PALMAS_INT_CTRL_INT_CLEAR 0x01 2175#define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0 2176 2177/* Registers for function USB_OTG */ 2178#define PALMAS_USB_WAKEUP 0x3 2179#define PALMAS_USB_VBUS_CTRL_SET 0x4 2180#define PALMAS_USB_VBUS_CTRL_CLR 0x5 2181#define PALMAS_USB_ID_CTRL_SET 0x6 2182#define PALMAS_USB_ID_CTRL_CLEAR 0x7 2183#define PALMAS_USB_VBUS_INT_SRC 0x8 2184#define PALMAS_USB_VBUS_INT_LATCH_SET 0x9 2185#define PALMAS_USB_VBUS_INT_LATCH_CLR 0xA 2186#define PALMAS_USB_VBUS_INT_EN_LO_SET 0xB 2187#define PALMAS_USB_VBUS_INT_EN_LO_CLR 0xC 2188#define PALMAS_USB_VBUS_INT_EN_HI_SET 0xD 2189#define PALMAS_USB_VBUS_INT_EN_HI_CLR 0xE 2190#define PALMAS_USB_ID_INT_SRC 0xF 2191#define PALMAS_USB_ID_INT_LATCH_SET 0x10 2192#define PALMAS_USB_ID_INT_LATCH_CLR 0x11 2193#define PALMAS_USB_ID_INT_EN_LO_SET 0x12 2194#define PALMAS_USB_ID_INT_EN_LO_CLR 0x13 2195#define PALMAS_USB_ID_INT_EN_HI_SET 0x14 2196#define PALMAS_USB_ID_INT_EN_HI_CLR 0x15 2197#define PALMAS_USB_OTG_ADP_CTRL 0x16 2198#define PALMAS_USB_OTG_ADP_HIGH 0x17 2199#define PALMAS_USB_OTG_ADP_LOW 0x18 2200#define PALMAS_USB_OTG_ADP_RISE 0x19 2201#define PALMAS_USB_OTG_REVISION 0x1A 2202 2203/* Bit definitions for USB_WAKEUP */ 2204#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01 2205#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0 2206 2207/* Bit definitions for USB_VBUS_CTRL_SET */ 2208#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80 2209#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 7 2210#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20 2211#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 5 2212#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10 2213#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 4 2214#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08 2215#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 3 2216#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04 2217#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 2 2218 2219/* Bit definitions for USB_VBUS_CTRL_CLR */ 2220#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80 2221#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 7 2222#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20 2223#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 5 2224#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10 2225#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 4 2226#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08 2227#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 3 2228#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04 2229#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 2 2230 2231/* Bit definitions for USB_ID_CTRL_SET */ 2232#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80 2233#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 7 2234#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40 2235#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 6 2236#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20 2237#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 5 2238#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10 2239#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 4 2240#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08 2241#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 3 2242#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04 2243#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 2 2244 2245/* Bit definitions for USB_ID_CTRL_CLEAR */ 2246#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80 2247#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 7 2248#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40 2249#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 6 2250#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20 2251#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 5 2252#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10 2253#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 4 2254#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08 2255#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 3 2256#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04 2257#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 2 2258 2259/* Bit definitions for USB_VBUS_INT_SRC */ 2260#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80 2261#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 7 2262#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40 2263#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 6 2264#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20 2265#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 5 2266#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08 2267#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 3 2268#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04 2269#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 2 2270#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02 2271#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 1 2272#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01 2273#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0 2274 2275/* Bit definitions for USB_VBUS_INT_LATCH_SET */ 2276#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80 2277#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 7 2278#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40 2279#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 6 2280#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20 2281#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 5 2282#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10 2283#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 4 2284#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08 2285#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 3 2286#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04 2287#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 2 2288#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02 2289#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 1 2290#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01 2291#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0 2292 2293/* Bit definitions for USB_VBUS_INT_LATCH_CLR */ 2294#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80 2295#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 7 2296#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40 2297#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 6 2298#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20 2299#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 5 2300#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10 2301#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 4 2302#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08 2303#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 3 2304#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04 2305#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 2 2306#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02 2307#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 1 2308#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01 2309#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0 2310 2311/* Bit definitions for USB_VBUS_INT_EN_LO_SET */ 2312#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80 2313#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 7 2314#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40 2315#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 6 2316#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20 2317#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 5 2318#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08 2319#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 3 2320#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04 2321#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 2 2322#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02 2323#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 1 2324#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01 2325#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0 2326 2327/* Bit definitions for USB_VBUS_INT_EN_LO_CLR */ 2328#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80 2329#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 7 2330#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40 2331#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 6 2332#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20 2333#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 5 2334#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08 2335#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 3 2336#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04 2337#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 2 2338#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02 2339#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 1 2340#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01 2341#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0 2342 2343/* Bit definitions for USB_VBUS_INT_EN_HI_SET */ 2344#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80 2345#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 7 2346#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40 2347#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 6 2348#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20 2349#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 5 2350#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10 2351#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 4 2352#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08 2353#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 3 2354#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04 2355#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 2 2356#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02 2357#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 1 2358#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01 2359#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0 2360 2361/* Bit definitions for USB_VBUS_INT_EN_HI_CLR */ 2362#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80 2363#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 7 2364#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40 2365#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 6 2366#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20 2367#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 5 2368#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10 2369#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 4 2370#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08 2371#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 3 2372#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04 2373#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 2 2374#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02 2375#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 1 2376#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01 2377#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0 2378 2379/* Bit definitions for USB_ID_INT_SRC */ 2380#define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10 2381#define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 4 2382#define PALMAS_USB_ID_INT_SRC_ID_A 0x08 2383#define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 3 2384#define PALMAS_USB_ID_INT_SRC_ID_B 0x04 2385#define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 2 2386#define PALMAS_USB_ID_INT_SRC_ID_C 0x02 2387#define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 1 2388#define PALMAS_USB_ID_INT_SRC_ID_GND 0x01 2389#define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0 2390 2391/* Bit definitions for USB_ID_INT_LATCH_SET */ 2392#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10 2393#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 4 2394#define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08 2395#define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 3 2396#define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04 2397#define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 2 2398#define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02 2399#define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 1 2400#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01 2401#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0 2402 2403/* Bit definitions for USB_ID_INT_LATCH_CLR */ 2404#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10 2405#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 4 2406#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08 2407#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 3 2408#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04 2409#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 2 2410#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02 2411#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 1 2412#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01 2413#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0 2414 2415/* Bit definitions for USB_ID_INT_EN_LO_SET */ 2416#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10 2417#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 4 2418#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08 2419#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 3 2420#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04 2421#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 2 2422#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02 2423#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 1 2424#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01 2425#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0 2426 2427/* Bit definitions for USB_ID_INT_EN_LO_CLR */ 2428#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10 2429#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 4 2430#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08 2431#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 3 2432#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04 2433#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 2 2434#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02 2435#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 1 2436#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01 2437#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0 2438 2439/* Bit definitions for USB_ID_INT_EN_HI_SET */ 2440#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10 2441#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 4 2442#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08 2443#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 3 2444#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04 2445#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 2 2446#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02 2447#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 1 2448#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01 2449#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0 2450 2451/* Bit definitions for USB_ID_INT_EN_HI_CLR */ 2452#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10 2453#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 4 2454#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08 2455#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 3 2456#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04 2457#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 2 2458#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02 2459#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 1 2460#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01 2461#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0 2462 2463/* Bit definitions for USB_OTG_ADP_CTRL */ 2464#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04 2465#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 2 2466#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03 2467#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0 2468 2469/* Bit definitions for USB_OTG_ADP_HIGH */ 2470#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xff 2471#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0 2472 2473/* Bit definitions for USB_OTG_ADP_LOW */ 2474#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xff 2475#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0 2476 2477/* Bit definitions for USB_OTG_ADP_RISE */ 2478#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xff 2479#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0 2480 2481/* Bit definitions for USB_OTG_REVISION */ 2482#define PALMAS_USB_OTG_REVISION_OTG_REV 0x01 2483#define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0 2484 2485/* Registers for function VIBRATOR */ 2486#define PALMAS_VIBRA_CTRL 0x0 2487 2488/* Bit definitions for VIBRA_CTRL */ 2489#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06 2490#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 1 2491#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01 2492#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0 2493 2494/* Registers for function GPIO */ 2495#define PALMAS_GPIO_DATA_IN 0x0 2496#define PALMAS_GPIO_DATA_DIR 0x1 2497#define PALMAS_GPIO_DATA_OUT 0x2 2498#define PALMAS_GPIO_DEBOUNCE_EN 0x3 2499#define PALMAS_GPIO_CLEAR_DATA_OUT 0x4 2500#define PALMAS_GPIO_SET_DATA_OUT 0x5 2501#define PALMAS_PU_PD_GPIO_CTRL1 0x6 2502#define PALMAS_PU_PD_GPIO_CTRL2 0x7 2503#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x8 2504 2505/* Bit definitions for GPIO_DATA_IN */ 2506#define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80 2507#define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 7 2508#define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40 2509#define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 6 2510#define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20 2511#define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 5 2512#define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10 2513#define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 4 2514#define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08 2515#define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 3 2516#define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04 2517#define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 2 2518#define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02 2519#define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 1 2520#define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01 2521#define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0 2522 2523/* Bit definitions for GPIO_DATA_DIR */ 2524#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80 2525#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 7 2526#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40 2527#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 6 2528#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20 2529#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 5 2530#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10 2531#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 4 2532#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08 2533#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 3 2534#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04 2535#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 2 2536#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02 2537#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 1 2538#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01 2539#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0 2540 2541/* Bit definitions for GPIO_DATA_OUT */ 2542#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80 2543#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 7 2544#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40 2545#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 6 2546#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20 2547#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 5 2548#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10 2549#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 4 2550#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08 2551#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 3 2552#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04 2553#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 2 2554#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02 2555#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 1 2556#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01 2557#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0 2558 2559/* Bit definitions for GPIO_DEBOUNCE_EN */ 2560#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80 2561#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 7 2562#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40 2563#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 6 2564#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20 2565#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 5 2566#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10 2567#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 4 2568#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08 2569#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 3 2570#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04 2571#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 2 2572#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02 2573#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 1 2574#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01 2575#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0 2576 2577/* Bit definitions for GPIO_CLEAR_DATA_OUT */ 2578#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80 2579#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 7 2580#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40 2581#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 6 2582#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20 2583#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 5 2584#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10 2585#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 4 2586#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08 2587#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 3 2588#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04 2589#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 2 2590#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02 2591#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 1 2592#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01 2593#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0 2594 2595/* Bit definitions for GPIO_SET_DATA_OUT */ 2596#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80 2597#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 7 2598#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40 2599#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 6 2600#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20 2601#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 5 2602#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10 2603#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 4 2604#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08 2605#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 3 2606#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04 2607#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 2 2608#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02 2609#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 1 2610#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01 2611#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0 2612 2613/* Bit definitions for PU_PD_GPIO_CTRL1 */ 2614#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40 2615#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 6 2616#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20 2617#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 5 2618#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10 2619#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 4 2620#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08 2621#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 3 2622#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04 2623#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 2 2624#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01 2625#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0 2626 2627/* Bit definitions for PU_PD_GPIO_CTRL2 */ 2628#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40 2629#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 6 2630#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20 2631#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 5 2632#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10 2633#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 4 2634#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08 2635#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 3 2636#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04 2637#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 2 2638#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02 2639#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 1 2640#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01 2641#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0 2642 2643/* Bit definitions for OD_OUTPUT_GPIO_CTRL */ 2644#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20 2645#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 5 2646#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04 2647#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 2 2648#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02 2649#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 1 2650 2651/* Registers for function GPADC */ 2652#define PALMAS_GPADC_CTRL1 0x0 2653#define PALMAS_GPADC_CTRL2 0x1 2654#define PALMAS_GPADC_RT_CTRL 0x2 2655#define PALMAS_GPADC_AUTO_CTRL 0x3 2656#define PALMAS_GPADC_STATUS 0x4 2657#define PALMAS_GPADC_RT_SELECT 0x5 2658#define PALMAS_GPADC_RT_CONV0_LSB 0x6 2659#define PALMAS_GPADC_RT_CONV0_MSB 0x7 2660#define PALMAS_GPADC_AUTO_SELECT 0x8 2661#define PALMAS_GPADC_AUTO_CONV0_LSB 0x9 2662#define PALMAS_GPADC_AUTO_CONV0_MSB 0xA 2663#define PALMAS_GPADC_AUTO_CONV1_LSB 0xB 2664#define PALMAS_GPADC_AUTO_CONV1_MSB 0xC 2665#define PALMAS_GPADC_SW_SELECT 0xD 2666#define PALMAS_GPADC_SW_CONV0_LSB 0xE 2667#define PALMAS_GPADC_SW_CONV0_MSB 0xF 2668#define PALMAS_GPADC_THRES_CONV0_LSB 0x10 2669#define PALMAS_GPADC_THRES_CONV0_MSB 0x11 2670#define PALMAS_GPADC_THRES_CONV1_LSB 0x12 2671#define PALMAS_GPADC_THRES_CONV1_MSB 0x13 2672#define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14 2673#define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15 2674 2675/* Bit definitions for GPADC_CTRL1 */ 2676#define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0 2677#define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 6 2678#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30 2679#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 4 2680#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c 2681#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 2 2682#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02 2683#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 1 2684#define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01 2685#define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0 2686 2687/* Bit definitions for GPADC_CTRL2 */ 2688#define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06 2689#define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 1 2690 2691/* Bit definitions for GPADC_RT_CTRL */ 2692#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02 2693#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 1 2694#define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01 2695#define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0 2696 2697/* Bit definitions for GPADC_AUTO_CTRL */ 2698#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80 2699#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 7 2700#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40 2701#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 6 2702#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20 2703#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 5 2704#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10 2705#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 4 2706#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0f 2707#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0 2708 2709/* Bit definitions for GPADC_STATUS */ 2710#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10 2711#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 4 2712 2713/* Bit definitions for GPADC_RT_SELECT */ 2714#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80 2715#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 7 2716#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0f 2717#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0 2718 2719/* Bit definitions for GPADC_RT_CONV0_LSB */ 2720#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xff 2721#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0 2722 2723/* Bit definitions for GPADC_RT_CONV0_MSB */ 2724#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0f 2725#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0 2726 2727/* Bit definitions for GPADC_AUTO_SELECT */ 2728#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xf0 2729#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 4 2730#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0f 2731#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0 2732 2733/* Bit definitions for GPADC_AUTO_CONV0_LSB */ 2734#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xff 2735#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0 2736 2737/* Bit definitions for GPADC_AUTO_CONV0_MSB */ 2738#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0f 2739#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0 2740 2741/* Bit definitions for GPADC_AUTO_CONV1_LSB */ 2742#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xff 2743#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0 2744 2745/* Bit definitions for GPADC_AUTO_CONV1_MSB */ 2746#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0f 2747#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0 2748 2749/* Bit definitions for GPADC_SW_SELECT */ 2750#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80 2751#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 7 2752#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10 2753#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 4 2754#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0f 2755#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0 2756 2757/* Bit definitions for GPADC_SW_CONV0_LSB */ 2758#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xff 2759#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0 2760 2761/* Bit definitions for GPADC_SW_CONV0_MSB */ 2762#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0f 2763#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0 2764 2765/* Bit definitions for GPADC_THRES_CONV0_LSB */ 2766#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xff 2767#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0 2768 2769/* Bit definitions for GPADC_THRES_CONV0_MSB */ 2770#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80 2771#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 7 2772#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0f 2773#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0 2774 2775/* Bit definitions for GPADC_THRES_CONV1_LSB */ 2776#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xff 2777#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0 2778 2779/* Bit definitions for GPADC_THRES_CONV1_MSB */ 2780#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80 2781#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 7 2782#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0f 2783#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0 2784 2785/* Bit definitions for GPADC_SMPS_ILMONITOR_EN */ 2786#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20 2787#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 5 2788#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10 2789#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 4 2790#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0f 2791#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0 2792 2793/* Bit definitions for GPADC_SMPS_VSEL_MONITORING */ 2794#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80 2795#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 7 2796#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7f 2797#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0 2798 2799/* Registers for function GPADC */ 2800#define PALMAS_GPADC_TRIM1 0x0 2801#define PALMAS_GPADC_TRIM2 0x1 2802#define PALMAS_GPADC_TRIM3 0x2 2803#define PALMAS_GPADC_TRIM4 0x3 2804#define PALMAS_GPADC_TRIM5 0x4 2805#define PALMAS_GPADC_TRIM6 0x5 2806#define PALMAS_GPADC_TRIM7 0x6 2807#define PALMAS_GPADC_TRIM8 0x7 2808#define PALMAS_GPADC_TRIM9 0x8 2809#define PALMAS_GPADC_TRIM10 0x9 2810#define PALMAS_GPADC_TRIM11 0xA 2811#define PALMAS_GPADC_TRIM12 0xB 2812#define PALMAS_GPADC_TRIM13 0xC 2813#define PALMAS_GPADC_TRIM14 0xD 2814#define PALMAS_GPADC_TRIM15 0xE 2815#define PALMAS_GPADC_TRIM16 0xF 2816 2817static inline int palmas_read(struct palmas *palmas, unsigned int base, 2818 unsigned int reg, unsigned int *val) 2819{ 2820 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 2821 int slave_id = PALMAS_BASE_TO_SLAVE(base); 2822 2823 return regmap_read(palmas->regmap[slave_id], addr, val); 2824} 2825 2826static inline int palmas_write(struct palmas *palmas, unsigned int base, 2827 unsigned int reg, unsigned int value) 2828{ 2829 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 2830 int slave_id = PALMAS_BASE_TO_SLAVE(base); 2831 2832 return regmap_write(palmas->regmap[slave_id], addr, value); 2833} 2834 2835static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base, 2836 unsigned int reg, const void *val, size_t val_count) 2837{ 2838 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 2839 int slave_id = PALMAS_BASE_TO_SLAVE(base); 2840 2841 return regmap_bulk_write(palmas->regmap[slave_id], addr, 2842 val, val_count); 2843} 2844 2845static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base, 2846 unsigned int reg, void *val, size_t val_count) 2847{ 2848 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 2849 int slave_id = PALMAS_BASE_TO_SLAVE(base); 2850 2851 return regmap_bulk_read(palmas->regmap[slave_id], addr, 2852 val, val_count); 2853} 2854 2855static inline int palmas_update_bits(struct palmas *palmas, unsigned int base, 2856 unsigned int reg, unsigned int mask, unsigned int val) 2857{ 2858 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 2859 int slave_id = PALMAS_BASE_TO_SLAVE(base); 2860 2861 return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val); 2862} 2863 2864static inline int palmas_irq_get_virq(struct palmas *palmas, int irq) 2865{ 2866 return regmap_irq_get_virq(palmas->irq_data, irq); 2867} 2868 2869#endif /* __LINUX_MFD_PALMAS_H */