tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom
kernel / include / linux / mfd / palmas.h
at v3.10 2853 lines 113 kB view raw
1/* 2 * TI Palmas 3 * 4 * Copyright 2011-2013 Texas Instruments Inc. 5 * 6 * Author: Graeme Gregory <gg@slimlogic.co.uk> 7 * Author: Ian Lartey <ian@slimlogic.co.uk> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 */ 15 16#ifndef __LINUX_MFD_PALMAS_H 17#define __LINUX_MFD_PALMAS_H 18 19#include <linux/usb/otg.h> 20#include <linux/leds.h> 21#include <linux/regmap.h> 22#include <linux/regulator/driver.h> 23 24#define PALMAS_NUM_CLIENTS 3 25 26/* The ID_REVISION NUMBERS */ 27#define PALMAS_CHIP_OLD_ID 0x0000 28#define PALMAS_CHIP_ID 0xC035 29#define PALMAS_CHIP_CHARGER_ID 0xC036 30 31#define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \ 32 ((a) == PALMAS_CHIP_ID)) 33#define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID) 34 35struct palmas_pmic; 36struct palmas_gpadc; 37struct palmas_resource; 38struct palmas_usb; 39 40struct palmas { 41 struct device *dev; 42 43 struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS]; 44 struct regmap *regmap[PALMAS_NUM_CLIENTS]; 45 46 /* Stored chip id */ 47 int id; 48 49 /* IRQ Data */ 50 int irq; 51 u32 irq_mask; 52 struct mutex irq_lock; 53 struct regmap_irq_chip_data *irq_data; 54 55 /* Child Devices */ 56 struct palmas_pmic *pmic; 57 struct palmas_gpadc *gpadc; 58 struct palmas_resource *resource; 59 struct palmas_usb *usb; 60 61 /* GPIO MUXing */ 62 u8 gpio_muxed; 63 u8 led_muxed; 64 u8 pwm_muxed; 65}; 66 67struct palmas_gpadc_platform_data { 68 /* Channel 3 current source is only enabled during conversion */ 69 int ch3_current; 70 71 /* Channel 0 current source can be used for battery detection. 72 * If used for battery detection this will cause a permanent current 73 * consumption depending on current level set here. 74 */ 75 int ch0_current; 76 77 /* default BAT_REMOVAL_DAT setting on device probe */ 78 int bat_removal; 79 80 /* Sets the START_POLARITY bit in the RT_CTRL register */ 81 int start_polarity; 82}; 83 84struct palmas_reg_init { 85 /* warm_rest controls the voltage levels after a warm reset 86 * 87 * 0: reload default values from OTP on warm reset 88 * 1: maintain voltage from VSEL on warm reset 89 */ 90 int warm_reset; 91 92 /* roof_floor controls whether the regulator uses the i2c style 93 * of DVS or uses the method where a GPIO or other control method is 94 * attached to the NSLEEP/ENABLE1/ENABLE2 pins 95 * 96 * For SMPS 97 * 98 * 0: i2c selection of voltage 99 * 1: pin selection of voltage. 100 * 101 * For LDO unused 102 */ 103 int roof_floor; 104 105 /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in 106 * the data sheet. 107 * 108 * For SMPS 109 * 110 * 0: Off 111 * 1: AUTO 112 * 2: ECO 113 * 3: Forced PWM 114 * 115 * For LDO 116 * 117 * 0: Off 118 * 1: On 119 */ 120 int mode_sleep; 121 122 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE 123 * register. Set this is the default voltage set in OTP needs 124 * to be overridden. 125 */ 126 u8 vsel; 127 128}; 129 130enum palmas_regulators { 131 /* SMPS regulators */ 132 PALMAS_REG_SMPS12, 133 PALMAS_REG_SMPS123, 134 PALMAS_REG_SMPS3, 135 PALMAS_REG_SMPS45, 136 PALMAS_REG_SMPS457, 137 PALMAS_REG_SMPS6, 138 PALMAS_REG_SMPS7, 139 PALMAS_REG_SMPS8, 140 PALMAS_REG_SMPS9, 141 PALMAS_REG_SMPS10, 142 /* LDO regulators */ 143 PALMAS_REG_LDO1, 144 PALMAS_REG_LDO2, 145 PALMAS_REG_LDO3, 146 PALMAS_REG_LDO4, 147 PALMAS_REG_LDO5, 148 PALMAS_REG_LDO6, 149 PALMAS_REG_LDO7, 150 PALMAS_REG_LDO8, 151 PALMAS_REG_LDO9, 152 PALMAS_REG_LDOLN, 153 PALMAS_REG_LDOUSB, 154 /* External regulators */ 155 PALMAS_REG_REGEN1, 156 PALMAS_REG_REGEN2, 157 PALMAS_REG_REGEN3, 158 PALMAS_REG_SYSEN1, 159 PALMAS_REG_SYSEN2, 160 /* Total number of regulators */ 161 PALMAS_NUM_REGS, 162}; 163 164struct palmas_pmic_platform_data { 165 /* An array of pointers to regulator init data indexed by regulator 166 * ID 167 */ 168 struct regulator_init_data *reg_data[PALMAS_NUM_REGS]; 169 170 /* An array of pointers to structures containing sleep mode and DVS 171 * configuration for regulators indexed by ID 172 */ 173 struct palmas_reg_init *reg_init[PALMAS_NUM_REGS]; 174 175 /* use LDO6 for vibrator control */ 176 int ldo6_vibrator; 177 178 /* Enable tracking mode of LDO8 */ 179 bool enable_ldo8_tracking; 180}; 181 182struct palmas_usb_platform_data { 183 /* Set this if platform wishes its own vbus control */ 184 int no_control_vbus; 185 186 /* Do we enable the wakeup comparator on probe */ 187 int wakeup; 188}; 189 190struct palmas_resource_platform_data { 191 int regen1_mode_sleep; 192 int regen2_mode_sleep; 193 int sysen1_mode_sleep; 194 int sysen2_mode_sleep; 195 196 /* bitfield to be loaded to NSLEEP_RES_ASSIGN */ 197 u8 nsleep_res; 198 /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */ 199 u8 nsleep_smps; 200 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */ 201 u8 nsleep_ldo1; 202 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */ 203 u8 nsleep_ldo2; 204 205 /* bitfield to be loaded to ENABLE1_RES_ASSIGN */ 206 u8 enable1_res; 207 /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */ 208 u8 enable1_smps; 209 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */ 210 u8 enable1_ldo1; 211 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */ 212 u8 enable1_ldo2; 213 214 /* bitfield to be loaded to ENABLE2_RES_ASSIGN */ 215 u8 enable2_res; 216 /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */ 217 u8 enable2_smps; 218 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */ 219 u8 enable2_ldo1; 220 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */ 221 u8 enable2_ldo2; 222}; 223 224struct palmas_clk_platform_data { 225 int clk32kg_mode_sleep; 226 int clk32kgaudio_mode_sleep; 227}; 228 229struct palmas_platform_data { 230 int irq_flags; 231 int gpio_base; 232 233 /* bit value to be loaded to the POWER_CTRL register */ 234 u8 power_ctrl; 235 236 /* 237 * boolean to select if we want to configure muxing here 238 * then the two value to load into the registers if true 239 */ 240 int mux_from_pdata; 241 u8 pad1, pad2; 242 243 struct palmas_pmic_platform_data *pmic_pdata; 244 struct palmas_gpadc_platform_data *gpadc_pdata; 245 struct palmas_usb_platform_data *usb_pdata; 246 struct palmas_resource_platform_data *resource_pdata; 247 struct palmas_clk_platform_data *clk_pdata; 248}; 249 250struct palmas_gpadc_calibration { 251 s32 gain; 252 s32 gain_error; 253 s32 offset_error; 254}; 255 256struct palmas_gpadc { 257 struct device *dev; 258 struct palmas *palmas; 259 260 int ch3_current; 261 int ch0_current; 262 263 int gpadc_force; 264 265 int bat_removal; 266 267 struct mutex reading_lock; 268 struct completion irq_complete; 269 270 int eoc_sw_irq; 271 272 struct palmas_gpadc_calibration *palmas_cal_tbl; 273 274 int conv0_channel; 275 int conv1_channel; 276 int rt_channel; 277}; 278 279struct palmas_gpadc_result { 280 s32 raw_code; 281 s32 corrected_code; 282 s32 result; 283}; 284 285#define PALMAS_MAX_CHANNELS 16 286 287/* Define the palmas IRQ numbers */ 288enum palmas_irqs { 289 /* INT1 registers */ 290 PALMAS_CHARG_DET_N_VBUS_OVV_IRQ, 291 PALMAS_PWRON_IRQ, 292 PALMAS_LONG_PRESS_KEY_IRQ, 293 PALMAS_RPWRON_IRQ, 294 PALMAS_PWRDOWN_IRQ, 295 PALMAS_HOTDIE_IRQ, 296 PALMAS_VSYS_MON_IRQ, 297 PALMAS_VBAT_MON_IRQ, 298 /* INT2 registers */ 299 PALMAS_RTC_ALARM_IRQ, 300 PALMAS_RTC_TIMER_IRQ, 301 PALMAS_WDT_IRQ, 302 PALMAS_BATREMOVAL_IRQ, 303 PALMAS_RESET_IN_IRQ, 304 PALMAS_FBI_BB_IRQ, 305 PALMAS_SHORT_IRQ, 306 PALMAS_VAC_ACOK_IRQ, 307 /* INT3 registers */ 308 PALMAS_GPADC_AUTO_0_IRQ, 309 PALMAS_GPADC_AUTO_1_IRQ, 310 PALMAS_GPADC_EOC_SW_IRQ, 311 PALMAS_GPADC_EOC_RT_IRQ, 312 PALMAS_ID_OTG_IRQ, 313 PALMAS_ID_IRQ, 314 PALMAS_VBUS_OTG_IRQ, 315 PALMAS_VBUS_IRQ, 316 /* INT4 registers */ 317 PALMAS_GPIO_0_IRQ, 318 PALMAS_GPIO_1_IRQ, 319 PALMAS_GPIO_2_IRQ, 320 PALMAS_GPIO_3_IRQ, 321 PALMAS_GPIO_4_IRQ, 322 PALMAS_GPIO_5_IRQ, 323 PALMAS_GPIO_6_IRQ, 324 PALMAS_GPIO_7_IRQ, 325 /* Total Number IRQs */ 326 PALMAS_NUM_IRQ, 327}; 328 329struct palmas_pmic { 330 struct palmas *palmas; 331 struct device *dev; 332 struct regulator_desc desc[PALMAS_NUM_REGS]; 333 struct regulator_dev *rdev[PALMAS_NUM_REGS]; 334 struct mutex mutex; 335 336 int smps123; 337 int smps457; 338 339 int range[PALMAS_REG_SMPS10]; 340 unsigned int ramp_delay[PALMAS_REG_SMPS10]; 341 unsigned int current_reg_mode[PALMAS_REG_SMPS10]; 342}; 343 344struct palmas_resource { 345 struct palmas *palmas; 346 struct device *dev; 347}; 348 349struct palmas_usb { 350 struct palmas *palmas; 351 struct device *dev; 352 353 /* for vbus reporting with irqs disabled */ 354 spinlock_t lock; 355 356 struct regulator *vbus_reg; 357 358 /* used to set vbus, in atomic path */ 359 struct work_struct set_vbus_work; 360 361 int irq1; 362 int irq2; 363 int irq3; 364 int irq4; 365 366 int vbus_enable; 367 368 u8 linkstat; 369}; 370 371#define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator) 372 373enum usb_irq_events { 374 /* Wakeup events from INT3 */ 375 PALMAS_USB_ID_WAKEPUP, 376 PALMAS_USB_VBUS_WAKEUP, 377 378 /* ID_OTG_EVENTS */ 379 PALMAS_USB_ID_GND, 380 N_PALMAS_USB_ID_GND, 381 PALMAS_USB_ID_C, 382 N_PALMAS_USB_ID_C, 383 PALMAS_USB_ID_B, 384 N_PALMAS_USB_ID_B, 385 PALMAS_USB_ID_A, 386 N_PALMAS_USB_ID_A, 387 PALMAS_USB_ID_FLOAT, 388 N_PALMAS_USB_ID_FLOAT, 389 390 /* VBUS_OTG_EVENTS */ 391 PALMAS_USB_VB_SESS_END, 392 N_PALMAS_USB_VB_SESS_END, 393 PALMAS_USB_VB_SESS_VLD, 394 N_PALMAS_USB_VB_SESS_VLD, 395 PALMAS_USB_VA_SESS_VLD, 396 N_PALMAS_USB_VA_SESS_VLD, 397 PALMAS_USB_VA_VBUS_VLD, 398 N_PALMAS_USB_VA_VBUS_VLD, 399 PALMAS_USB_VADP_SNS, 400 N_PALMAS_USB_VADP_SNS, 401 PALMAS_USB_VADP_PRB, 402 N_PALMAS_USB_VADP_PRB, 403 PALMAS_USB_VOTG_SESS_VLD, 404 N_PALMAS_USB_VOTG_SESS_VLD, 405}; 406 407/* defines so we can store the mux settings */ 408#define PALMAS_GPIO_0_MUXED (1 << 0) 409#define PALMAS_GPIO_1_MUXED (1 << 1) 410#define PALMAS_GPIO_2_MUXED (1 << 2) 411#define PALMAS_GPIO_3_MUXED (1 << 3) 412#define PALMAS_GPIO_4_MUXED (1 << 4) 413#define PALMAS_GPIO_5_MUXED (1 << 5) 414#define PALMAS_GPIO_6_MUXED (1 << 6) 415#define PALMAS_GPIO_7_MUXED (1 << 7) 416 417#define PALMAS_LED1_MUXED (1 << 0) 418#define PALMAS_LED2_MUXED (1 << 1) 419 420#define PALMAS_PWM1_MUXED (1 << 0) 421#define PALMAS_PWM2_MUXED (1 << 1) 422 423/* helper macro to get correct slave number */ 424#define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1) 425#define PALMAS_BASE_TO_REG(x, y) ((x & 0xff) + y) 426 427/* Base addresses of IP blocks in Palmas */ 428#define PALMAS_SMPS_DVS_BASE 0x20 429#define PALMAS_RTC_BASE 0x100 430#define PALMAS_VALIDITY_BASE 0x118 431#define PALMAS_SMPS_BASE 0x120 432#define PALMAS_LDO_BASE 0x150 433#define PALMAS_DVFS_BASE 0x180 434#define PALMAS_PMU_CONTROL_BASE 0x1A0 435#define PALMAS_RESOURCE_BASE 0x1D4 436#define PALMAS_PU_PD_OD_BASE 0x1F4 437#define PALMAS_LED_BASE 0x200 438#define PALMAS_INTERRUPT_BASE 0x210 439#define PALMAS_USB_OTG_BASE 0x250 440#define PALMAS_VIBRATOR_BASE 0x270 441#define PALMAS_GPIO_BASE 0x280 442#define PALMAS_USB_BASE 0x290 443#define PALMAS_GPADC_BASE 0x2C0 444#define PALMAS_TRIM_GPADC_BASE 0x3CD 445 446/* Registers for function RTC */ 447#define PALMAS_SECONDS_REG 0x0 448#define PALMAS_MINUTES_REG 0x1 449#define PALMAS_HOURS_REG 0x2 450#define PALMAS_DAYS_REG 0x3 451#define PALMAS_MONTHS_REG 0x4 452#define PALMAS_YEARS_REG 0x5 453#define PALMAS_WEEKS_REG 0x6 454#define PALMAS_ALARM_SECONDS_REG 0x8 455#define PALMAS_ALARM_MINUTES_REG 0x9 456#define PALMAS_ALARM_HOURS_REG 0xA 457#define PALMAS_ALARM_DAYS_REG 0xB 458#define PALMAS_ALARM_MONTHS_REG 0xC 459#define PALMAS_ALARM_YEARS_REG 0xD 460#define PALMAS_RTC_CTRL_REG 0x10 461#define PALMAS_RTC_STATUS_REG 0x11 462#define PALMAS_RTC_INTERRUPTS_REG 0x12 463#define PALMAS_RTC_COMP_LSB_REG 0x13 464#define PALMAS_RTC_COMP_MSB_REG 0x14 465#define PALMAS_RTC_RES_PROG_REG 0x15 466#define PALMAS_RTC_RESET_STATUS_REG 0x16 467 468/* Bit definitions for SECONDS_REG */ 469#define PALMAS_SECONDS_REG_SEC1_MASK 0x70 470#define PALMAS_SECONDS_REG_SEC1_SHIFT 4 471#define PALMAS_SECONDS_REG_SEC0_MASK 0x0f 472#define PALMAS_SECONDS_REG_SEC0_SHIFT 0 473 474/* Bit definitions for MINUTES_REG */ 475#define PALMAS_MINUTES_REG_MIN1_MASK 0x70 476#define PALMAS_MINUTES_REG_MIN1_SHIFT 4 477#define PALMAS_MINUTES_REG_MIN0_MASK 0x0f 478#define PALMAS_MINUTES_REG_MIN0_SHIFT 0 479 480/* Bit definitions for HOURS_REG */ 481#define PALMAS_HOURS_REG_PM_NAM 0x80 482#define PALMAS_HOURS_REG_PM_NAM_SHIFT 7 483#define PALMAS_HOURS_REG_HOUR1_MASK 0x30 484#define PALMAS_HOURS_REG_HOUR1_SHIFT 4 485#define PALMAS_HOURS_REG_HOUR0_MASK 0x0f 486#define PALMAS_HOURS_REG_HOUR0_SHIFT 0 487 488/* Bit definitions for DAYS_REG */ 489#define PALMAS_DAYS_REG_DAY1_MASK 0x30 490#define PALMAS_DAYS_REG_DAY1_SHIFT 4 491#define PALMAS_DAYS_REG_DAY0_MASK 0x0f 492#define PALMAS_DAYS_REG_DAY0_SHIFT 0 493 494/* Bit definitions for MONTHS_REG */ 495#define PALMAS_MONTHS_REG_MONTH1 0x10 496#define PALMAS_MONTHS_REG_MONTH1_SHIFT 4 497#define PALMAS_MONTHS_REG_MONTH0_MASK 0x0f 498#define PALMAS_MONTHS_REG_MONTH0_SHIFT 0 499 500/* Bit definitions for YEARS_REG */ 501#define PALMAS_YEARS_REG_YEAR1_MASK 0xf0 502#define PALMAS_YEARS_REG_YEAR1_SHIFT 4 503#define PALMAS_YEARS_REG_YEAR0_MASK 0x0f 504#define PALMAS_YEARS_REG_YEAR0_SHIFT 0 505 506/* Bit definitions for WEEKS_REG */ 507#define PALMAS_WEEKS_REG_WEEK_MASK 0x07 508#define PALMAS_WEEKS_REG_WEEK_SHIFT 0 509 510/* Bit definitions for ALARM_SECONDS_REG */ 511#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70 512#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 4 513#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0f 514#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0 515 516/* Bit definitions for ALARM_MINUTES_REG */ 517#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70 518#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 4 519#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0f 520#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0 521 522/* Bit definitions for ALARM_HOURS_REG */ 523#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80 524#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 7 525#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30 526#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 4 527#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0f 528#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0 529 530/* Bit definitions for ALARM_DAYS_REG */ 531#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30 532#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 4 533#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0f 534#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0 535 536/* Bit definitions for ALARM_MONTHS_REG */ 537#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10 538#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 4 539#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0f 540#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0 541 542/* Bit definitions for ALARM_YEARS_REG */ 543#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0 544#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 4 545#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0f 546#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0 547 548/* Bit definitions for RTC_CTRL_REG */ 549#define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80 550#define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 7 551#define PALMAS_RTC_CTRL_REG_GET_TIME 0x40 552#define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 6 553#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20 554#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 5 555#define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10 556#define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 4 557#define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08 558#define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 3 559#define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04 560#define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 2 561#define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02 562#define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 1 563#define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01 564#define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0 565 566/* Bit definitions for RTC_STATUS_REG */ 567#define PALMAS_RTC_STATUS_REG_POWER_UP 0x80 568#define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 7 569#define PALMAS_RTC_STATUS_REG_ALARM 0x40 570#define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 6 571#define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20 572#define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 5 573#define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10 574#define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 4 575#define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08 576#define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 3 577#define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04 578#define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 2 579#define PALMAS_RTC_STATUS_REG_RUN 0x02 580#define PALMAS_RTC_STATUS_REG_RUN_SHIFT 1 581 582/* Bit definitions for RTC_INTERRUPTS_REG */ 583#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10 584#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 4 585#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08 586#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 3 587#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04 588#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 2 589#define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03 590#define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0 591 592/* Bit definitions for RTC_COMP_LSB_REG */ 593#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xff 594#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0 595 596/* Bit definitions for RTC_COMP_MSB_REG */ 597#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xff 598#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0 599 600/* Bit definitions for RTC_RES_PROG_REG */ 601#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3f 602#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0 603 604/* Bit definitions for RTC_RESET_STATUS_REG */ 605#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01 606#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0 607 608/* Registers for function BACKUP */ 609#define PALMAS_BACKUP0 0x0 610#define PALMAS_BACKUP1 0x1 611#define PALMAS_BACKUP2 0x2 612#define PALMAS_BACKUP3 0x3 613#define PALMAS_BACKUP4 0x4 614#define PALMAS_BACKUP5 0x5 615#define PALMAS_BACKUP6 0x6 616#define PALMAS_BACKUP7 0x7 617 618/* Bit definitions for BACKUP0 */ 619#define PALMAS_BACKUP0_BACKUP_MASK 0xff 620#define PALMAS_BACKUP0_BACKUP_SHIFT 0 621 622/* Bit definitions for BACKUP1 */ 623#define PALMAS_BACKUP1_BACKUP_MASK 0xff 624#define PALMAS_BACKUP1_BACKUP_SHIFT 0 625 626/* Bit definitions for BACKUP2 */ 627#define PALMAS_BACKUP2_BACKUP_MASK 0xff 628#define PALMAS_BACKUP2_BACKUP_SHIFT 0 629 630/* Bit definitions for BACKUP3 */ 631#define PALMAS_BACKUP3_BACKUP_MASK 0xff 632#define PALMAS_BACKUP3_BACKUP_SHIFT 0 633 634/* Bit definitions for BACKUP4 */ 635#define PALMAS_BACKUP4_BACKUP_MASK 0xff 636#define PALMAS_BACKUP4_BACKUP_SHIFT 0 637 638/* Bit definitions for BACKUP5 */ 639#define PALMAS_BACKUP5_BACKUP_MASK 0xff 640#define PALMAS_BACKUP5_BACKUP_SHIFT 0 641 642/* Bit definitions for BACKUP6 */ 643#define PALMAS_BACKUP6_BACKUP_MASK 0xff 644#define PALMAS_BACKUP6_BACKUP_SHIFT 0 645 646/* Bit definitions for BACKUP7 */ 647#define PALMAS_BACKUP7_BACKUP_MASK 0xff 648#define PALMAS_BACKUP7_BACKUP_SHIFT 0 649 650/* Registers for function SMPS */ 651#define PALMAS_SMPS12_CTRL 0x0 652#define PALMAS_SMPS12_TSTEP 0x1 653#define PALMAS_SMPS12_FORCE 0x2 654#define PALMAS_SMPS12_VOLTAGE 0x3 655#define PALMAS_SMPS3_CTRL 0x4 656#define PALMAS_SMPS3_VOLTAGE 0x7 657#define PALMAS_SMPS45_CTRL 0x8 658#define PALMAS_SMPS45_TSTEP 0x9 659#define PALMAS_SMPS45_FORCE 0xA 660#define PALMAS_SMPS45_VOLTAGE 0xB 661#define PALMAS_SMPS6_CTRL 0xC 662#define PALMAS_SMPS6_TSTEP 0xD 663#define PALMAS_SMPS6_FORCE 0xE 664#define PALMAS_SMPS6_VOLTAGE 0xF 665#define PALMAS_SMPS7_CTRL 0x10 666#define PALMAS_SMPS7_VOLTAGE 0x13 667#define PALMAS_SMPS8_CTRL 0x14 668#define PALMAS_SMPS8_TSTEP 0x15 669#define PALMAS_SMPS8_FORCE 0x16 670#define PALMAS_SMPS8_VOLTAGE 0x17 671#define PALMAS_SMPS9_CTRL 0x18 672#define PALMAS_SMPS9_VOLTAGE 0x1B 673#define PALMAS_SMPS10_CTRL 0x1C 674#define PALMAS_SMPS10_STATUS 0x1F 675#define PALMAS_SMPS_CTRL 0x24 676#define PALMAS_SMPS_PD_CTRL 0x25 677#define PALMAS_SMPS_DITHER_EN 0x26 678#define PALMAS_SMPS_THERMAL_EN 0x27 679#define PALMAS_SMPS_THERMAL_STATUS 0x28 680#define PALMAS_SMPS_SHORT_STATUS 0x29 681#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A 682#define PALMAS_SMPS_POWERGOOD_MASK1 0x2B 683#define PALMAS_SMPS_POWERGOOD_MASK2 0x2C 684 685/* Bit definitions for SMPS12_CTRL */ 686#define PALMAS_SMPS12_CTRL_WR_S 0x80 687#define PALMAS_SMPS12_CTRL_WR_S_SHIFT 7 688#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40 689#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 6 690#define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30 691#define PALMAS_SMPS12_CTRL_STATUS_SHIFT 4 692#define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c 693#define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 2 694#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03 695#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0 696 697/* Bit definitions for SMPS12_TSTEP */ 698#define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03 699#define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0 700 701/* Bit definitions for SMPS12_FORCE */ 702#define PALMAS_SMPS12_FORCE_CMD 0x80 703#define PALMAS_SMPS12_FORCE_CMD_SHIFT 7 704#define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7f 705#define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0 706 707/* Bit definitions for SMPS12_VOLTAGE */ 708#define PALMAS_SMPS12_VOLTAGE_RANGE 0x80 709#define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 7 710#define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7f 711#define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0 712 713/* Bit definitions for SMPS3_CTRL */ 714#define PALMAS_SMPS3_CTRL_WR_S 0x80 715#define PALMAS_SMPS3_CTRL_WR_S_SHIFT 7 716#define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30 717#define PALMAS_SMPS3_CTRL_STATUS_SHIFT 4 718#define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c 719#define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 2 720#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03 721#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0 722 723/* Bit definitions for SMPS3_VOLTAGE */ 724#define PALMAS_SMPS3_VOLTAGE_RANGE 0x80 725#define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 7 726#define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7f 727#define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0 728 729/* Bit definitions for SMPS45_CTRL */ 730#define PALMAS_SMPS45_CTRL_WR_S 0x80 731#define PALMAS_SMPS45_CTRL_WR_S_SHIFT 7 732#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40 733#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 6 734#define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30 735#define PALMAS_SMPS45_CTRL_STATUS_SHIFT 4 736#define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c 737#define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 2 738#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03 739#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0 740 741/* Bit definitions for SMPS45_TSTEP */ 742#define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03 743#define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0 744 745/* Bit definitions for SMPS45_FORCE */ 746#define PALMAS_SMPS45_FORCE_CMD 0x80 747#define PALMAS_SMPS45_FORCE_CMD_SHIFT 7 748#define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7f 749#define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0 750 751/* Bit definitions for SMPS45_VOLTAGE */ 752#define PALMAS_SMPS45_VOLTAGE_RANGE 0x80 753#define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 7 754#define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7f 755#define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0 756 757/* Bit definitions for SMPS6_CTRL */ 758#define PALMAS_SMPS6_CTRL_WR_S 0x80 759#define PALMAS_SMPS6_CTRL_WR_S_SHIFT 7 760#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40 761#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 6 762#define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30 763#define PALMAS_SMPS6_CTRL_STATUS_SHIFT 4 764#define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c 765#define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 2 766#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03 767#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0 768 769/* Bit definitions for SMPS6_TSTEP */ 770#define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03 771#define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0 772 773/* Bit definitions for SMPS6_FORCE */ 774#define PALMAS_SMPS6_FORCE_CMD 0x80 775#define PALMAS_SMPS6_FORCE_CMD_SHIFT 7 776#define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7f 777#define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0 778 779/* Bit definitions for SMPS6_VOLTAGE */ 780#define PALMAS_SMPS6_VOLTAGE_RANGE 0x80 781#define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 7 782#define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7f 783#define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0 784 785/* Bit definitions for SMPS7_CTRL */ 786#define PALMAS_SMPS7_CTRL_WR_S 0x80 787#define PALMAS_SMPS7_CTRL_WR_S_SHIFT 7 788#define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30 789#define PALMAS_SMPS7_CTRL_STATUS_SHIFT 4 790#define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c 791#define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 2 792#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03 793#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0 794 795/* Bit definitions for SMPS7_VOLTAGE */ 796#define PALMAS_SMPS7_VOLTAGE_RANGE 0x80 797#define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 7 798#define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7f 799#define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0 800 801/* Bit definitions for SMPS8_CTRL */ 802#define PALMAS_SMPS8_CTRL_WR_S 0x80 803#define PALMAS_SMPS8_CTRL_WR_S_SHIFT 7 804#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40 805#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 6 806#define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30 807#define PALMAS_SMPS8_CTRL_STATUS_SHIFT 4 808#define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c 809#define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 2 810#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03 811#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0 812 813/* Bit definitions for SMPS8_TSTEP */ 814#define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03 815#define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0 816 817/* Bit definitions for SMPS8_FORCE */ 818#define PALMAS_SMPS8_FORCE_CMD 0x80 819#define PALMAS_SMPS8_FORCE_CMD_SHIFT 7 820#define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7f 821#define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0 822 823/* Bit definitions for SMPS8_VOLTAGE */ 824#define PALMAS_SMPS8_VOLTAGE_RANGE 0x80 825#define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 7 826#define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7f 827#define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0 828 829/* Bit definitions for SMPS9_CTRL */ 830#define PALMAS_SMPS9_CTRL_WR_S 0x80 831#define PALMAS_SMPS9_CTRL_WR_S_SHIFT 7 832#define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30 833#define PALMAS_SMPS9_CTRL_STATUS_SHIFT 4 834#define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c 835#define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 2 836#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03 837#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0 838 839/* Bit definitions for SMPS9_VOLTAGE */ 840#define PALMAS_SMPS9_VOLTAGE_RANGE 0x80 841#define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 7 842#define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7f 843#define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0 844 845/* Bit definitions for SMPS10_CTRL */ 846#define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0 847#define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 4 848#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0f 849#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0 850 851/* Bit definitions for SMPS10_STATUS */ 852#define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0f 853#define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0 854 855/* Bit definitions for SMPS_CTRL */ 856#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20 857#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 5 858#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10 859#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 4 860#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c 861#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 2 862#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03 863#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0 864 865/* Bit definitions for SMPS_PD_CTRL */ 866#define PALMAS_SMPS_PD_CTRL_SMPS9 0x40 867#define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 6 868#define PALMAS_SMPS_PD_CTRL_SMPS8 0x20 869#define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 5 870#define PALMAS_SMPS_PD_CTRL_SMPS7 0x10 871#define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 4 872#define PALMAS_SMPS_PD_CTRL_SMPS6 0x08 873#define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 3 874#define PALMAS_SMPS_PD_CTRL_SMPS45 0x04 875#define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 2 876#define PALMAS_SMPS_PD_CTRL_SMPS3 0x02 877#define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 1 878#define PALMAS_SMPS_PD_CTRL_SMPS12 0x01 879#define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0 880 881/* Bit definitions for SMPS_THERMAL_EN */ 882#define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40 883#define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 6 884#define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20 885#define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 5 886#define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08 887#define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 3 888#define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04 889#define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 2 890#define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01 891#define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0 892 893/* Bit definitions for SMPS_THERMAL_STATUS */ 894#define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40 895#define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 6 896#define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20 897#define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 5 898#define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08 899#define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 3 900#define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04 901#define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 2 902#define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01 903#define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0 904 905/* Bit definitions for SMPS_SHORT_STATUS */ 906#define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80 907#define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 7 908#define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40 909#define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 6 910#define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20 911#define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 5 912#define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10 913#define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 4 914#define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08 915#define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 3 916#define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04 917#define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 2 918#define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02 919#define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 1 920#define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01 921#define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0 922 923/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ 924#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40 925#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 6 926#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20 927#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 5 928#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10 929#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 4 930#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08 931#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 3 932#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04 933#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 2 934#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02 935#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 1 936#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01 937#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0 938 939/* Bit definitions for SMPS_POWERGOOD_MASK1 */ 940#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80 941#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 7 942#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40 943#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 6 944#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20 945#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 5 946#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10 947#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 4 948#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08 949#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 3 950#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04 951#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 2 952#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02 953#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 1 954#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01 955#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0 956 957/* Bit definitions for SMPS_POWERGOOD_MASK2 */ 958#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80 959#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7 960#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04 961#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 2 962#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02 963#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 1 964#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01 965#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0 966 967/* Registers for function LDO */ 968#define PALMAS_LDO1_CTRL 0x0 969#define PALMAS_LDO1_VOLTAGE 0x1 970#define PALMAS_LDO2_CTRL 0x2 971#define PALMAS_LDO2_VOLTAGE 0x3 972#define PALMAS_LDO3_CTRL 0x4 973#define PALMAS_LDO3_VOLTAGE 0x5 974#define PALMAS_LDO4_CTRL 0x6 975#define PALMAS_LDO4_VOLTAGE 0x7 976#define PALMAS_LDO5_CTRL 0x8 977#define PALMAS_LDO5_VOLTAGE 0x9 978#define PALMAS_LDO6_CTRL 0xA 979#define PALMAS_LDO6_VOLTAGE 0xB 980#define PALMAS_LDO7_CTRL 0xC 981#define PALMAS_LDO7_VOLTAGE 0xD 982#define PALMAS_LDO8_CTRL 0xE 983#define PALMAS_LDO8_VOLTAGE 0xF 984#define PALMAS_LDO9_CTRL 0x10 985#define PALMAS_LDO9_VOLTAGE 0x11 986#define PALMAS_LDOLN_CTRL 0x12 987#define PALMAS_LDOLN_VOLTAGE 0x13 988#define PALMAS_LDOUSB_CTRL 0x14 989#define PALMAS_LDOUSB_VOLTAGE 0x15 990#define PALMAS_LDO_CTRL 0x1A 991#define PALMAS_LDO_PD_CTRL1 0x1B 992#define PALMAS_LDO_PD_CTRL2 0x1C 993#define PALMAS_LDO_SHORT_STATUS1 0x1D 994#define PALMAS_LDO_SHORT_STATUS2 0x1E 995 996/* Bit definitions for LDO1_CTRL */ 997#define PALMAS_LDO1_CTRL_WR_S 0x80 998#define PALMAS_LDO1_CTRL_WR_S_SHIFT 7 999#define PALMAS_LDO1_CTRL_STATUS 0x10 1000#define PALMAS_LDO1_CTRL_STATUS_SHIFT 4 1001#define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04 1002#define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 2 1003#define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01 1004#define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0 1005 1006/* Bit definitions for LDO1_VOLTAGE */ 1007#define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3f 1008#define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0 1009 1010/* Bit definitions for LDO2_CTRL */ 1011#define PALMAS_LDO2_CTRL_WR_S 0x80 1012#define PALMAS_LDO2_CTRL_WR_S_SHIFT 7 1013#define PALMAS_LDO2_CTRL_STATUS 0x10 1014#define PALMAS_LDO2_CTRL_STATUS_SHIFT 4 1015#define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04 1016#define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 2 1017#define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01 1018#define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0 1019 1020/* Bit definitions for LDO2_VOLTAGE */ 1021#define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3f 1022#define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0 1023 1024/* Bit definitions for LDO3_CTRL */ 1025#define PALMAS_LDO3_CTRL_WR_S 0x80 1026#define PALMAS_LDO3_CTRL_WR_S_SHIFT 7 1027#define PALMAS_LDO3_CTRL_STATUS 0x10 1028#define PALMAS_LDO3_CTRL_STATUS_SHIFT 4 1029#define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04 1030#define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 2 1031#define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01 1032#define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0 1033 1034/* Bit definitions for LDO3_VOLTAGE */ 1035#define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3f 1036#define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0 1037 1038/* Bit definitions for LDO4_CTRL */ 1039#define PALMAS_LDO4_CTRL_WR_S 0x80 1040#define PALMAS_LDO4_CTRL_WR_S_SHIFT 7 1041#define PALMAS_LDO4_CTRL_STATUS 0x10 1042#define PALMAS_LDO4_CTRL_STATUS_SHIFT 4 1043#define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04 1044#define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 2 1045#define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01 1046#define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0 1047 1048/* Bit definitions for LDO4_VOLTAGE */ 1049#define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3f 1050#define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0 1051 1052/* Bit definitions for LDO5_CTRL */ 1053#define PALMAS_LDO5_CTRL_WR_S 0x80 1054#define PALMAS_LDO5_CTRL_WR_S_SHIFT 7 1055#define PALMAS_LDO5_CTRL_STATUS 0x10 1056#define PALMAS_LDO5_CTRL_STATUS_SHIFT 4 1057#define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04 1058#define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 2 1059#define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01 1060#define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0 1061 1062/* Bit definitions for LDO5_VOLTAGE */ 1063#define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3f 1064#define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0 1065 1066/* Bit definitions for LDO6_CTRL */ 1067#define PALMAS_LDO6_CTRL_WR_S 0x80 1068#define PALMAS_LDO6_CTRL_WR_S_SHIFT 7 1069#define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40 1070#define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 6 1071#define PALMAS_LDO6_CTRL_STATUS 0x10 1072#define PALMAS_LDO6_CTRL_STATUS_SHIFT 4 1073#define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04 1074#define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 2 1075#define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01 1076#define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0 1077 1078/* Bit definitions for LDO6_VOLTAGE */ 1079#define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3f 1080#define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0 1081 1082/* Bit definitions for LDO7_CTRL */ 1083#define PALMAS_LDO7_CTRL_WR_S 0x80 1084#define PALMAS_LDO7_CTRL_WR_S_SHIFT 7 1085#define PALMAS_LDO7_CTRL_STATUS 0x10 1086#define PALMAS_LDO7_CTRL_STATUS_SHIFT 4 1087#define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04 1088#define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 2 1089#define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01 1090#define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0 1091 1092/* Bit definitions for LDO7_VOLTAGE */ 1093#define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3f 1094#define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0 1095 1096/* Bit definitions for LDO8_CTRL */ 1097#define PALMAS_LDO8_CTRL_WR_S 0x80 1098#define PALMAS_LDO8_CTRL_WR_S_SHIFT 7 1099#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40 1100#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 6 1101#define PALMAS_LDO8_CTRL_STATUS 0x10 1102#define PALMAS_LDO8_CTRL_STATUS_SHIFT 4 1103#define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04 1104#define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 2 1105#define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01 1106#define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0 1107 1108/* Bit definitions for LDO8_VOLTAGE */ 1109#define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3f 1110#define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0 1111 1112/* Bit definitions for LDO9_CTRL */ 1113#define PALMAS_LDO9_CTRL_WR_S 0x80 1114#define PALMAS_LDO9_CTRL_WR_S_SHIFT 7 1115#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40 1116#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 6 1117#define PALMAS_LDO9_CTRL_STATUS 0x10 1118#define PALMAS_LDO9_CTRL_STATUS_SHIFT 4 1119#define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04 1120#define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 2 1121#define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01 1122#define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0 1123 1124/* Bit definitions for LDO9_VOLTAGE */ 1125#define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3f 1126#define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0 1127 1128/* Bit definitions for LDOLN_CTRL */ 1129#define PALMAS_LDOLN_CTRL_WR_S 0x80 1130#define PALMAS_LDOLN_CTRL_WR_S_SHIFT 7 1131#define PALMAS_LDOLN_CTRL_STATUS 0x10 1132#define PALMAS_LDOLN_CTRL_STATUS_SHIFT 4 1133#define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04 1134#define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 2 1135#define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01 1136#define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0 1137 1138/* Bit definitions for LDOLN_VOLTAGE */ 1139#define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3f 1140#define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0 1141 1142/* Bit definitions for LDOUSB_CTRL */ 1143#define PALMAS_LDOUSB_CTRL_WR_S 0x80 1144#define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 7 1145#define PALMAS_LDOUSB_CTRL_STATUS 0x10 1146#define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 4 1147#define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04 1148#define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 2 1149#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01 1150#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0 1151 1152/* Bit definitions for LDOUSB_VOLTAGE */ 1153#define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3f 1154#define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0 1155 1156/* Bit definitions for LDO_CTRL */ 1157#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01 1158#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0 1159 1160/* Bit definitions for LDO_PD_CTRL1 */ 1161#define PALMAS_LDO_PD_CTRL1_LDO8 0x80 1162#define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 7 1163#define PALMAS_LDO_PD_CTRL1_LDO7 0x40 1164#define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 6 1165#define PALMAS_LDO_PD_CTRL1_LDO6 0x20 1166#define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 5 1167#define PALMAS_LDO_PD_CTRL1_LDO5 0x10 1168#define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 4 1169#define PALMAS_LDO_PD_CTRL1_LDO4 0x08 1170#define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 3 1171#define PALMAS_LDO_PD_CTRL1_LDO3 0x04 1172#define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 2 1173#define PALMAS_LDO_PD_CTRL1_LDO2 0x02 1174#define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 1 1175#define PALMAS_LDO_PD_CTRL1_LDO1 0x01 1176#define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0 1177 1178/* Bit definitions for LDO_PD_CTRL2 */ 1179#define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04 1180#define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 2 1181#define PALMAS_LDO_PD_CTRL2_LDOLN 0x02 1182#define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 1 1183#define PALMAS_LDO_PD_CTRL2_LDO9 0x01 1184#define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0 1185 1186/* Bit definitions for LDO_SHORT_STATUS1 */ 1187#define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80 1188#define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 7 1189#define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40 1190#define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 6 1191#define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20 1192#define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 5 1193#define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10 1194#define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 4 1195#define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08 1196#define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 3 1197#define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04 1198#define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 2 1199#define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02 1200#define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 1 1201#define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01 1202#define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0 1203 1204/* Bit definitions for LDO_SHORT_STATUS2 */ 1205#define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08 1206#define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 3 1207#define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04 1208#define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 2 1209#define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02 1210#define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 1 1211#define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01 1212#define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0 1213 1214/* Registers for function PMU_CONTROL */ 1215#define PALMAS_DEV_CTRL 0x0 1216#define PALMAS_POWER_CTRL 0x1 1217#define PALMAS_VSYS_LO 0x2 1218#define PALMAS_VSYS_MON 0x3 1219#define PALMAS_VBAT_MON 0x4 1220#define PALMAS_WATCHDOG 0x5 1221#define PALMAS_BOOT_STATUS 0x6 1222#define PALMAS_BATTERY_BOUNCE 0x7 1223#define PALMAS_BACKUP_BATTERY_CTRL 0x8 1224#define PALMAS_LONG_PRESS_KEY 0x9 1225#define PALMAS_OSC_THERM_CTRL 0xA 1226#define PALMAS_BATDEBOUNCING 0xB 1227#define PALMAS_SWOFF_HWRST 0xF 1228#define PALMAS_SWOFF_COLDRST 0x10 1229#define PALMAS_SWOFF_STATUS 0x11 1230#define PALMAS_PMU_CONFIG 0x12 1231#define PALMAS_SPARE 0x14 1232#define PALMAS_PMU_SECONDARY_INT 0x15 1233#define PALMAS_SW_REVISION 0x17 1234#define PALMAS_EXT_CHRG_CTRL 0x18 1235#define PALMAS_PMU_SECONDARY_INT2 0x19 1236 1237/* Bit definitions for DEV_CTRL */ 1238#define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c 1239#define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 2 1240#define PALMAS_DEV_CTRL_SW_RST 0x02 1241#define PALMAS_DEV_CTRL_SW_RST_SHIFT 1 1242#define PALMAS_DEV_CTRL_DEV_ON 0x01 1243#define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0 1244 1245/* Bit definitions for POWER_CTRL */ 1246#define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04 1247#define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 2 1248#define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02 1249#define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 1 1250#define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01 1251#define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0 1252 1253/* Bit definitions for VSYS_LO */ 1254#define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1f 1255#define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0 1256 1257/* Bit definitions for VSYS_MON */ 1258#define PALMAS_VSYS_MON_ENABLE 0x80 1259#define PALMAS_VSYS_MON_ENABLE_SHIFT 7 1260#define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3f 1261#define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0 1262 1263/* Bit definitions for VBAT_MON */ 1264#define PALMAS_VBAT_MON_ENABLE 0x80 1265#define PALMAS_VBAT_MON_ENABLE_SHIFT 7 1266#define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3f 1267#define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0 1268 1269/* Bit definitions for WATCHDOG */ 1270#define PALMAS_WATCHDOG_LOCK 0x20 1271#define PALMAS_WATCHDOG_LOCK_SHIFT 5 1272#define PALMAS_WATCHDOG_ENABLE 0x10 1273#define PALMAS_WATCHDOG_ENABLE_SHIFT 4 1274#define PALMAS_WATCHDOG_MODE 0x08 1275#define PALMAS_WATCHDOG_MODE_SHIFT 3 1276#define PALMAS_WATCHDOG_TIMER_MASK 0x07 1277#define PALMAS_WATCHDOG_TIMER_SHIFT 0 1278 1279/* Bit definitions for BOOT_STATUS */ 1280#define PALMAS_BOOT_STATUS_BOOT1 0x02 1281#define PALMAS_BOOT_STATUS_BOOT1_SHIFT 1 1282#define PALMAS_BOOT_STATUS_BOOT0 0x01 1283#define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0 1284 1285/* Bit definitions for BATTERY_BOUNCE */ 1286#define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3f 1287#define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0 1288 1289/* Bit definitions for BACKUP_BATTERY_CTRL */ 1290#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80 1291#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 7 1292#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40 1293#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 6 1294#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20 1295#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 5 1296#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10 1297#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 4 1298#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08 1299#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 3 1300#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06 1301#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 1 1302#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01 1303#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0 1304 1305/* Bit definitions for LONG_PRESS_KEY */ 1306#define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80 1307#define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 7 1308#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10 1309#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 4 1310#define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c 1311#define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 2 1312#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03 1313#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0 1314 1315/* Bit definitions for OSC_THERM_CTRL */ 1316#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80 1317#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 7 1318#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40 1319#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 6 1320#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20 1321#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 5 1322#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10 1323#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 4 1324#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c 1325#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 2 1326#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02 1327#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 1 1328#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01 1329#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0 1330 1331/* Bit definitions for BATDEBOUNCING */ 1332#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80 1333#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 7 1334#define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78 1335#define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 3 1336#define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07 1337#define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0 1338 1339/* Bit definitions for SWOFF_HWRST */ 1340#define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80 1341#define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 7 1342#define PALMAS_SWOFF_HWRST_PWRDOWN 0x40 1343#define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 6 1344#define PALMAS_SWOFF_HWRST_WTD 0x20 1345#define PALMAS_SWOFF_HWRST_WTD_SHIFT 5 1346#define PALMAS_SWOFF_HWRST_TSHUT 0x10 1347#define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 4 1348#define PALMAS_SWOFF_HWRST_RESET_IN 0x08 1349#define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 3 1350#define PALMAS_SWOFF_HWRST_SW_RST 0x04 1351#define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 2 1352#define PALMAS_SWOFF_HWRST_VSYS_LO 0x02 1353#define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 1 1354#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01 1355#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0 1356 1357/* Bit definitions for SWOFF_COLDRST */ 1358#define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80 1359#define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 7 1360#define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40 1361#define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 6 1362#define PALMAS_SWOFF_COLDRST_WTD 0x20 1363#define PALMAS_SWOFF_COLDRST_WTD_SHIFT 5 1364#define PALMAS_SWOFF_COLDRST_TSHUT 0x10 1365#define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 4 1366#define PALMAS_SWOFF_COLDRST_RESET_IN 0x08 1367#define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 3 1368#define PALMAS_SWOFF_COLDRST_SW_RST 0x04 1369#define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 2 1370#define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02 1371#define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 1 1372#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01 1373#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0 1374 1375/* Bit definitions for SWOFF_STATUS */ 1376#define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80 1377#define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 7 1378#define PALMAS_SWOFF_STATUS_PWRDOWN 0x40 1379#define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 6 1380#define PALMAS_SWOFF_STATUS_WTD 0x20 1381#define PALMAS_SWOFF_STATUS_WTD_SHIFT 5 1382#define PALMAS_SWOFF_STATUS_TSHUT 0x10 1383#define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 4 1384#define PALMAS_SWOFF_STATUS_RESET_IN 0x08 1385#define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 3 1386#define PALMAS_SWOFF_STATUS_SW_RST 0x04 1387#define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 2 1388#define PALMAS_SWOFF_STATUS_VSYS_LO 0x02 1389#define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 1 1390#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01 1391#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0 1392 1393/* Bit definitions for PMU_CONFIG */ 1394#define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40 1395#define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 6 1396#define PALMAS_PMU_CONFIG_SPARE_MASK 0x30 1397#define PALMAS_PMU_CONFIG_SPARE_SHIFT 4 1398#define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c 1399#define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 2 1400#define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02 1401#define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 1 1402#define PALMAS_PMU_CONFIG_AUTODEVON 0x01 1403#define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0 1404 1405/* Bit definitions for SPARE */ 1406#define PALMAS_SPARE_SPARE_MASK 0xf8 1407#define PALMAS_SPARE_SPARE_SHIFT 3 1408#define PALMAS_SPARE_REGEN3_OD 0x04 1409#define PALMAS_SPARE_REGEN3_OD_SHIFT 2 1410#define PALMAS_SPARE_REGEN2_OD 0x02 1411#define PALMAS_SPARE_REGEN2_OD_SHIFT 1 1412#define PALMAS_SPARE_REGEN1_OD 0x01 1413#define PALMAS_SPARE_REGEN1_OD_SHIFT 0 1414 1415/* Bit definitions for PMU_SECONDARY_INT */ 1416#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80 1417#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 7 1418#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40 1419#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 6 1420#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20 1421#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 5 1422#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10 1423#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 4 1424#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08 1425#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 3 1426#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04 1427#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 2 1428#define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02 1429#define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 1 1430#define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01 1431#define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0 1432 1433/* Bit definitions for SW_REVISION */ 1434#define PALMAS_SW_REVISION_SW_REVISION_MASK 0xff 1435#define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0 1436 1437/* Bit definitions for EXT_CHRG_CTRL */ 1438#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80 1439#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 7 1440#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40 1441#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 6 1442#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08 1443#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 3 1444#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04 1445#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 2 1446#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02 1447#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 1 1448#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01 1449#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0 1450 1451/* Bit definitions for PMU_SECONDARY_INT2 */ 1452#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20 1453#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 5 1454#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10 1455#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 4 1456#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02 1457#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 1 1458#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01 1459#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0 1460 1461/* Registers for function RESOURCE */ 1462#define PALMAS_CLK32KG_CTRL 0x0 1463#define PALMAS_CLK32KGAUDIO_CTRL 0x1 1464#define PALMAS_REGEN1_CTRL 0x2 1465#define PALMAS_REGEN2_CTRL 0x3 1466#define PALMAS_SYSEN1_CTRL 0x4 1467#define PALMAS_SYSEN2_CTRL 0x5 1468#define PALMAS_NSLEEP_RES_ASSIGN 0x6 1469#define PALMAS_NSLEEP_SMPS_ASSIGN 0x7 1470#define PALMAS_NSLEEP_LDO_ASSIGN1 0x8 1471#define PALMAS_NSLEEP_LDO_ASSIGN2 0x9 1472#define PALMAS_ENABLE1_RES_ASSIGN 0xA 1473#define PALMAS_ENABLE1_SMPS_ASSIGN 0xB 1474#define PALMAS_ENABLE1_LDO_ASSIGN1 0xC 1475#define PALMAS_ENABLE1_LDO_ASSIGN2 0xD 1476#define PALMAS_ENABLE2_RES_ASSIGN 0xE 1477#define PALMAS_ENABLE2_SMPS_ASSIGN 0xF 1478#define PALMAS_ENABLE2_LDO_ASSIGN1 0x10 1479#define PALMAS_ENABLE2_LDO_ASSIGN2 0x11 1480#define PALMAS_REGEN3_CTRL 0x12 1481 1482/* Bit definitions for CLK32KG_CTRL */ 1483#define PALMAS_CLK32KG_CTRL_STATUS 0x10 1484#define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 4 1485#define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04 1486#define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 2 1487#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01 1488#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0 1489 1490/* Bit definitions for CLK32KGAUDIO_CTRL */ 1491#define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10 1492#define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 4 1493#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08 1494#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 3 1495#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04 1496#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 2 1497#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01 1498#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0 1499 1500/* Bit definitions for REGEN1_CTRL */ 1501#define PALMAS_REGEN1_CTRL_STATUS 0x10 1502#define PALMAS_REGEN1_CTRL_STATUS_SHIFT 4 1503#define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04 1504#define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 2 1505#define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01 1506#define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0 1507 1508/* Bit definitions for REGEN2_CTRL */ 1509#define PALMAS_REGEN2_CTRL_STATUS 0x10 1510#define PALMAS_REGEN2_CTRL_STATUS_SHIFT 4 1511#define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04 1512#define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 2 1513#define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01 1514#define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0 1515 1516/* Bit definitions for SYSEN1_CTRL */ 1517#define PALMAS_SYSEN1_CTRL_STATUS 0x10 1518#define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 4 1519#define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04 1520#define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 2 1521#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01 1522#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0 1523 1524/* Bit definitions for SYSEN2_CTRL */ 1525#define PALMAS_SYSEN2_CTRL_STATUS 0x10 1526#define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 4 1527#define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04 1528#define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 2 1529#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01 1530#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0 1531 1532/* Bit definitions for NSLEEP_RES_ASSIGN */ 1533#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40 1534#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 6 1535#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20 1536#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 1537#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10 1538#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 4 1539#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08 1540#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 3 1541#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04 1542#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 2 1543#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02 1544#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 1 1545#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01 1546#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0 1547 1548/* Bit definitions for NSLEEP_SMPS_ASSIGN */ 1549#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80 1550#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 7 1551#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40 1552#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 6 1553#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20 1554#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 5 1555#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10 1556#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 4 1557#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08 1558#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 3 1559#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04 1560#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 2 1561#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02 1562#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 1 1563#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01 1564#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0 1565 1566/* Bit definitions for NSLEEP_LDO_ASSIGN1 */ 1567#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80 1568#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 7 1569#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40 1570#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 6 1571#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20 1572#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 5 1573#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10 1574#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 4 1575#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08 1576#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 3 1577#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04 1578#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 2 1579#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02 1580#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 1 1581#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01 1582#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0 1583 1584/* Bit definitions for NSLEEP_LDO_ASSIGN2 */ 1585#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04 1586#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 2 1587#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02 1588#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 1 1589#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01 1590#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0 1591 1592/* Bit definitions for ENABLE1_RES_ASSIGN */ 1593#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40 1594#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 6 1595#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20 1596#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 1597#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10 1598#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 4 1599#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08 1600#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 3 1601#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04 1602#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 2 1603#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02 1604#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 1 1605#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01 1606#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0 1607 1608/* Bit definitions for ENABLE1_SMPS_ASSIGN */ 1609#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80 1610#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 7 1611#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40 1612#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 6 1613#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20 1614#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 5 1615#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10 1616#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 4 1617#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08 1618#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 3 1619#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04 1620#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 2 1621#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02 1622#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 1 1623#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01 1624#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0 1625 1626/* Bit definitions for ENABLE1_LDO_ASSIGN1 */ 1627#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80 1628#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 7 1629#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40 1630#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 6 1631#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20 1632#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 5 1633#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10 1634#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 4 1635#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08 1636#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 3 1637#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04 1638#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 2 1639#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02 1640#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 1 1641#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01 1642#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0 1643 1644/* Bit definitions for ENABLE1_LDO_ASSIGN2 */ 1645#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04 1646#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 2 1647#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02 1648#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 1 1649#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01 1650#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0 1651 1652/* Bit definitions for ENABLE2_RES_ASSIGN */ 1653#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40 1654#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 6 1655#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20 1656#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 1657#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10 1658#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 4 1659#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08 1660#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 3 1661#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04 1662#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 2 1663#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02 1664#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 1 1665#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01 1666#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0 1667 1668/* Bit definitions for ENABLE2_SMPS_ASSIGN */ 1669#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80 1670#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 7 1671#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40 1672#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 6 1673#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20 1674#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 5 1675#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10 1676#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 4 1677#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08 1678#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 3 1679#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04 1680#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 2 1681#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02 1682#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 1 1683#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01 1684#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0 1685 1686/* Bit definitions for ENABLE2_LDO_ASSIGN1 */ 1687#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80 1688#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 7 1689#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40 1690#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 6 1691#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20 1692#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 5 1693#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10 1694#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 4 1695#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08 1696#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 3 1697#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04 1698#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 2 1699#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02 1700#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 1 1701#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01 1702#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0 1703 1704/* Bit definitions for ENABLE2_LDO_ASSIGN2 */ 1705#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04 1706#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 2 1707#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02 1708#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 1 1709#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01 1710#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0 1711 1712/* Bit definitions for REGEN3_CTRL */ 1713#define PALMAS_REGEN3_CTRL_STATUS 0x10 1714#define PALMAS_REGEN3_CTRL_STATUS_SHIFT 4 1715#define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04 1716#define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 2 1717#define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01 1718#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0 1719 1720/* Registers for function PAD_CONTROL */ 1721#define PALMAS_PU_PD_INPUT_CTRL1 0x0 1722#define PALMAS_PU_PD_INPUT_CTRL2 0x1 1723#define PALMAS_PU_PD_INPUT_CTRL3 0x2 1724#define PALMAS_OD_OUTPUT_CTRL 0x4 1725#define PALMAS_POLARITY_CTRL 0x5 1726#define PALMAS_PRIMARY_SECONDARY_PAD1 0x6 1727#define PALMAS_PRIMARY_SECONDARY_PAD2 0x7 1728#define PALMAS_I2C_SPI 0x8 1729#define PALMAS_PU_PD_INPUT_CTRL4 0x9 1730#define PALMAS_PRIMARY_SECONDARY_PAD3 0xA 1731 1732/* Bit definitions for PU_PD_INPUT_CTRL1 */ 1733#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40 1734#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 6 1735#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20 1736#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 5 1737#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10 1738#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 4 1739#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04 1740#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 2 1741#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02 1742#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 1 1743 1744/* Bit definitions for PU_PD_INPUT_CTRL2 */ 1745#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20 1746#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 5 1747#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10 1748#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 4 1749#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08 1750#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 3 1751#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04 1752#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 2 1753#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02 1754#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 1 1755#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01 1756#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0 1757 1758/* Bit definitions for PU_PD_INPUT_CTRL3 */ 1759#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40 1760#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 6 1761#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10 1762#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 4 1763#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04 1764#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 2 1765#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01 1766#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0 1767 1768/* Bit definitions for OD_OUTPUT_CTRL */ 1769#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80 1770#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 7 1771#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40 1772#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 6 1773#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20 1774#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 5 1775#define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08 1776#define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 3 1777 1778/* Bit definitions for POLARITY_CTRL */ 1779#define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80 1780#define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 7 1781#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40 1782#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 6 1783#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20 1784#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 5 1785#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10 1786#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 4 1787#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08 1788#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 3 1789#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04 1790#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 2 1791#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02 1792#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 1 1793#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01 1794#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0 1795 1796/* Bit definitions for PRIMARY_SECONDARY_PAD1 */ 1797#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80 1798#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 7 1799#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60 1800#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 5 1801#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18 1802#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 3 1803#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04 1804#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 2 1805#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02 1806#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 1 1807#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01 1808#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0 1809 1810/* Bit definitions for PRIMARY_SECONDARY_PAD2 */ 1811#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30 1812#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 4 1813#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08 1814#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 3 1815#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06 1816#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 1 1817#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01 1818#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0 1819 1820/* Bit definitions for I2C_SPI */ 1821#define PALMAS_I2C_SPI_I2C2OTP_EN 0x80 1822#define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 7 1823#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40 1824#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 6 1825#define PALMAS_I2C_SPI_ID_I2C2 0x20 1826#define PALMAS_I2C_SPI_ID_I2C2_SHIFT 5 1827#define PALMAS_I2C_SPI_I2C_SPI 0x10 1828#define PALMAS_I2C_SPI_I2C_SPI_SHIFT 4 1829#define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0f 1830#define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0 1831 1832/* Bit definitions for PU_PD_INPUT_CTRL4 */ 1833#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40 1834#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 6 1835#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10 1836#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 4 1837#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04 1838#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 2 1839#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01 1840#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0 1841 1842/* Bit definitions for PRIMARY_SECONDARY_PAD3 */ 1843#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02 1844#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 1 1845#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01 1846#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0 1847 1848/* Registers for function LED_PWM */ 1849#define PALMAS_LED_PERIOD_CTRL 0x0 1850#define PALMAS_LED_CTRL 0x1 1851#define PALMAS_PWM_CTRL1 0x2 1852#define PALMAS_PWM_CTRL2 0x3 1853 1854/* Bit definitions for LED_PERIOD_CTRL */ 1855#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38 1856#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 3 1857#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07 1858#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0 1859 1860/* Bit definitions for LED_CTRL */ 1861#define PALMAS_LED_CTRL_LED_2_SEQ 0x20 1862#define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 5 1863#define PALMAS_LED_CTRL_LED_1_SEQ 0x10 1864#define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 4 1865#define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c 1866#define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 2 1867#define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03 1868#define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0 1869 1870/* Bit definitions for PWM_CTRL1 */ 1871#define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02 1872#define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 1 1873#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01 1874#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0 1875 1876/* Bit definitions for PWM_CTRL2 */ 1877#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xff 1878#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0 1879 1880/* Registers for function INTERRUPT */ 1881#define PALMAS_INT1_STATUS 0x0 1882#define PALMAS_INT1_MASK 0x1 1883#define PALMAS_INT1_LINE_STATE 0x2 1884#define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x3 1885#define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x4 1886#define PALMAS_INT2_STATUS 0x5 1887#define PALMAS_INT2_MASK 0x6 1888#define PALMAS_INT2_LINE_STATE 0x7 1889#define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x8 1890#define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x9 1891#define PALMAS_INT3_STATUS 0xA 1892#define PALMAS_INT3_MASK 0xB 1893#define PALMAS_INT3_LINE_STATE 0xC 1894#define PALMAS_INT3_EDGE_DETECT1_RESERVED 0xD 1895#define PALMAS_INT3_EDGE_DETECT2_RESERVED 0xE 1896#define PALMAS_INT4_STATUS 0xF 1897#define PALMAS_INT4_MASK 0x10 1898#define PALMAS_INT4_LINE_STATE 0x11 1899#define PALMAS_INT4_EDGE_DETECT1 0x12 1900#define PALMAS_INT4_EDGE_DETECT2 0x13 1901#define PALMAS_INT_CTRL 0x14 1902 1903/* Bit definitions for INT1_STATUS */ 1904#define PALMAS_INT1_STATUS_VBAT_MON 0x80 1905#define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 7 1906#define PALMAS_INT1_STATUS_VSYS_MON 0x40 1907#define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 6 1908#define PALMAS_INT1_STATUS_HOTDIE 0x20 1909#define PALMAS_INT1_STATUS_HOTDIE_SHIFT 5 1910#define PALMAS_INT1_STATUS_PWRDOWN 0x10 1911#define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 4 1912#define PALMAS_INT1_STATUS_RPWRON 0x08 1913#define PALMAS_INT1_STATUS_RPWRON_SHIFT 3 1914#define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04 1915#define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 2 1916#define PALMAS_INT1_STATUS_PWRON 0x02 1917#define PALMAS_INT1_STATUS_PWRON_SHIFT 1 1918#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01 1919#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0 1920 1921/* Bit definitions for INT1_MASK */ 1922#define PALMAS_INT1_MASK_VBAT_MON 0x80 1923#define PALMAS_INT1_MASK_VBAT_MON_SHIFT 7 1924#define PALMAS_INT1_MASK_VSYS_MON 0x40 1925#define PALMAS_INT1_MASK_VSYS_MON_SHIFT 6 1926#define PALMAS_INT1_MASK_HOTDIE 0x20 1927#define PALMAS_INT1_MASK_HOTDIE_SHIFT 5 1928#define PALMAS_INT1_MASK_PWRDOWN 0x10 1929#define PALMAS_INT1_MASK_PWRDOWN_SHIFT 4 1930#define PALMAS_INT1_MASK_RPWRON 0x08 1931#define PALMAS_INT1_MASK_RPWRON_SHIFT 3 1932#define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04 1933#define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 2 1934#define PALMAS_INT1_MASK_PWRON 0x02 1935#define PALMAS_INT1_MASK_PWRON_SHIFT 1 1936#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01 1937#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0 1938 1939/* Bit definitions for INT1_LINE_STATE */ 1940#define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80 1941#define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 7 1942#define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40 1943#define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 6 1944#define PALMAS_INT1_LINE_STATE_HOTDIE 0x20 1945#define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 5 1946#define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10 1947#define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 4 1948#define PALMAS_INT1_LINE_STATE_RPWRON 0x08 1949#define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 3 1950#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04 1951#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 2 1952#define PALMAS_INT1_LINE_STATE_PWRON 0x02 1953#define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 1 1954#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01 1955#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0 1956 1957/* Bit definitions for INT2_STATUS */ 1958#define PALMAS_INT2_STATUS_VAC_ACOK 0x80 1959#define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 7 1960#define PALMAS_INT2_STATUS_SHORT 0x40 1961#define PALMAS_INT2_STATUS_SHORT_SHIFT 6 1962#define PALMAS_INT2_STATUS_FBI_BB 0x20 1963#define PALMAS_INT2_STATUS_FBI_BB_SHIFT 5 1964#define PALMAS_INT2_STATUS_RESET_IN 0x10 1965#define PALMAS_INT2_STATUS_RESET_IN_SHIFT 4 1966#define PALMAS_INT2_STATUS_BATREMOVAL 0x08 1967#define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 3 1968#define PALMAS_INT2_STATUS_WDT 0x04 1969#define PALMAS_INT2_STATUS_WDT_SHIFT 2 1970#define PALMAS_INT2_STATUS_RTC_TIMER 0x02 1971#define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 1 1972#define PALMAS_INT2_STATUS_RTC_ALARM 0x01 1973#define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0 1974 1975/* Bit definitions for INT2_MASK */ 1976#define PALMAS_INT2_MASK_VAC_ACOK 0x80 1977#define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 7 1978#define PALMAS_INT2_MASK_SHORT 0x40 1979#define PALMAS_INT2_MASK_SHORT_SHIFT 6 1980#define PALMAS_INT2_MASK_FBI_BB 0x20 1981#define PALMAS_INT2_MASK_FBI_BB_SHIFT 5 1982#define PALMAS_INT2_MASK_RESET_IN 0x10 1983#define PALMAS_INT2_MASK_RESET_IN_SHIFT 4 1984#define PALMAS_INT2_MASK_BATREMOVAL 0x08 1985#define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 3 1986#define PALMAS_INT2_MASK_WDT 0x04 1987#define PALMAS_INT2_MASK_WDT_SHIFT 2 1988#define PALMAS_INT2_MASK_RTC_TIMER 0x02 1989#define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 1 1990#define PALMAS_INT2_MASK_RTC_ALARM 0x01 1991#define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0 1992 1993/* Bit definitions for INT2_LINE_STATE */ 1994#define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80 1995#define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 7 1996#define PALMAS_INT2_LINE_STATE_SHORT 0x40 1997#define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 6 1998#define PALMAS_INT2_LINE_STATE_FBI_BB 0x20 1999#define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 5 2000#define PALMAS_INT2_LINE_STATE_RESET_IN 0x10 2001#define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 4 2002#define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08 2003#define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 3 2004#define PALMAS_INT2_LINE_STATE_WDT 0x04 2005#define PALMAS_INT2_LINE_STATE_WDT_SHIFT 2 2006#define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02 2007#define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 1 2008#define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01 2009#define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0 2010 2011/* Bit definitions for INT3_STATUS */ 2012#define PALMAS_INT3_STATUS_VBUS 0x80 2013#define PALMAS_INT3_STATUS_VBUS_SHIFT 7 2014#define PALMAS_INT3_STATUS_VBUS_OTG 0x40 2015#define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 6 2016#define PALMAS_INT3_STATUS_ID 0x20 2017#define PALMAS_INT3_STATUS_ID_SHIFT 5 2018#define PALMAS_INT3_STATUS_ID_OTG 0x10 2019#define PALMAS_INT3_STATUS_ID_OTG_SHIFT 4 2020#define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08 2021#define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 3 2022#define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04 2023#define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 2 2024#define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02 2025#define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 1 2026#define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01 2027#define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0 2028 2029/* Bit definitions for INT3_MASK */ 2030#define PALMAS_INT3_MASK_VBUS 0x80 2031#define PALMAS_INT3_MASK_VBUS_SHIFT 7 2032#define PALMAS_INT3_MASK_VBUS_OTG 0x40 2033#define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 6 2034#define PALMAS_INT3_MASK_ID 0x20 2035#define PALMAS_INT3_MASK_ID_SHIFT 5 2036#define PALMAS_INT3_MASK_ID_OTG 0x10 2037#define PALMAS_INT3_MASK_ID_OTG_SHIFT 4 2038#define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08 2039#define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 3 2040#define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04 2041#define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 2 2042#define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02 2043#define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 1 2044#define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01 2045#define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0 2046 2047/* Bit definitions for INT3_LINE_STATE */ 2048#define PALMAS_INT3_LINE_STATE_VBUS 0x80 2049#define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 7 2050#define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40 2051#define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 6 2052#define PALMAS_INT3_LINE_STATE_ID 0x20 2053#define PALMAS_INT3_LINE_STATE_ID_SHIFT 5 2054#define PALMAS_INT3_LINE_STATE_ID_OTG 0x10 2055#define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 4 2056#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08 2057#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 3 2058#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04 2059#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 2 2060#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02 2061#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 1 2062#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01 2063#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0 2064 2065/* Bit definitions for INT4_STATUS */ 2066#define PALMAS_INT4_STATUS_GPIO_7 0x80 2067#define PALMAS_INT4_STATUS_GPIO_7_SHIFT 7 2068#define PALMAS_INT4_STATUS_GPIO_6 0x40 2069#define PALMAS_INT4_STATUS_GPIO_6_SHIFT 6 2070#define PALMAS_INT4_STATUS_GPIO_5 0x20 2071#define PALMAS_INT4_STATUS_GPIO_5_SHIFT 5 2072#define PALMAS_INT4_STATUS_GPIO_4 0x10 2073#define PALMAS_INT4_STATUS_GPIO_4_SHIFT 4 2074#define PALMAS_INT4_STATUS_GPIO_3 0x08 2075#define PALMAS_INT4_STATUS_GPIO_3_SHIFT 3 2076#define PALMAS_INT4_STATUS_GPIO_2 0x04 2077#define PALMAS_INT4_STATUS_GPIO_2_SHIFT 2 2078#define PALMAS_INT4_STATUS_GPIO_1 0x02 2079#define PALMAS_INT4_STATUS_GPIO_1_SHIFT 1 2080#define PALMAS_INT4_STATUS_GPIO_0 0x01 2081#define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0 2082 2083/* Bit definitions for INT4_MASK */ 2084#define PALMAS_INT4_MASK_GPIO_7 0x80 2085#define PALMAS_INT4_MASK_GPIO_7_SHIFT 7 2086#define PALMAS_INT4_MASK_GPIO_6 0x40 2087#define PALMAS_INT4_MASK_GPIO_6_SHIFT 6 2088#define PALMAS_INT4_MASK_GPIO_5 0x20 2089#define PALMAS_INT4_MASK_GPIO_5_SHIFT 5 2090#define PALMAS_INT4_MASK_GPIO_4 0x10 2091#define PALMAS_INT4_MASK_GPIO_4_SHIFT 4 2092#define PALMAS_INT4_MASK_GPIO_3 0x08 2093#define PALMAS_INT4_MASK_GPIO_3_SHIFT 3 2094#define PALMAS_INT4_MASK_GPIO_2 0x04 2095#define PALMAS_INT4_MASK_GPIO_2_SHIFT 2 2096#define PALMAS_INT4_MASK_GPIO_1 0x02 2097#define PALMAS_INT4_MASK_GPIO_1_SHIFT 1 2098#define PALMAS_INT4_MASK_GPIO_0 0x01 2099#define PALMAS_INT4_MASK_GPIO_0_SHIFT 0 2100 2101/* Bit definitions for INT4_LINE_STATE */ 2102#define PALMAS_INT4_LINE_STATE_GPIO_7 0x80 2103#define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 7 2104#define PALMAS_INT4_LINE_STATE_GPIO_6 0x40 2105#define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 6 2106#define PALMAS_INT4_LINE_STATE_GPIO_5 0x20 2107#define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 5 2108#define PALMAS_INT4_LINE_STATE_GPIO_4 0x10 2109#define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 4 2110#define PALMAS_INT4_LINE_STATE_GPIO_3 0x08 2111#define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 3 2112#define PALMAS_INT4_LINE_STATE_GPIO_2 0x04 2113#define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 2 2114#define PALMAS_INT4_LINE_STATE_GPIO_1 0x02 2115#define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 1 2116#define PALMAS_INT4_LINE_STATE_GPIO_0 0x01 2117#define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0 2118 2119/* Bit definitions for INT4_EDGE_DETECT1 */ 2120#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80 2121#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 7 2122#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40 2123#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 6 2124#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20 2125#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 5 2126#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10 2127#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 4 2128#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08 2129#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 3 2130#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04 2131#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 2 2132#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02 2133#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 1 2134#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01 2135#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0 2136 2137/* Bit definitions for INT4_EDGE_DETECT2 */ 2138#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80 2139#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 7 2140#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40 2141#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 6 2142#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20 2143#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 5 2144#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10 2145#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 4 2146#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08 2147#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 3 2148#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04 2149#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 2 2150#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02 2151#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 1 2152#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01 2153#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0 2154 2155/* Bit definitions for INT_CTRL */ 2156#define PALMAS_INT_CTRL_INT_PENDING 0x04 2157#define PALMAS_INT_CTRL_INT_PENDING_SHIFT 2 2158#define PALMAS_INT_CTRL_INT_CLEAR 0x01 2159#define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0 2160 2161/* Registers for function USB_OTG */ 2162#define PALMAS_USB_WAKEUP 0x3 2163#define PALMAS_USB_VBUS_CTRL_SET 0x4 2164#define PALMAS_USB_VBUS_CTRL_CLR 0x5 2165#define PALMAS_USB_ID_CTRL_SET 0x6 2166#define PALMAS_USB_ID_CTRL_CLEAR 0x7 2167#define PALMAS_USB_VBUS_INT_SRC 0x8 2168#define PALMAS_USB_VBUS_INT_LATCH_SET 0x9 2169#define PALMAS_USB_VBUS_INT_LATCH_CLR 0xA 2170#define PALMAS_USB_VBUS_INT_EN_LO_SET 0xB 2171#define PALMAS_USB_VBUS_INT_EN_LO_CLR 0xC 2172#define PALMAS_USB_VBUS_INT_EN_HI_SET 0xD 2173#define PALMAS_USB_VBUS_INT_EN_HI_CLR 0xE 2174#define PALMAS_USB_ID_INT_SRC 0xF 2175#define PALMAS_USB_ID_INT_LATCH_SET 0x10 2176#define PALMAS_USB_ID_INT_LATCH_CLR 0x11 2177#define PALMAS_USB_ID_INT_EN_LO_SET 0x12 2178#define PALMAS_USB_ID_INT_EN_LO_CLR 0x13 2179#define PALMAS_USB_ID_INT_EN_HI_SET 0x14 2180#define PALMAS_USB_ID_INT_EN_HI_CLR 0x15 2181#define PALMAS_USB_OTG_ADP_CTRL 0x16 2182#define PALMAS_USB_OTG_ADP_HIGH 0x17 2183#define PALMAS_USB_OTG_ADP_LOW 0x18 2184#define PALMAS_USB_OTG_ADP_RISE 0x19 2185#define PALMAS_USB_OTG_REVISION 0x1A 2186 2187/* Bit definitions for USB_WAKEUP */ 2188#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01 2189#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0 2190 2191/* Bit definitions for USB_VBUS_CTRL_SET */ 2192#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80 2193#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 7 2194#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20 2195#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 5 2196#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10 2197#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 4 2198#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08 2199#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 3 2200#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04 2201#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 2 2202 2203/* Bit definitions for USB_VBUS_CTRL_CLR */ 2204#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80 2205#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 7 2206#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20 2207#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 5 2208#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10 2209#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 4 2210#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08 2211#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 3 2212#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04 2213#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 2 2214 2215/* Bit definitions for USB_ID_CTRL_SET */ 2216#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80 2217#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 7 2218#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40 2219#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 6 2220#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20 2221#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 5 2222#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10 2223#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 4 2224#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08 2225#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 3 2226#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04 2227#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 2 2228 2229/* Bit definitions for USB_ID_CTRL_CLEAR */ 2230#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80 2231#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 7 2232#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40 2233#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 6 2234#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20 2235#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 5 2236#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10 2237#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 4 2238#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08 2239#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 3 2240#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04 2241#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 2 2242 2243/* Bit definitions for USB_VBUS_INT_SRC */ 2244#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80 2245#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 7 2246#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40 2247#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 6 2248#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20 2249#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 5 2250#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08 2251#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 3 2252#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04 2253#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 2 2254#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02 2255#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 1 2256#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01 2257#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0 2258 2259/* Bit definitions for USB_VBUS_INT_LATCH_SET */ 2260#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80 2261#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 7 2262#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40 2263#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 6 2264#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20 2265#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 5 2266#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10 2267#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 4 2268#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08 2269#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 3 2270#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04 2271#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 2 2272#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02 2273#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 1 2274#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01 2275#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0 2276 2277/* Bit definitions for USB_VBUS_INT_LATCH_CLR */ 2278#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80 2279#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 7 2280#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40 2281#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 6 2282#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20 2283#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 5 2284#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10 2285#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 4 2286#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08 2287#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 3 2288#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04 2289#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 2 2290#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02 2291#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 1 2292#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01 2293#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0 2294 2295/* Bit definitions for USB_VBUS_INT_EN_LO_SET */ 2296#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80 2297#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 7 2298#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40 2299#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 6 2300#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20 2301#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 5 2302#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08 2303#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 3 2304#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04 2305#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 2 2306#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02 2307#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 1 2308#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01 2309#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0 2310 2311/* Bit definitions for USB_VBUS_INT_EN_LO_CLR */ 2312#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80 2313#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 7 2314#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40 2315#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 6 2316#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20 2317#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 5 2318#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08 2319#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 3 2320#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04 2321#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 2 2322#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02 2323#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 1 2324#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01 2325#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0 2326 2327/* Bit definitions for USB_VBUS_INT_EN_HI_SET */ 2328#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80 2329#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 7 2330#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40 2331#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 6 2332#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20 2333#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 5 2334#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10 2335#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 4 2336#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08 2337#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 3 2338#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04 2339#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 2 2340#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02 2341#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 1 2342#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01 2343#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0 2344 2345/* Bit definitions for USB_VBUS_INT_EN_HI_CLR */ 2346#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80 2347#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 7 2348#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40 2349#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 6 2350#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20 2351#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 5 2352#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10 2353#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 4 2354#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08 2355#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 3 2356#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04 2357#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 2 2358#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02 2359#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 1 2360#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01 2361#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0 2362 2363/* Bit definitions for USB_ID_INT_SRC */ 2364#define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10 2365#define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 4 2366#define PALMAS_USB_ID_INT_SRC_ID_A 0x08 2367#define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 3 2368#define PALMAS_USB_ID_INT_SRC_ID_B 0x04 2369#define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 2 2370#define PALMAS_USB_ID_INT_SRC_ID_C 0x02 2371#define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 1 2372#define PALMAS_USB_ID_INT_SRC_ID_GND 0x01 2373#define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0 2374 2375/* Bit definitions for USB_ID_INT_LATCH_SET */ 2376#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10 2377#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 4 2378#define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08 2379#define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 3 2380#define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04 2381#define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 2 2382#define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02 2383#define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 1 2384#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01 2385#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0 2386 2387/* Bit definitions for USB_ID_INT_LATCH_CLR */ 2388#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10 2389#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 4 2390#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08 2391#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 3 2392#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04 2393#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 2 2394#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02 2395#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 1 2396#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01 2397#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0 2398 2399/* Bit definitions for USB_ID_INT_EN_LO_SET */ 2400#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10 2401#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 4 2402#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08 2403#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 3 2404#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04 2405#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 2 2406#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02 2407#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 1 2408#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01 2409#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0 2410 2411/* Bit definitions for USB_ID_INT_EN_LO_CLR */ 2412#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10 2413#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 4 2414#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08 2415#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 3 2416#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04 2417#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 2 2418#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02 2419#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 1 2420#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01 2421#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0 2422 2423/* Bit definitions for USB_ID_INT_EN_HI_SET */ 2424#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10 2425#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 4 2426#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08 2427#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 3 2428#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04 2429#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 2 2430#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02 2431#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 1 2432#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01 2433#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0 2434 2435/* Bit definitions for USB_ID_INT_EN_HI_CLR */ 2436#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10 2437#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 4 2438#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08 2439#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 3 2440#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04 2441#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 2 2442#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02 2443#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 1 2444#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01 2445#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0 2446 2447/* Bit definitions for USB_OTG_ADP_CTRL */ 2448#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04 2449#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 2 2450#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03 2451#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0 2452 2453/* Bit definitions for USB_OTG_ADP_HIGH */ 2454#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xff 2455#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0 2456 2457/* Bit definitions for USB_OTG_ADP_LOW */ 2458#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xff 2459#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0 2460 2461/* Bit definitions for USB_OTG_ADP_RISE */ 2462#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xff 2463#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0 2464 2465/* Bit definitions for USB_OTG_REVISION */ 2466#define PALMAS_USB_OTG_REVISION_OTG_REV 0x01 2467#define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0 2468 2469/* Registers for function VIBRATOR */ 2470#define PALMAS_VIBRA_CTRL 0x0 2471 2472/* Bit definitions for VIBRA_CTRL */ 2473#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06 2474#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 1 2475#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01 2476#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0 2477 2478/* Registers for function GPIO */ 2479#define PALMAS_GPIO_DATA_IN 0x0 2480#define PALMAS_GPIO_DATA_DIR 0x1 2481#define PALMAS_GPIO_DATA_OUT 0x2 2482#define PALMAS_GPIO_DEBOUNCE_EN 0x3 2483#define PALMAS_GPIO_CLEAR_DATA_OUT 0x4 2484#define PALMAS_GPIO_SET_DATA_OUT 0x5 2485#define PALMAS_PU_PD_GPIO_CTRL1 0x6 2486#define PALMAS_PU_PD_GPIO_CTRL2 0x7 2487#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x8 2488 2489/* Bit definitions for GPIO_DATA_IN */ 2490#define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80 2491#define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 7 2492#define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40 2493#define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 6 2494#define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20 2495#define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 5 2496#define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10 2497#define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 4 2498#define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08 2499#define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 3 2500#define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04 2501#define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 2 2502#define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02 2503#define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 1 2504#define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01 2505#define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0 2506 2507/* Bit definitions for GPIO_DATA_DIR */ 2508#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80 2509#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 7 2510#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40 2511#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 6 2512#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20 2513#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 5 2514#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10 2515#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 4 2516#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08 2517#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 3 2518#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04 2519#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 2 2520#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02 2521#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 1 2522#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01 2523#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0 2524 2525/* Bit definitions for GPIO_DATA_OUT */ 2526#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80 2527#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 7 2528#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40 2529#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 6 2530#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20 2531#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 5 2532#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10 2533#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 4 2534#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08 2535#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 3 2536#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04 2537#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 2 2538#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02 2539#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 1 2540#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01 2541#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0 2542 2543/* Bit definitions for GPIO_DEBOUNCE_EN */ 2544#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80 2545#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 7 2546#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40 2547#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 6 2548#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20 2549#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 5 2550#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10 2551#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 4 2552#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08 2553#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 3 2554#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04 2555#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 2 2556#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02 2557#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 1 2558#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01 2559#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0 2560 2561/* Bit definitions for GPIO_CLEAR_DATA_OUT */ 2562#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80 2563#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 7 2564#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40 2565#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 6 2566#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20 2567#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 5 2568#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10 2569#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 4 2570#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08 2571#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 3 2572#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04 2573#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 2 2574#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02 2575#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 1 2576#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01 2577#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0 2578 2579/* Bit definitions for GPIO_SET_DATA_OUT */ 2580#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80 2581#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 7 2582#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40 2583#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 6 2584#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20 2585#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 5 2586#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10 2587#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 4 2588#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08 2589#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 3 2590#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04 2591#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 2 2592#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02 2593#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 1 2594#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01 2595#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0 2596 2597/* Bit definitions for PU_PD_GPIO_CTRL1 */ 2598#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40 2599#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 6 2600#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20 2601#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 5 2602#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10 2603#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 4 2604#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08 2605#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 3 2606#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04 2607#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 2 2608#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01 2609#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0 2610 2611/* Bit definitions for PU_PD_GPIO_CTRL2 */ 2612#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40 2613#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 6 2614#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20 2615#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 5 2616#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10 2617#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 4 2618#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08 2619#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 3 2620#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04 2621#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 2 2622#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02 2623#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 1 2624#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01 2625#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0 2626 2627/* Bit definitions for OD_OUTPUT_GPIO_CTRL */ 2628#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20 2629#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 5 2630#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04 2631#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 2 2632#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02 2633#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 1 2634 2635/* Registers for function GPADC */ 2636#define PALMAS_GPADC_CTRL1 0x0 2637#define PALMAS_GPADC_CTRL2 0x1 2638#define PALMAS_GPADC_RT_CTRL 0x2 2639#define PALMAS_GPADC_AUTO_CTRL 0x3 2640#define PALMAS_GPADC_STATUS 0x4 2641#define PALMAS_GPADC_RT_SELECT 0x5 2642#define PALMAS_GPADC_RT_CONV0_LSB 0x6 2643#define PALMAS_GPADC_RT_CONV0_MSB 0x7 2644#define PALMAS_GPADC_AUTO_SELECT 0x8 2645#define PALMAS_GPADC_AUTO_CONV0_LSB 0x9 2646#define PALMAS_GPADC_AUTO_CONV0_MSB 0xA 2647#define PALMAS_GPADC_AUTO_CONV1_LSB 0xB 2648#define PALMAS_GPADC_AUTO_CONV1_MSB 0xC 2649#define PALMAS_GPADC_SW_SELECT 0xD 2650#define PALMAS_GPADC_SW_CONV0_LSB 0xE 2651#define PALMAS_GPADC_SW_CONV0_MSB 0xF 2652#define PALMAS_GPADC_THRES_CONV0_LSB 0x10 2653#define PALMAS_GPADC_THRES_CONV0_MSB 0x11 2654#define PALMAS_GPADC_THRES_CONV1_LSB 0x12 2655#define PALMAS_GPADC_THRES_CONV1_MSB 0x13 2656#define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14 2657#define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15 2658 2659/* Bit definitions for GPADC_CTRL1 */ 2660#define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0 2661#define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 6 2662#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30 2663#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 4 2664#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c 2665#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 2 2666#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02 2667#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 1 2668#define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01 2669#define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0 2670 2671/* Bit definitions for GPADC_CTRL2 */ 2672#define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06 2673#define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 1 2674 2675/* Bit definitions for GPADC_RT_CTRL */ 2676#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02 2677#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 1 2678#define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01 2679#define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0 2680 2681/* Bit definitions for GPADC_AUTO_CTRL */ 2682#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80 2683#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 7 2684#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40 2685#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 6 2686#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20 2687#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 5 2688#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10 2689#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 4 2690#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0f 2691#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0 2692 2693/* Bit definitions for GPADC_STATUS */ 2694#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10 2695#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 4 2696 2697/* Bit definitions for GPADC_RT_SELECT */ 2698#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80 2699#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 7 2700#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0f 2701#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0 2702 2703/* Bit definitions for GPADC_RT_CONV0_LSB */ 2704#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xff 2705#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0 2706 2707/* Bit definitions for GPADC_RT_CONV0_MSB */ 2708#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0f 2709#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0 2710 2711/* Bit definitions for GPADC_AUTO_SELECT */ 2712#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xf0 2713#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 4 2714#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0f 2715#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0 2716 2717/* Bit definitions for GPADC_AUTO_CONV0_LSB */ 2718#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xff 2719#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0 2720 2721/* Bit definitions for GPADC_AUTO_CONV0_MSB */ 2722#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0f 2723#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0 2724 2725/* Bit definitions for GPADC_AUTO_CONV1_LSB */ 2726#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xff 2727#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0 2728 2729/* Bit definitions for GPADC_AUTO_CONV1_MSB */ 2730#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0f 2731#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0 2732 2733/* Bit definitions for GPADC_SW_SELECT */ 2734#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80 2735#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 7 2736#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10 2737#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 4 2738#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0f 2739#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0 2740 2741/* Bit definitions for GPADC_SW_CONV0_LSB */ 2742#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xff 2743#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0 2744 2745/* Bit definitions for GPADC_SW_CONV0_MSB */ 2746#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0f 2747#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0 2748 2749/* Bit definitions for GPADC_THRES_CONV0_LSB */ 2750#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xff 2751#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0 2752 2753/* Bit definitions for GPADC_THRES_CONV0_MSB */ 2754#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80 2755#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 7 2756#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0f 2757#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0 2758 2759/* Bit definitions for GPADC_THRES_CONV1_LSB */ 2760#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xff 2761#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0 2762 2763/* Bit definitions for GPADC_THRES_CONV1_MSB */ 2764#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80 2765#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 7 2766#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0f 2767#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0 2768 2769/* Bit definitions for GPADC_SMPS_ILMONITOR_EN */ 2770#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20 2771#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 5 2772#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10 2773#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 4 2774#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0f 2775#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0 2776 2777/* Bit definitions for GPADC_SMPS_VSEL_MONITORING */ 2778#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80 2779#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 7 2780#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7f 2781#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0 2782 2783/* Registers for function GPADC */ 2784#define PALMAS_GPADC_TRIM1 0x0 2785#define PALMAS_GPADC_TRIM2 0x1 2786#define PALMAS_GPADC_TRIM3 0x2 2787#define PALMAS_GPADC_TRIM4 0x3 2788#define PALMAS_GPADC_TRIM5 0x4 2789#define PALMAS_GPADC_TRIM6 0x5 2790#define PALMAS_GPADC_TRIM7 0x6 2791#define PALMAS_GPADC_TRIM8 0x7 2792#define PALMAS_GPADC_TRIM9 0x8 2793#define PALMAS_GPADC_TRIM10 0x9 2794#define PALMAS_GPADC_TRIM11 0xA 2795#define PALMAS_GPADC_TRIM12 0xB 2796#define PALMAS_GPADC_TRIM13 0xC 2797#define PALMAS_GPADC_TRIM14 0xD 2798#define PALMAS_GPADC_TRIM15 0xE 2799#define PALMAS_GPADC_TRIM16 0xF 2800 2801static inline int palmas_read(struct palmas *palmas, unsigned int base, 2802 unsigned int reg, unsigned int *val) 2803{ 2804 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 2805 int slave_id = PALMAS_BASE_TO_SLAVE(base); 2806 2807 return regmap_read(palmas->regmap[slave_id], addr, val); 2808} 2809 2810static inline int palmas_write(struct palmas *palmas, unsigned int base, 2811 unsigned int reg, unsigned int value) 2812{ 2813 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 2814 int slave_id = PALMAS_BASE_TO_SLAVE(base); 2815 2816 return regmap_write(palmas->regmap[slave_id], addr, value); 2817} 2818 2819static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base, 2820 unsigned int reg, const void *val, size_t val_count) 2821{ 2822 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 2823 int slave_id = PALMAS_BASE_TO_SLAVE(base); 2824 2825 return regmap_bulk_write(palmas->regmap[slave_id], addr, 2826 val, val_count); 2827} 2828 2829static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base, 2830 unsigned int reg, void *val, size_t val_count) 2831{ 2832 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 2833 int slave_id = PALMAS_BASE_TO_SLAVE(base); 2834 2835 return regmap_bulk_read(palmas->regmap[slave_id], addr, 2836 val, val_count); 2837} 2838 2839static inline int palmas_update_bits(struct palmas *palmas, unsigned int base, 2840 unsigned int reg, unsigned int mask, unsigned int val) 2841{ 2842 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 2843 int slave_id = PALMAS_BASE_TO_SLAVE(base); 2844 2845 return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val); 2846} 2847 2848static inline int palmas_irq_get_virq(struct palmas *palmas, int irq) 2849{ 2850 return regmap_irq_get_virq(palmas->irq_data, irq); 2851} 2852 2853#endif /* __LINUX_MFD_PALMAS_H */