tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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kernel / drivers / pinctrl / pinctrl-sunxi.c
at v3.10-rc2 2021 lines 66 kB view raw
1/* 2 * Allwinner A1X SoCs pinctrl driver. 3 * 4 * Copyright (C) 2012 Maxime Ripard 5 * 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13#include <linux/io.h> 14#include <linux/clk.h> 15#include <linux/gpio.h> 16#include <linux/module.h> 17#include <linux/of.h> 18#include <linux/of_address.h> 19#include <linux/of_device.h> 20#include <linux/pinctrl/consumer.h> 21#include <linux/pinctrl/machine.h> 22#include <linux/pinctrl/pinctrl.h> 23#include <linux/pinctrl/pinconf-generic.h> 24#include <linux/pinctrl/pinmux.h> 25#include <linux/platform_device.h> 26#include <linux/slab.h> 27 28#include "core.h" 29#include "pinctrl-sunxi.h" 30 31static const struct sunxi_desc_pin sun4i_a10_pins[] = { 32 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0, 33 SUNXI_FUNCTION(0x0, "gpio_in"), 34 SUNXI_FUNCTION(0x1, "gpio_out"), 35 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */ 36 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */ 37 SUNXI_FUNCTION(0x4, "uart2")), /* RTS */ 38 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1, 39 SUNXI_FUNCTION(0x0, "gpio_in"), 40 SUNXI_FUNCTION(0x1, "gpio_out"), 41 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */ 42 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */ 43 SUNXI_FUNCTION(0x4, "uart2")), /* CTS */ 44 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2, 45 SUNXI_FUNCTION(0x0, "gpio_in"), 46 SUNXI_FUNCTION(0x1, "gpio_out"), 47 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */ 48 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */ 49 SUNXI_FUNCTION(0x4, "uart2")), /* TX */ 50 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3, 51 SUNXI_FUNCTION(0x0, "gpio_in"), 52 SUNXI_FUNCTION(0x1, "gpio_out"), 53 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */ 54 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */ 55 SUNXI_FUNCTION(0x4, "uart2")), /* RX */ 56 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4, 57 SUNXI_FUNCTION(0x0, "gpio_in"), 58 SUNXI_FUNCTION(0x1, "gpio_out"), 59 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */ 60 SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */ 61 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5, 62 SUNXI_FUNCTION(0x0, "gpio_in"), 63 SUNXI_FUNCTION(0x1, "gpio_out"), 64 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */ 65 SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */ 66 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6, 67 SUNXI_FUNCTION(0x0, "gpio_in"), 68 SUNXI_FUNCTION(0x1, "gpio_out"), 69 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */ 70 SUNXI_FUNCTION(0x3, "spi3")), /* CLK */ 71 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7, 72 SUNXI_FUNCTION(0x0, "gpio_in"), 73 SUNXI_FUNCTION(0x1, "gpio_out"), 74 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */ 75 SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */ 76 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8, 77 SUNXI_FUNCTION(0x0, "gpio_in"), 78 SUNXI_FUNCTION(0x1, "gpio_out"), 79 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */ 80 SUNXI_FUNCTION(0x3, "spi3")), /* MISO */ 81 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9, 82 SUNXI_FUNCTION(0x0, "gpio_in"), 83 SUNXI_FUNCTION(0x1, "gpio_out"), 84 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */ 85 SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */ 86 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10, 87 SUNXI_FUNCTION(0x0, "gpio_in"), 88 SUNXI_FUNCTION(0x1, "gpio_out"), 89 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */ 90 SUNXI_FUNCTION(0x4, "uart1")), /* TX */ 91 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11, 92 SUNXI_FUNCTION(0x0, "gpio_in"), 93 SUNXI_FUNCTION(0x1, "gpio_out"), 94 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */ 95 SUNXI_FUNCTION(0x4, "uart1")), /* RX */ 96 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12, 97 SUNXI_FUNCTION(0x0, "gpio_in"), 98 SUNXI_FUNCTION(0x1, "gpio_out"), 99 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */ 100 SUNXI_FUNCTION(0x3, "uart6"), /* TX */ 101 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ 102 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13, 103 SUNXI_FUNCTION(0x0, "gpio_in"), 104 SUNXI_FUNCTION(0x1, "gpio_out"), 105 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */ 106 SUNXI_FUNCTION(0x3, "uart6"), /* RX */ 107 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ 108 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14, 109 SUNXI_FUNCTION(0x0, "gpio_in"), 110 SUNXI_FUNCTION(0x1, "gpio_out"), 111 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */ 112 SUNXI_FUNCTION(0x3, "uart7"), /* TX */ 113 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */ 114 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15, 115 SUNXI_FUNCTION(0x0, "gpio_in"), 116 SUNXI_FUNCTION(0x1, "gpio_out"), 117 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */ 118 SUNXI_FUNCTION(0x3, "uart7"), /* RX */ 119 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */ 120 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16, 121 SUNXI_FUNCTION(0x0, "gpio_in"), 122 SUNXI_FUNCTION(0x1, "gpio_out"), 123 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */ 124 SUNXI_FUNCTION(0x3, "can"), /* TX */ 125 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */ 126 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17, 127 SUNXI_FUNCTION(0x0, "gpio_in"), 128 SUNXI_FUNCTION(0x1, "gpio_out"), 129 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */ 130 SUNXI_FUNCTION(0x3, "can"), /* RX */ 131 SUNXI_FUNCTION(0x4, "uart1")), /* RING */ 132 /* Hole */ 133 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, 134 SUNXI_FUNCTION(0x0, "gpio_in"), 135 SUNXI_FUNCTION(0x1, "gpio_out"), 136 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ 137 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, 138 SUNXI_FUNCTION(0x0, "gpio_in"), 139 SUNXI_FUNCTION(0x1, "gpio_out"), 140 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ 141 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, 142 SUNXI_FUNCTION(0x0, "gpio_in"), 143 SUNXI_FUNCTION(0x1, "gpio_out"), 144 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */ 145 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, 146 SUNXI_FUNCTION(0x0, "gpio_in"), 147 SUNXI_FUNCTION(0x1, "gpio_out"), 148 SUNXI_FUNCTION(0x2, "ir0")), /* TX */ 149 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, 150 SUNXI_FUNCTION(0x0, "gpio_in"), 151 SUNXI_FUNCTION(0x1, "gpio_out"), 152 SUNXI_FUNCTION(0x2, "ir0")), /* RX */ 153 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5, 154 SUNXI_FUNCTION(0x0, "gpio_in"), 155 SUNXI_FUNCTION(0x1, "gpio_out"), 156 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */ 157 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */ 158 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6, 159 SUNXI_FUNCTION(0x0, "gpio_in"), 160 SUNXI_FUNCTION(0x1, "gpio_out"), 161 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */ 162 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */ 163 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7, 164 SUNXI_FUNCTION(0x0, "gpio_in"), 165 SUNXI_FUNCTION(0x1, "gpio_out"), 166 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */ 167 SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */ 168 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8, 169 SUNXI_FUNCTION(0x0, "gpio_in"), 170 SUNXI_FUNCTION(0x1, "gpio_out"), 171 SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */ 172 SUNXI_FUNCTION(0x3, "ac97")), /* DO */ 173 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9, 174 SUNXI_FUNCTION(0x0, "gpio_in"), 175 SUNXI_FUNCTION(0x1, "gpio_out"), 176 SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */ 177 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, 178 SUNXI_FUNCTION(0x0, "gpio_in"), 179 SUNXI_FUNCTION(0x1, "gpio_out"), 180 SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */ 181 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11, 182 SUNXI_FUNCTION(0x0, "gpio_in"), 183 SUNXI_FUNCTION(0x1, "gpio_out"), 184 SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */ 185 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12, 186 SUNXI_FUNCTION(0x0, "gpio_in"), 187 SUNXI_FUNCTION(0x1, "gpio_out"), 188 SUNXI_FUNCTION(0x2, "i2s"), /* DI */ 189 SUNXI_FUNCTION(0x3, "ac97")), /* DI */ 190 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13, 191 SUNXI_FUNCTION(0x0, "gpio_in"), 192 SUNXI_FUNCTION(0x1, "gpio_out"), 193 SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */ 194 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14, 195 SUNXI_FUNCTION(0x0, "gpio_in"), 196 SUNXI_FUNCTION(0x1, "gpio_out"), 197 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ 198 SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */ 199 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, 200 SUNXI_FUNCTION(0x0, "gpio_in"), 201 SUNXI_FUNCTION(0x1, "gpio_out"), 202 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ 203 SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */ 204 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, 205 SUNXI_FUNCTION(0x0, "gpio_in"), 206 SUNXI_FUNCTION(0x1, "gpio_out"), 207 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ 208 SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */ 209 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, 210 SUNXI_FUNCTION(0x0, "gpio_in"), 211 SUNXI_FUNCTION(0x1, "gpio_out"), 212 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ 213 SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */ 214 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, 215 SUNXI_FUNCTION(0x0, "gpio_in"), 216 SUNXI_FUNCTION(0x1, "gpio_out"), 217 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ 218 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19, 219 SUNXI_FUNCTION(0x0, "gpio_in"), 220 SUNXI_FUNCTION(0x1, "gpio_out"), 221 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ 222 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20, 223 SUNXI_FUNCTION(0x0, "gpio_in"), 224 SUNXI_FUNCTION(0x1, "gpio_out"), 225 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ 226 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21, 227 SUNXI_FUNCTION(0x0, "gpio_in"), 228 SUNXI_FUNCTION(0x1, "gpio_out"), 229 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ 230 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22, 231 SUNXI_FUNCTION(0x0, "gpio_in"), 232 SUNXI_FUNCTION(0x1, "gpio_out"), 233 SUNXI_FUNCTION(0x2, "uart0"), /* TX */ 234 SUNXI_FUNCTION(0x3, "ir1")), /* TX */ 235 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23, 236 SUNXI_FUNCTION(0x0, "gpio_in"), 237 SUNXI_FUNCTION(0x1, "gpio_out"), 238 SUNXI_FUNCTION(0x2, "uart0"), /* RX */ 239 SUNXI_FUNCTION(0x3, "ir1")), /* RX */ 240 /* Hole */ 241 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, 242 SUNXI_FUNCTION(0x0, "gpio_in"), 243 SUNXI_FUNCTION(0x1, "gpio_out"), 244 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ 245 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ 246 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, 247 SUNXI_FUNCTION(0x0, "gpio_in"), 248 SUNXI_FUNCTION(0x1, "gpio_out"), 249 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ 250 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ 251 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, 252 SUNXI_FUNCTION(0x0, "gpio_in"), 253 SUNXI_FUNCTION(0x1, "gpio_out"), 254 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ 255 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */ 256 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, 257 SUNXI_FUNCTION(0x0, "gpio_in"), 258 SUNXI_FUNCTION(0x1, "gpio_out"), 259 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */ 260 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, 261 SUNXI_FUNCTION(0x0, "gpio_in"), 262 SUNXI_FUNCTION(0x1, "gpio_out"), 263 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ 264 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, 265 SUNXI_FUNCTION(0x0, "gpio_in"), 266 SUNXI_FUNCTION(0x1, "gpio_out"), 267 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */ 268 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, 269 SUNXI_FUNCTION(0x0, "gpio_in"), 270 SUNXI_FUNCTION(0x1, "gpio_out"), 271 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ 272 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ 273 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, 274 SUNXI_FUNCTION(0x0, "gpio_in"), 275 SUNXI_FUNCTION(0x1, "gpio_out"), 276 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ 277 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ 278 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, 279 SUNXI_FUNCTION(0x0, "gpio_in"), 280 SUNXI_FUNCTION(0x1, "gpio_out"), 281 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ 282 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ 283 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, 284 SUNXI_FUNCTION(0x0, "gpio_in"), 285 SUNXI_FUNCTION(0x1, "gpio_out"), 286 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ 287 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ 288 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, 289 SUNXI_FUNCTION(0x0, "gpio_in"), 290 SUNXI_FUNCTION(0x1, "gpio_out"), 291 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ 292 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ 293 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, 294 SUNXI_FUNCTION(0x0, "gpio_in"), 295 SUNXI_FUNCTION(0x1, "gpio_out"), 296 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ 297 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ 298 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, 299 SUNXI_FUNCTION(0x0, "gpio_in"), 300 SUNXI_FUNCTION(0x1, "gpio_out"), 301 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */ 302 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, 303 SUNXI_FUNCTION(0x0, "gpio_in"), 304 SUNXI_FUNCTION(0x1, "gpio_out"), 305 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */ 306 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, 307 SUNXI_FUNCTION(0x0, "gpio_in"), 308 SUNXI_FUNCTION(0x1, "gpio_out"), 309 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */ 310 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, 311 SUNXI_FUNCTION(0x0, "gpio_in"), 312 SUNXI_FUNCTION(0x1, "gpio_out"), 313 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */ 314 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16, 315 SUNXI_FUNCTION(0x0, "gpio_in"), 316 SUNXI_FUNCTION(0x1, "gpio_out"), 317 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */ 318 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17, 319 SUNXI_FUNCTION(0x0, "gpio_in"), 320 SUNXI_FUNCTION(0x1, "gpio_out"), 321 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */ 322 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18, 323 SUNXI_FUNCTION(0x0, "gpio_in"), 324 SUNXI_FUNCTION(0x1, "gpio_out"), 325 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */ 326 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, 327 SUNXI_FUNCTION(0x0, "gpio_in"), 328 SUNXI_FUNCTION(0x1, "gpio_out"), 329 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */ 330 SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */ 331 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20, 332 SUNXI_FUNCTION(0x0, "gpio_in"), 333 SUNXI_FUNCTION(0x1, "gpio_out"), 334 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */ 335 SUNXI_FUNCTION(0x3, "spi2")), /* CLK */ 336 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21, 337 SUNXI_FUNCTION(0x0, "gpio_in"), 338 SUNXI_FUNCTION(0x1, "gpio_out"), 339 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */ 340 SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */ 341 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22, 342 SUNXI_FUNCTION(0x0, "gpio_in"), 343 SUNXI_FUNCTION(0x1, "gpio_out"), 344 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */ 345 SUNXI_FUNCTION(0x3, "spi2")), /* MISO */ 346 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23, 347 SUNXI_FUNCTION(0x0, "gpio_in"), 348 SUNXI_FUNCTION(0x1, "gpio_out"), 349 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ 350 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24, 351 SUNXI_FUNCTION(0x0, "gpio_in"), 352 SUNXI_FUNCTION(0x1, "gpio_out"), 353 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */ 354 /* Hole */ 355 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0, 356 SUNXI_FUNCTION(0x0, "gpio_in"), 357 SUNXI_FUNCTION(0x1, "gpio_out"), 358 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */ 359 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */ 360 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1, 361 SUNXI_FUNCTION(0x0, "gpio_in"), 362 SUNXI_FUNCTION(0x1, "gpio_out"), 363 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */ 364 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */ 365 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, 366 SUNXI_FUNCTION(0x0, "gpio_in"), 367 SUNXI_FUNCTION(0x1, "gpio_out"), 368 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ 369 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */ 370 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, 371 SUNXI_FUNCTION(0x0, "gpio_in"), 372 SUNXI_FUNCTION(0x1, "gpio_out"), 373 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ 374 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */ 375 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, 376 SUNXI_FUNCTION(0x0, "gpio_in"), 377 SUNXI_FUNCTION(0x1, "gpio_out"), 378 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ 379 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */ 380 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, 381 SUNXI_FUNCTION(0x0, "gpio_in"), 382 SUNXI_FUNCTION(0x1, "gpio_out"), 383 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ 384 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */ 385 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, 386 SUNXI_FUNCTION(0x0, "gpio_in"), 387 SUNXI_FUNCTION(0x1, "gpio_out"), 388 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ 389 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */ 390 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, 391 SUNXI_FUNCTION(0x0, "gpio_in"), 392 SUNXI_FUNCTION(0x1, "gpio_out"), 393 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ 394 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */ 395 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8, 396 SUNXI_FUNCTION(0x0, "gpio_in"), 397 SUNXI_FUNCTION(0x1, "gpio_out"), 398 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */ 399 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */ 400 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9, 401 SUNXI_FUNCTION(0x0, "gpio_in"), 402 SUNXI_FUNCTION(0x1, "gpio_out"), 403 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */ 404 SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */ 405 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, 406 SUNXI_FUNCTION(0x0, "gpio_in"), 407 SUNXI_FUNCTION(0x1, "gpio_out"), 408 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ 409 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */ 410 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, 411 SUNXI_FUNCTION(0x0, "gpio_in"), 412 SUNXI_FUNCTION(0x1, "gpio_out"), 413 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ 414 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */ 415 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, 416 SUNXI_FUNCTION(0x0, "gpio_in"), 417 SUNXI_FUNCTION(0x1, "gpio_out"), 418 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ 419 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */ 420 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, 421 SUNXI_FUNCTION(0x0, "gpio_in"), 422 SUNXI_FUNCTION(0x1, "gpio_out"), 423 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ 424 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */ 425 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, 426 SUNXI_FUNCTION(0x0, "gpio_in"), 427 SUNXI_FUNCTION(0x1, "gpio_out"), 428 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ 429 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */ 430 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, 431 SUNXI_FUNCTION(0x0, "gpio_in"), 432 SUNXI_FUNCTION(0x1, "gpio_out"), 433 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ 434 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */ 435 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16, 436 SUNXI_FUNCTION(0x0, "gpio_in"), 437 SUNXI_FUNCTION(0x1, "gpio_out"), 438 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */ 439 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */ 440 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17, 441 SUNXI_FUNCTION(0x0, "gpio_in"), 442 SUNXI_FUNCTION(0x1, "gpio_out"), 443 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */ 444 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */ 445 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, 446 SUNXI_FUNCTION(0x0, "gpio_in"), 447 SUNXI_FUNCTION(0x1, "gpio_out"), 448 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ 449 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */ 450 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, 451 SUNXI_FUNCTION(0x0, "gpio_in"), 452 SUNXI_FUNCTION(0x1, "gpio_out"), 453 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ 454 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */ 455 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, 456 SUNXI_FUNCTION(0x0, "gpio_in"), 457 SUNXI_FUNCTION(0x1, "gpio_out"), 458 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ 459 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */ 460 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, 461 SUNXI_FUNCTION(0x0, "gpio_in"), 462 SUNXI_FUNCTION(0x1, "gpio_out"), 463 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ 464 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */ 465 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, 466 SUNXI_FUNCTION(0x0, "gpio_in"), 467 SUNXI_FUNCTION(0x1, "gpio_out"), 468 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ 469 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */ 470 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, 471 SUNXI_FUNCTION(0x0, "gpio_in"), 472 SUNXI_FUNCTION(0x1, "gpio_out"), 473 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ 474 SUNXI_FUNCTION(0x3, "sim")), /* DET */ 475 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, 476 SUNXI_FUNCTION(0x0, "gpio_in"), 477 SUNXI_FUNCTION(0x1, "gpio_out"), 478 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ 479 SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */ 480 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, 481 SUNXI_FUNCTION(0x0, "gpio_in"), 482 SUNXI_FUNCTION(0x1, "gpio_out"), 483 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ 484 SUNXI_FUNCTION(0x3, "sim")), /* RST */ 485 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, 486 SUNXI_FUNCTION(0x0, "gpio_in"), 487 SUNXI_FUNCTION(0x1, "gpio_out"), 488 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ 489 SUNXI_FUNCTION(0x3, "sim")), /* SCK */ 490 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, 491 SUNXI_FUNCTION(0x0, "gpio_in"), 492 SUNXI_FUNCTION(0x1, "gpio_out"), 493 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ 494 SUNXI_FUNCTION(0x3, "sim")), /* SDA */ 495 /* Hole */ 496 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, 497 SUNXI_FUNCTION(0x0, "gpio_in"), 498 SUNXI_FUNCTION(0x1, "gpio_out"), 499 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */ 500 SUNXI_FUNCTION(0x3, "csi0")), /* PCK */ 501 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, 502 SUNXI_FUNCTION(0x0, "gpio_in"), 503 SUNXI_FUNCTION(0x1, "gpio_out"), 504 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */ 505 SUNXI_FUNCTION(0x3, "csi0")), /* CK */ 506 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, 507 SUNXI_FUNCTION(0x0, "gpio_in"), 508 SUNXI_FUNCTION(0x1, "gpio_out"), 509 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */ 510 SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */ 511 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, 512 SUNXI_FUNCTION(0x0, "gpio_in"), 513 SUNXI_FUNCTION(0x1, "gpio_out"), 514 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */ 515 SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */ 516 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, 517 SUNXI_FUNCTION(0x0, "gpio_in"), 518 SUNXI_FUNCTION(0x1, "gpio_out"), 519 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */ 520 SUNXI_FUNCTION(0x3, "csi0")), /* D0 */ 521 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, 522 SUNXI_FUNCTION(0x0, "gpio_in"), 523 SUNXI_FUNCTION(0x1, "gpio_out"), 524 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */ 525 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ 526 SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */ 527 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, 528 SUNXI_FUNCTION(0x0, "gpio_in"), 529 SUNXI_FUNCTION(0x1, "gpio_out"), 530 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */ 531 SUNXI_FUNCTION(0x3, "csi0")), /* D2 */ 532 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, 533 SUNXI_FUNCTION(0x0, "gpio_in"), 534 SUNXI_FUNCTION(0x1, "gpio_out"), 535 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */ 536 SUNXI_FUNCTION(0x3, "csi0")), /* D3 */ 537 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, 538 SUNXI_FUNCTION(0x0, "gpio_in"), 539 SUNXI_FUNCTION(0x1, "gpio_out"), 540 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */ 541 SUNXI_FUNCTION(0x3, "csi0")), /* D4 */ 542 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, 543 SUNXI_FUNCTION(0x0, "gpio_in"), 544 SUNXI_FUNCTION(0x1, "gpio_out"), 545 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */ 546 SUNXI_FUNCTION(0x3, "csi0")), /* D5 */ 547 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, 548 SUNXI_FUNCTION(0x0, "gpio_in"), 549 SUNXI_FUNCTION(0x1, "gpio_out"), 550 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */ 551 SUNXI_FUNCTION(0x3, "csi0")), /* D6 */ 552 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, 553 SUNXI_FUNCTION(0x0, "gpio_in"), 554 SUNXI_FUNCTION(0x1, "gpio_out"), 555 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */ 556 SUNXI_FUNCTION(0x3, "csi0")), /* D7 */ 557 /* Hole */ 558 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, 559 SUNXI_FUNCTION(0x0, "gpio_in"), 560 SUNXI_FUNCTION(0x1, "gpio_out"), 561 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ 562 SUNXI_FUNCTION(0x4, "jtag")), /* MSI */ 563 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, 564 SUNXI_FUNCTION(0x0, "gpio_in"), 565 SUNXI_FUNCTION(0x1, "gpio_out"), 566 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ 567 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */ 568 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, 569 SUNXI_FUNCTION(0x0, "gpio_in"), 570 SUNXI_FUNCTION(0x1, "gpio_out"), 571 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ 572 SUNXI_FUNCTION(0x4, "uart0")), /* TX */ 573 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, 574 SUNXI_FUNCTION(0x0, "gpio_in"), 575 SUNXI_FUNCTION(0x1, "gpio_out"), 576 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ 577 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */ 578 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, 579 SUNXI_FUNCTION(0x0, "gpio_in"), 580 SUNXI_FUNCTION(0x1, "gpio_out"), 581 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ 582 SUNXI_FUNCTION(0x4, "uart0")), /* RX */ 583 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, 584 SUNXI_FUNCTION(0x0, "gpio_in"), 585 SUNXI_FUNCTION(0x1, "gpio_out"), 586 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ 587 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */ 588 /* Hole */ 589 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, 590 SUNXI_FUNCTION(0x0, "gpio_in"), 591 SUNXI_FUNCTION(0x1, "gpio_out"), 592 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */ 593 SUNXI_FUNCTION(0x3, "csi1"), /* PCK */ 594 SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */ 595 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, 596 SUNXI_FUNCTION(0x0, "gpio_in"), 597 SUNXI_FUNCTION(0x1, "gpio_out"), 598 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */ 599 SUNXI_FUNCTION(0x3, "csi1"), /* CK */ 600 SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */ 601 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, 602 SUNXI_FUNCTION(0x0, "gpio_in"), 603 SUNXI_FUNCTION(0x1, "gpio_out"), 604 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */ 605 SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */ 606 SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */ 607 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, 608 SUNXI_FUNCTION(0x0, "gpio_in"), 609 SUNXI_FUNCTION(0x1, "gpio_out"), 610 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */ 611 SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */ 612 SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */ 613 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, 614 SUNXI_FUNCTION(0x0, "gpio_in"), 615 SUNXI_FUNCTION(0x1, "gpio_out"), 616 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */ 617 SUNXI_FUNCTION(0x3, "csi1"), /* D0 */ 618 SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */ 619 SUNXI_FUNCTION(0x5, "csi0")), /* D8 */ 620 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5, 621 SUNXI_FUNCTION(0x0, "gpio_in"), 622 SUNXI_FUNCTION(0x1, "gpio_out"), 623 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */ 624 SUNXI_FUNCTION(0x3, "csi1"), /* D1 */ 625 SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */ 626 SUNXI_FUNCTION(0x5, "csi0")), /* D9 */ 627 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6, 628 SUNXI_FUNCTION(0x0, "gpio_in"), 629 SUNXI_FUNCTION(0x1, "gpio_out"), 630 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */ 631 SUNXI_FUNCTION(0x3, "csi1"), /* D2 */ 632 SUNXI_FUNCTION(0x4, "uart3"), /* TX */ 633 SUNXI_FUNCTION(0x5, "csi0")), /* D10 */ 634 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7, 635 SUNXI_FUNCTION(0x0, "gpio_in"), 636 SUNXI_FUNCTION(0x1, "gpio_out"), 637 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */ 638 SUNXI_FUNCTION(0x3, "csi1"), /* D3 */ 639 SUNXI_FUNCTION(0x4, "uart3"), /* RX */ 640 SUNXI_FUNCTION(0x5, "csi0")), /* D11 */ 641 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8, 642 SUNXI_FUNCTION(0x0, "gpio_in"), 643 SUNXI_FUNCTION(0x1, "gpio_out"), 644 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */ 645 SUNXI_FUNCTION(0x3, "csi1"), /* D4 */ 646 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ 647 SUNXI_FUNCTION(0x5, "csi0")), /* D12 */ 648 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, 649 SUNXI_FUNCTION(0x0, "gpio_in"), 650 SUNXI_FUNCTION(0x1, "gpio_out"), 651 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */ 652 SUNXI_FUNCTION(0x3, "csi1"), /* D5 */ 653 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ 654 SUNXI_FUNCTION(0x5, "csi0")), /* D13 */ 655 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, 656 SUNXI_FUNCTION(0x0, "gpio_in"), 657 SUNXI_FUNCTION(0x1, "gpio_out"), 658 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */ 659 SUNXI_FUNCTION(0x3, "csi1"), /* D6 */ 660 SUNXI_FUNCTION(0x4, "uart4"), /* TX */ 661 SUNXI_FUNCTION(0x5, "csi0")), /* D14 */ 662 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, 663 SUNXI_FUNCTION(0x0, "gpio_in"), 664 SUNXI_FUNCTION(0x1, "gpio_out"), 665 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */ 666 SUNXI_FUNCTION(0x3, "csi1"), /* D7 */ 667 SUNXI_FUNCTION(0x4, "uart4"), /* RX */ 668 SUNXI_FUNCTION(0x5, "csi0")), /* D15 */ 669 /* Hole */ 670 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0, 671 SUNXI_FUNCTION(0x0, "gpio_in"), 672 SUNXI_FUNCTION(0x1, "gpio_out"), 673 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */ 674 SUNXI_FUNCTION(0x3, "pata"), /* ATAA0 */ 675 SUNXI_FUNCTION(0x4, "uart3"), /* TX */ 676 SUNXI_FUNCTION(0x7, "csi1")), /* D0 */ 677 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1, 678 SUNXI_FUNCTION(0x0, "gpio_in"), 679 SUNXI_FUNCTION(0x1, "gpio_out"), 680 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */ 681 SUNXI_FUNCTION(0x3, "pata"), /* ATAA1 */ 682 SUNXI_FUNCTION(0x4, "uart3"), /* RX */ 683 SUNXI_FUNCTION(0x7, "csi1")), /* D1 */ 684 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2, 685 SUNXI_FUNCTION(0x0, "gpio_in"), 686 SUNXI_FUNCTION(0x1, "gpio_out"), 687 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */ 688 SUNXI_FUNCTION(0x3, "pata"), /* ATAA2 */ 689 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ 690 SUNXI_FUNCTION(0x7, "csi1")), /* D2 */ 691 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3, 692 SUNXI_FUNCTION(0x0, "gpio_in"), 693 SUNXI_FUNCTION(0x1, "gpio_out"), 694 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */ 695 SUNXI_FUNCTION(0x3, "pata"), /* ATAIRQ */ 696 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ 697 SUNXI_FUNCTION(0x7, "csi1")), /* D3 */ 698 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4, 699 SUNXI_FUNCTION(0x0, "gpio_in"), 700 SUNXI_FUNCTION(0x1, "gpio_out"), 701 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */ 702 SUNXI_FUNCTION(0x3, "pata"), /* ATAD0 */ 703 SUNXI_FUNCTION(0x4, "uart4"), /* TX */ 704 SUNXI_FUNCTION(0x7, "csi1")), /* D4 */ 705 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5, 706 SUNXI_FUNCTION(0x0, "gpio_in"), 707 SUNXI_FUNCTION(0x1, "gpio_out"), 708 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */ 709 SUNXI_FUNCTION(0x3, "pata"), /* ATAD1 */ 710 SUNXI_FUNCTION(0x4, "uart4"), /* RX */ 711 SUNXI_FUNCTION(0x7, "csi1")), /* D5 */ 712 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6, 713 SUNXI_FUNCTION(0x0, "gpio_in"), 714 SUNXI_FUNCTION(0x1, "gpio_out"), 715 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */ 716 SUNXI_FUNCTION(0x3, "pata"), /* ATAD2 */ 717 SUNXI_FUNCTION(0x4, "uart5"), /* TX */ 718 SUNXI_FUNCTION(0x5, "ms"), /* BS */ 719 SUNXI_FUNCTION(0x7, "csi1")), /* D6 */ 720 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7, 721 SUNXI_FUNCTION(0x0, "gpio_in"), 722 SUNXI_FUNCTION(0x1, "gpio_out"), 723 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */ 724 SUNXI_FUNCTION(0x3, "pata"), /* ATAD3 */ 725 SUNXI_FUNCTION(0x4, "uart5"), /* RX */ 726 SUNXI_FUNCTION(0x5, "ms"), /* CLK */ 727 SUNXI_FUNCTION(0x7, "csi1")), /* D7 */ 728 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8, 729 SUNXI_FUNCTION(0x0, "gpio_in"), 730 SUNXI_FUNCTION(0x1, "gpio_out"), 731 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */ 732 SUNXI_FUNCTION(0x3, "pata"), /* ATAD4 */ 733 SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */ 734 SUNXI_FUNCTION(0x5, "ms"), /* D0 */ 735 SUNXI_FUNCTION(0x7, "csi1")), /* D8 */ 736 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9, 737 SUNXI_FUNCTION(0x0, "gpio_in"), 738 SUNXI_FUNCTION(0x1, "gpio_out"), 739 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */ 740 SUNXI_FUNCTION(0x3, "pata"), /* ATAD5 */ 741 SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */ 742 SUNXI_FUNCTION(0x5, "ms"), /* D1 */ 743 SUNXI_FUNCTION(0x7, "csi1")), /* D9 */ 744 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10, 745 SUNXI_FUNCTION(0x0, "gpio_in"), 746 SUNXI_FUNCTION(0x1, "gpio_out"), 747 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */ 748 SUNXI_FUNCTION(0x3, "pata"), /* ATAD6 */ 749 SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */ 750 SUNXI_FUNCTION(0x5, "ms"), /* D2 */ 751 SUNXI_FUNCTION(0x7, "csi1")), /* D10 */ 752 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11, 753 SUNXI_FUNCTION(0x0, "gpio_in"), 754 SUNXI_FUNCTION(0x1, "gpio_out"), 755 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */ 756 SUNXI_FUNCTION(0x3, "pata"), /* ATAD7 */ 757 SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */ 758 SUNXI_FUNCTION(0x5, "ms"), /* D3 */ 759 SUNXI_FUNCTION(0x7, "csi1")), /* D11 */ 760 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12, 761 SUNXI_FUNCTION(0x0, "gpio_in"), 762 SUNXI_FUNCTION(0x1, "gpio_out"), 763 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */ 764 SUNXI_FUNCTION(0x3, "pata"), /* ATAD8 */ 765 SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */ 766 SUNXI_FUNCTION(0x7, "csi1")), /* D12 */ 767 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13, 768 SUNXI_FUNCTION(0x0, "gpio_in"), 769 SUNXI_FUNCTION(0x1, "gpio_out"), 770 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */ 771 SUNXI_FUNCTION(0x3, "pata"), /* ATAD9 */ 772 SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */ 773 SUNXI_FUNCTION(0x5, "sim"), /* RST */ 774 SUNXI_FUNCTION(0x7, "csi1")), /* D13 */ 775 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14, 776 SUNXI_FUNCTION(0x0, "gpio_in"), 777 SUNXI_FUNCTION(0x1, "gpio_out"), 778 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */ 779 SUNXI_FUNCTION(0x3, "pata"), /* ATAD10 */ 780 SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */ 781 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */ 782 SUNXI_FUNCTION(0x7, "csi1")), /* D14 */ 783 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15, 784 SUNXI_FUNCTION(0x0, "gpio_in"), 785 SUNXI_FUNCTION(0x1, "gpio_out"), 786 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */ 787 SUNXI_FUNCTION(0x3, "pata"), /* ATAD11 */ 788 SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */ 789 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */ 790 SUNXI_FUNCTION(0x7, "csi1")), /* D15 */ 791 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16, 792 SUNXI_FUNCTION(0x0, "gpio_in"), 793 SUNXI_FUNCTION(0x1, "gpio_out"), 794 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */ 795 SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */ 796 SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */ 797 SUNXI_FUNCTION(0x7, "csi1")), /* D16 */ 798 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17, 799 SUNXI_FUNCTION(0x0, "gpio_in"), 800 SUNXI_FUNCTION(0x1, "gpio_out"), 801 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */ 802 SUNXI_FUNCTION(0x3, "pata"), /* ATAD13 */ 803 SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */ 804 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */ 805 SUNXI_FUNCTION(0x7, "csi1")), /* D17 */ 806 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18, 807 SUNXI_FUNCTION(0x0, "gpio_in"), 808 SUNXI_FUNCTION(0x1, "gpio_out"), 809 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */ 810 SUNXI_FUNCTION(0x3, "pata"), /* ATAD14 */ 811 SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */ 812 SUNXI_FUNCTION(0x5, "sim"), /* SCK */ 813 SUNXI_FUNCTION(0x7, "csi1")), /* D18 */ 814 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19, 815 SUNXI_FUNCTION(0x0, "gpio_in"), 816 SUNXI_FUNCTION(0x1, "gpio_out"), 817 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */ 818 SUNXI_FUNCTION(0x3, "pata"), /* ATAD15 */ 819 SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */ 820 SUNXI_FUNCTION(0x5, "sim"), /* SDA */ 821 SUNXI_FUNCTION(0x7, "csi1")), /* D19 */ 822 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20, 823 SUNXI_FUNCTION(0x0, "gpio_in"), 824 SUNXI_FUNCTION(0x1, "gpio_out"), 825 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */ 826 SUNXI_FUNCTION(0x3, "pata"), /* ATAOE */ 827 SUNXI_FUNCTION(0x4, "can"), /* TX */ 828 SUNXI_FUNCTION(0x7, "csi1")), /* D20 */ 829 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21, 830 SUNXI_FUNCTION(0x0, "gpio_in"), 831 SUNXI_FUNCTION(0x1, "gpio_out"), 832 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */ 833 SUNXI_FUNCTION(0x3, "pata"), /* ATADREQ */ 834 SUNXI_FUNCTION(0x4, "can"), /* RX */ 835 SUNXI_FUNCTION(0x7, "csi1")), /* D21 */ 836 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22, 837 SUNXI_FUNCTION(0x0, "gpio_in"), 838 SUNXI_FUNCTION(0x1, "gpio_out"), 839 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */ 840 SUNXI_FUNCTION(0x3, "pata"), /* ATADACK */ 841 SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */ 842 SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */ 843 SUNXI_FUNCTION(0x7, "csi1")), /* D22 */ 844 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23, 845 SUNXI_FUNCTION(0x0, "gpio_in"), 846 SUNXI_FUNCTION(0x1, "gpio_out"), 847 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */ 848 SUNXI_FUNCTION(0x3, "pata"), /* ATACS0 */ 849 SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */ 850 SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */ 851 SUNXI_FUNCTION(0x7, "csi1")), /* D23 */ 852 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24, 853 SUNXI_FUNCTION(0x0, "gpio_in"), 854 SUNXI_FUNCTION(0x1, "gpio_out"), 855 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */ 856 SUNXI_FUNCTION(0x3, "pata"), /* ATACS1 */ 857 SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */ 858 SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */ 859 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */ 860 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25, 861 SUNXI_FUNCTION(0x0, "gpio_in"), 862 SUNXI_FUNCTION(0x1, "gpio_out"), 863 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */ 864 SUNXI_FUNCTION(0x3, "pata"), /* ATAIORDY */ 865 SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */ 866 SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */ 867 SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */ 868 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26, 869 SUNXI_FUNCTION(0x0, "gpio_in"), 870 SUNXI_FUNCTION(0x1, "gpio_out"), 871 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */ 872 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOR */ 873 SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */ 874 SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */ 875 SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */ 876 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27, 877 SUNXI_FUNCTION(0x0, "gpio_in"), 878 SUNXI_FUNCTION(0x1, "gpio_out"), 879 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */ 880 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOW */ 881 SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */ 882 SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */ 883 SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */ 884 /* Hole */ 885 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0, 886 SUNXI_FUNCTION(0x0, "gpio_in"), 887 SUNXI_FUNCTION(0x1, "gpio_out")), 888 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1, 889 SUNXI_FUNCTION(0x0, "gpio_in"), 890 SUNXI_FUNCTION(0x1, "gpio_out")), 891 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2, 892 SUNXI_FUNCTION(0x0, "gpio_in"), 893 SUNXI_FUNCTION(0x1, "gpio_out")), 894 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3, 895 SUNXI_FUNCTION(0x0, "gpio_in"), 896 SUNXI_FUNCTION(0x1, "gpio_out"), 897 SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */ 898 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4, 899 SUNXI_FUNCTION(0x0, "gpio_in"), 900 SUNXI_FUNCTION(0x1, "gpio_out"), 901 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */ 902 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5, 903 SUNXI_FUNCTION(0x0, "gpio_in"), 904 SUNXI_FUNCTION(0x1, "gpio_out"), 905 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */ 906 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6, 907 SUNXI_FUNCTION(0x0, "gpio_in"), 908 SUNXI_FUNCTION(0x1, "gpio_out"), 909 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */ 910 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7, 911 SUNXI_FUNCTION(0x0, "gpio_in"), 912 SUNXI_FUNCTION(0x1, "gpio_out"), 913 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */ 914 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8, 915 SUNXI_FUNCTION(0x0, "gpio_in"), 916 SUNXI_FUNCTION(0x1, "gpio_out"), 917 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */ 918 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9, 919 SUNXI_FUNCTION(0x0, "gpio_in"), 920 SUNXI_FUNCTION(0x1, "gpio_out"), 921 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */ 922 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10, 923 SUNXI_FUNCTION(0x0, "gpio_in"), 924 SUNXI_FUNCTION(0x1, "gpio_out"), 925 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */ 926 SUNXI_FUNCTION(0x3, "uart5")), /* TX */ 927 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11, 928 SUNXI_FUNCTION(0x0, "gpio_in"), 929 SUNXI_FUNCTION(0x1, "gpio_out"), 930 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ 931 SUNXI_FUNCTION(0x3, "uart5")), /* RX */ 932 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12, 933 SUNXI_FUNCTION(0x0, "gpio_in"), 934 SUNXI_FUNCTION(0x1, "gpio_out"), 935 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ 936 SUNXI_FUNCTION(0x3, "uart6")), /* TX */ 937 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13, 938 SUNXI_FUNCTION(0x0, "gpio_in"), 939 SUNXI_FUNCTION(0x1, "gpio_out"), 940 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ 941 SUNXI_FUNCTION(0x3, "uart6")), /* RX */ 942 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14, 943 SUNXI_FUNCTION(0x0, "gpio_in"), 944 SUNXI_FUNCTION(0x1, "gpio_out"), 945 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */ 946 SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */ 947 SUNXI_FUNCTION(0x4, "timer4")), /* TCLKIN0 */ 948 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15, 949 SUNXI_FUNCTION(0x0, "gpio_in"), 950 SUNXI_FUNCTION(0x1, "gpio_out"), 951 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ 952 SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */ 953 SUNXI_FUNCTION(0x4, "timer5")), /* TCLKIN1 */ 954 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16, 955 SUNXI_FUNCTION(0x0, "gpio_in"), 956 SUNXI_FUNCTION(0x1, "gpio_out"), 957 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ 958 SUNXI_FUNCTION(0x3, "uart2")), /* RTS */ 959 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17, 960 SUNXI_FUNCTION(0x0, "gpio_in"), 961 SUNXI_FUNCTION(0x1, "gpio_out"), 962 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ 963 SUNXI_FUNCTION(0x3, "uart2")), /* CTS */ 964 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18, 965 SUNXI_FUNCTION(0x0, "gpio_in"), 966 SUNXI_FUNCTION(0x1, "gpio_out"), 967 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ 968 SUNXI_FUNCTION(0x3, "uart2")), /* TX */ 969 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19, 970 SUNXI_FUNCTION(0x0, "gpio_in"), 971 SUNXI_FUNCTION(0x1, "gpio_out"), 972 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ 973 SUNXI_FUNCTION(0x3, "uart2")), /* RX */ 974 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20, 975 SUNXI_FUNCTION(0x0, "gpio_in"), 976 SUNXI_FUNCTION(0x1, "gpio_out"), 977 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */ 978 SUNXI_FUNCTION(0x3, "uart7"), /* TX */ 979 SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */ 980 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21, 981 SUNXI_FUNCTION(0x0, "gpio_in"), 982 SUNXI_FUNCTION(0x1, "gpio_out"), 983 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */ 984 SUNXI_FUNCTION(0x3, "uart7"), /* RX */ 985 SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */ 986}; 987 988static const struct sunxi_desc_pin sun5i_a13_pins[] = { 989 /* Hole */ 990 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, 991 SUNXI_FUNCTION(0x0, "gpio_in"), 992 SUNXI_FUNCTION(0x1, "gpio_out"), 993 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ 994 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, 995 SUNXI_FUNCTION(0x0, "gpio_in"), 996 SUNXI_FUNCTION(0x1, "gpio_out"), 997 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ 998 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, 999 SUNXI_FUNCTION(0x0, "gpio_in"), 1000 SUNXI_FUNCTION(0x1, "gpio_out"), 1001 SUNXI_FUNCTION(0x2, "pwm")), 1002 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, 1003 SUNXI_FUNCTION(0x0, "gpio_in"), 1004 SUNXI_FUNCTION(0x1, "gpio_out"), 1005 SUNXI_FUNCTION(0x2, "ir0")), /* TX */ 1006 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, 1007 SUNXI_FUNCTION(0x0, "gpio_in"), 1008 SUNXI_FUNCTION(0x1, "gpio_out"), 1009 SUNXI_FUNCTION(0x2, "ir0")), /* RX */ 1010 /* Hole */ 1011 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, 1012 SUNXI_FUNCTION(0x0, "gpio_in"), 1013 SUNXI_FUNCTION(0x1, "gpio_out"), 1014 SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */ 1015 /* Hole */ 1016 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, 1017 SUNXI_FUNCTION(0x0, "gpio_in"), 1018 SUNXI_FUNCTION(0x1, "gpio_out"), 1019 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ 1020 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, 1021 SUNXI_FUNCTION(0x0, "gpio_in"), 1022 SUNXI_FUNCTION(0x1, "gpio_out"), 1023 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ 1024 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, 1025 SUNXI_FUNCTION(0x0, "gpio_in"), 1026 SUNXI_FUNCTION(0x1, "gpio_out"), 1027 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ 1028 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, 1029 SUNXI_FUNCTION(0x0, "gpio_in"), 1030 SUNXI_FUNCTION(0x1, "gpio_out"), 1031 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ 1032 /* Hole */ 1033 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, 1034 SUNXI_FUNCTION(0x0, "gpio_in"), 1035 SUNXI_FUNCTION(0x1, "gpio_out"), 1036 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ 1037 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ 1038 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, 1039 SUNXI_FUNCTION(0x0, "gpio_in"), 1040 SUNXI_FUNCTION(0x1, "gpio_out"), 1041 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ 1042 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ 1043 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, 1044 SUNXI_FUNCTION(0x0, "gpio_in"), 1045 SUNXI_FUNCTION(0x1, "gpio_out"), 1046 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ 1047 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ 1048 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, 1049 SUNXI_FUNCTION(0x0, "gpio_in"), 1050 SUNXI_FUNCTION(0x1, "gpio_out"), 1051 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */ 1052 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ 1053 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, 1054 SUNXI_FUNCTION(0x0, "gpio_in"), 1055 SUNXI_FUNCTION(0x1, "gpio_out"), 1056 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ 1057 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, 1058 SUNXI_FUNCTION(0x0, "gpio_in"), 1059 SUNXI_FUNCTION(0x1, "gpio_out"), 1060 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */ 1061 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, 1062 SUNXI_FUNCTION(0x0, "gpio_in"), 1063 SUNXI_FUNCTION(0x1, "gpio_out"), 1064 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ 1065 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ 1066 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, 1067 SUNXI_FUNCTION(0x0, "gpio_in"), 1068 SUNXI_FUNCTION(0x1, "gpio_out"), 1069 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ 1070 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ 1071 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, 1072 SUNXI_FUNCTION(0x0, "gpio_in"), 1073 SUNXI_FUNCTION(0x1, "gpio_out"), 1074 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ 1075 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ 1076 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, 1077 SUNXI_FUNCTION(0x0, "gpio_in"), 1078 SUNXI_FUNCTION(0x1, "gpio_out"), 1079 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ 1080 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ 1081 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, 1082 SUNXI_FUNCTION(0x0, "gpio_in"), 1083 SUNXI_FUNCTION(0x1, "gpio_out"), 1084 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ 1085 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ 1086 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, 1087 SUNXI_FUNCTION(0x0, "gpio_in"), 1088 SUNXI_FUNCTION(0x1, "gpio_out"), 1089 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ 1090 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ 1091 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, 1092 SUNXI_FUNCTION(0x0, "gpio_in"), 1093 SUNXI_FUNCTION(0x1, "gpio_out"), 1094 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */ 1095 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ 1096 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, 1097 SUNXI_FUNCTION(0x0, "gpio_in"), 1098 SUNXI_FUNCTION(0x1, "gpio_out"), 1099 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */ 1100 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ 1101 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, 1102 SUNXI_FUNCTION(0x0, "gpio_in"), 1103 SUNXI_FUNCTION(0x1, "gpio_out"), 1104 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */ 1105 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ 1106 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, 1107 SUNXI_FUNCTION(0x0, "gpio_in"), 1108 SUNXI_FUNCTION(0x1, "gpio_out"), 1109 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ 1110 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ 1111 /* Hole */ 1112 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, 1113 SUNXI_FUNCTION(0x0, "gpio_in"), 1114 SUNXI_FUNCTION(0x1, "gpio_out"), 1115 SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */ 1116 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */ 1117 /* Hole */ 1118 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, 1119 SUNXI_FUNCTION(0x0, "gpio_in"), 1120 SUNXI_FUNCTION(0x1, "gpio_out"), 1121 SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */ 1122 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, 1123 SUNXI_FUNCTION(0x0, "gpio_in"), 1124 SUNXI_FUNCTION(0x1, "gpio_out"), 1125 SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */ 1126 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, 1127 SUNXI_FUNCTION(0x0, "gpio_in"), 1128 SUNXI_FUNCTION(0x1, "gpio_out"), 1129 SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */ 1130 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, 1131 SUNXI_FUNCTION(0x0, "gpio_in"), 1132 SUNXI_FUNCTION(0x1, "gpio_out"), 1133 SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */ 1134 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, 1135 SUNXI_FUNCTION(0x0, "gpio_in"), 1136 SUNXI_FUNCTION(0x1, "gpio_out"), 1137 SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */ 1138 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, 1139 SUNXI_FUNCTION(0x0, "gpio_in"), 1140 SUNXI_FUNCTION(0x1, "gpio_out"), 1141 SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */ 1142 /* Hole */ 1143 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, 1144 SUNXI_FUNCTION(0x0, "gpio_in"), 1145 SUNXI_FUNCTION(0x1, "gpio_out"), 1146 SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */ 1147 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, 1148 SUNXI_FUNCTION(0x0, "gpio_in"), 1149 SUNXI_FUNCTION(0x1, "gpio_out"), 1150 SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */ 1151 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, 1152 SUNXI_FUNCTION(0x0, "gpio_in"), 1153 SUNXI_FUNCTION(0x1, "gpio_out"), 1154 SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */ 1155 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, 1156 SUNXI_FUNCTION(0x0, "gpio_in"), 1157 SUNXI_FUNCTION(0x1, "gpio_out"), 1158 SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */ 1159 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, 1160 SUNXI_FUNCTION(0x0, "gpio_in"), 1161 SUNXI_FUNCTION(0x1, "gpio_out"), 1162 SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */ 1163 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, 1164 SUNXI_FUNCTION(0x0, "gpio_in"), 1165 SUNXI_FUNCTION(0x1, "gpio_out"), 1166 SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */ 1167 /* Hole */ 1168 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, 1169 SUNXI_FUNCTION(0x0, "gpio_in"), 1170 SUNXI_FUNCTION(0x1, "gpio_out"), 1171 SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */ 1172 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, 1173 SUNXI_FUNCTION(0x0, "gpio_in"), 1174 SUNXI_FUNCTION(0x1, "gpio_out"), 1175 SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */ 1176 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, 1177 SUNXI_FUNCTION(0x0, "gpio_in"), 1178 SUNXI_FUNCTION(0x1, "gpio_out"), 1179 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */ 1180 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, 1181 SUNXI_FUNCTION(0x0, "gpio_in"), 1182 SUNXI_FUNCTION(0x1, "gpio_out"), 1183 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */ 1184 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, 1185 SUNXI_FUNCTION(0x0, "gpio_in"), 1186 SUNXI_FUNCTION(0x1, "gpio_out"), 1187 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */ 1188 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, 1189 SUNXI_FUNCTION(0x0, "gpio_in"), 1190 SUNXI_FUNCTION(0x1, "gpio_out"), 1191 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */ 1192 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, 1193 SUNXI_FUNCTION(0x0, "gpio_in"), 1194 SUNXI_FUNCTION(0x1, "gpio_out"), 1195 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */ 1196 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, 1197 SUNXI_FUNCTION(0x0, "gpio_in"), 1198 SUNXI_FUNCTION(0x1, "gpio_out"), 1199 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */ 1200 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, 1201 SUNXI_FUNCTION(0x0, "gpio_in"), 1202 SUNXI_FUNCTION(0x1, "gpio_out"), 1203 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */ 1204 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, 1205 SUNXI_FUNCTION(0x0, "gpio_in"), 1206 SUNXI_FUNCTION(0x1, "gpio_out"), 1207 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */ 1208 /* Hole */ 1209 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, 1210 SUNXI_FUNCTION(0x0, "gpio_in"), 1211 SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */ 1212 SUNXI_FUNCTION(0x4, "spi2")), /* CS0 */ 1213 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, 1214 SUNXI_FUNCTION(0x0, "gpio_in"), 1215 SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */ 1216 SUNXI_FUNCTION(0x4, "spi2")), /* CLK */ 1217 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, 1218 SUNXI_FUNCTION(0x0, "gpio_in"), 1219 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */ 1220 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */ 1221 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, 1222 SUNXI_FUNCTION(0x0, "gpio_in"), 1223 SUNXI_FUNCTION(0x1, "gpio_out"), 1224 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */ 1225 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */ 1226 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, 1227 SUNXI_FUNCTION(0x0, "gpio_in"), 1228 SUNXI_FUNCTION(0x1, "gpio_out"), 1229 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */ 1230 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */ 1231 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, 1232 SUNXI_FUNCTION(0x0, "gpio_in"), 1233 SUNXI_FUNCTION(0x1, "gpio_out"), 1234 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ 1235 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */ 1236 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, 1237 SUNXI_FUNCTION(0x0, "gpio_in"), 1238 SUNXI_FUNCTION(0x1, "gpio_out"), 1239 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */ 1240 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */ 1241 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, 1242 SUNXI_FUNCTION(0x0, "gpio_in"), 1243 SUNXI_FUNCTION(0x1, "gpio_out"), 1244 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */ 1245 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */ 1246 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, 1247 SUNXI_FUNCTION(0x0, "gpio_in"), 1248 SUNXI_FUNCTION(0x1, "gpio_out"), 1249 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */ 1250 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */ 1251 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, 1252 SUNXI_FUNCTION(0x0, "gpio_in"), 1253 SUNXI_FUNCTION(0x1, "gpio_out"), 1254 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */ 1255 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */ 1256 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, 1257 SUNXI_FUNCTION(0x0, "gpio_in"), 1258 SUNXI_FUNCTION(0x1, "gpio_out"), 1259 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */ 1260 SUNXI_FUNCTION(0x4, "uart1")), /* TX */ 1261 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, 1262 SUNXI_FUNCTION(0x0, "gpio_in"), 1263 SUNXI_FUNCTION(0x1, "gpio_out"), 1264 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */ 1265 SUNXI_FUNCTION(0x4, "uart1")), /* RX */ 1266 /* Hole */ 1267 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, 1268 SUNXI_FUNCTION(0x0, "gpio_in"), 1269 SUNXI_FUNCTION(0x1, "gpio_out"), 1270 SUNXI_FUNCTION(0x4, "mmc0")), /* D1 */ 1271 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, 1272 SUNXI_FUNCTION(0x0, "gpio_in"), 1273 SUNXI_FUNCTION(0x1, "gpio_out"), 1274 SUNXI_FUNCTION(0x4, "mmc0")), /* D0 */ 1275 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, 1276 SUNXI_FUNCTION(0x0, "gpio_in"), 1277 SUNXI_FUNCTION(0x1, "gpio_out"), 1278 SUNXI_FUNCTION(0x4, "mmc0")), /* CLK */ 1279 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, 1280 SUNXI_FUNCTION(0x0, "gpio_in"), 1281 SUNXI_FUNCTION(0x1, "gpio_out"), 1282 SUNXI_FUNCTION(0x4, "mmc0")), /* CMD */ 1283 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, 1284 SUNXI_FUNCTION(0x0, "gpio_in"), 1285 SUNXI_FUNCTION(0x1, "gpio_out"), 1286 SUNXI_FUNCTION(0x4, "mmc0")), /* D3 */ 1287 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, 1288 SUNXI_FUNCTION(0x0, "gpio_in"), 1289 SUNXI_FUNCTION(0x1, "gpio_out"), 1290 SUNXI_FUNCTION(0x4, "mmc0")), /* D2 */ 1291 /* Hole */ 1292 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, 1293 SUNXI_FUNCTION(0x0, "gpio_in"), 1294 SUNXI_FUNCTION(0x1, "gpio_out")), 1295 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, 1296 SUNXI_FUNCTION(0x0, "gpio_in"), 1297 SUNXI_FUNCTION(0x1, "gpio_out")), 1298 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, 1299 SUNXI_FUNCTION(0x0, "gpio_in"), 1300 SUNXI_FUNCTION(0x1, "gpio_out")), 1301 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, 1302 SUNXI_FUNCTION(0x0, "gpio_in"), 1303 SUNXI_FUNCTION(0x1, "gpio_out"), 1304 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ 1305 SUNXI_FUNCTION(0x4, "uart1")), /* TX */ 1306 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, 1307 SUNXI_FUNCTION(0x0, "gpio_in"), 1308 SUNXI_FUNCTION(0x1, "gpio_out"), 1309 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ 1310 SUNXI_FUNCTION(0x4, "uart1")), /* RX */ 1311/* Hole */ 1312 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, 1313 SUNXI_FUNCTION(0x0, "gpio_in"), 1314 SUNXI_FUNCTION(0x1, "gpio_out"), 1315 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ 1316 SUNXI_FUNCTION(0x3, "uart3")), /* TX */ 1317 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, 1318 SUNXI_FUNCTION(0x0, "gpio_in"), 1319 SUNXI_FUNCTION(0x1, "gpio_out"), 1320 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ 1321 SUNXI_FUNCTION(0x3, "uart3")), /* RX */ 1322 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, 1323 SUNXI_FUNCTION(0x0, "gpio_in"), 1324 SUNXI_FUNCTION(0x1, "gpio_out"), 1325 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ 1326 SUNXI_FUNCTION(0x3, "uart3")), /* CTS */ 1327 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12, 1328 SUNXI_FUNCTION(0x0, "gpio_in"), 1329 SUNXI_FUNCTION(0x1, "gpio_out"), 1330 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ 1331 SUNXI_FUNCTION(0x3, "uart3")), /* RTS */ 1332}; 1333 1334static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = { 1335 .pins = sun4i_a10_pins, 1336 .npins = ARRAY_SIZE(sun4i_a10_pins), 1337}; 1338 1339static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = { 1340 .pins = sun5i_a13_pins, 1341 .npins = ARRAY_SIZE(sun5i_a13_pins), 1342}; 1343 1344static struct sunxi_pinctrl_group * 1345sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) 1346{ 1347 int i; 1348 1349 for (i = 0; i < pctl->ngroups; i++) { 1350 struct sunxi_pinctrl_group *grp = pctl->groups + i; 1351 1352 if (!strcmp(grp->name, group)) 1353 return grp; 1354 } 1355 1356 return NULL; 1357} 1358 1359static struct sunxi_pinctrl_function * 1360sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl, 1361 const char *name) 1362{ 1363 struct sunxi_pinctrl_function *func = pctl->functions; 1364 int i; 1365 1366 for (i = 0; i < pctl->nfunctions; i++) { 1367 if (!func[i].name) 1368 break; 1369 1370 if (!strcmp(func[i].name, name)) 1371 return func + i; 1372 } 1373 1374 return NULL; 1375} 1376 1377static struct sunxi_desc_function * 1378sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl, 1379 const char *pin_name, 1380 const char *func_name) 1381{ 1382 int i; 1383 1384 for (i = 0; i < pctl->desc->npins; i++) { 1385 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1386 1387 if (!strcmp(pin->pin.name, pin_name)) { 1388 struct sunxi_desc_function *func = pin->functions; 1389 1390 while (func->name) { 1391 if (!strcmp(func->name, func_name)) 1392 return func; 1393 1394 func++; 1395 } 1396 } 1397 } 1398 1399 return NULL; 1400} 1401 1402static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 1403{ 1404 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1405 1406 return pctl->ngroups; 1407} 1408 1409static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev, 1410 unsigned group) 1411{ 1412 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1413 1414 return pctl->groups[group].name; 1415} 1416 1417static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 1418 unsigned group, 1419 const unsigned **pins, 1420 unsigned *num_pins) 1421{ 1422 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1423 1424 *pins = (unsigned *)&pctl->groups[group].pin; 1425 *num_pins = 1; 1426 1427 return 0; 1428} 1429 1430static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 1431 struct device_node *node, 1432 struct pinctrl_map **map, 1433 unsigned *num_maps) 1434{ 1435 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1436 unsigned long *pinconfig; 1437 struct property *prop; 1438 const char *function; 1439 const char *group; 1440 int ret, nmaps, i = 0; 1441 u32 val; 1442 1443 *map = NULL; 1444 *num_maps = 0; 1445 1446 ret = of_property_read_string(node, "allwinner,function", &function); 1447 if (ret) { 1448 dev_err(pctl->dev, 1449 "missing allwinner,function property in node %s\n", 1450 node->name); 1451 return -EINVAL; 1452 } 1453 1454 nmaps = of_property_count_strings(node, "allwinner,pins") * 2; 1455 if (nmaps < 0) { 1456 dev_err(pctl->dev, 1457 "missing allwinner,pins property in node %s\n", 1458 node->name); 1459 return -EINVAL; 1460 } 1461 1462 *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL); 1463 if (!map) 1464 return -ENOMEM; 1465 1466 of_property_for_each_string(node, "allwinner,pins", prop, group) { 1467 struct sunxi_pinctrl_group *grp = 1468 sunxi_pinctrl_find_group_by_name(pctl, group); 1469 int j = 0, configlen = 0; 1470 1471 if (!grp) { 1472 dev_err(pctl->dev, "unknown pin %s", group); 1473 continue; 1474 } 1475 1476 if (!sunxi_pinctrl_desc_find_function_by_name(pctl, 1477 grp->name, 1478 function)) { 1479 dev_err(pctl->dev, "unsupported function %s on pin %s", 1480 function, group); 1481 continue; 1482 } 1483 1484 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; 1485 (*map)[i].data.mux.group = group; 1486 (*map)[i].data.mux.function = function; 1487 1488 i++; 1489 1490 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; 1491 (*map)[i].data.configs.group_or_pin = group; 1492 1493 if (of_find_property(node, "allwinner,drive", NULL)) 1494 configlen++; 1495 if (of_find_property(node, "allwinner,pull", NULL)) 1496 configlen++; 1497 1498 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL); 1499 1500 if (!of_property_read_u32(node, "allwinner,drive", &val)) { 1501 u16 strength = (val + 1) * 10; 1502 pinconfig[j++] = 1503 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, 1504 strength); 1505 } 1506 1507 if (!of_property_read_u32(node, "allwinner,pull", &val)) { 1508 enum pin_config_param pull = PIN_CONFIG_END; 1509 if (val == 1) 1510 pull = PIN_CONFIG_BIAS_PULL_UP; 1511 else if (val == 2) 1512 pull = PIN_CONFIG_BIAS_PULL_DOWN; 1513 pinconfig[j++] = pinconf_to_config_packed(pull, 0); 1514 } 1515 1516 (*map)[i].data.configs.configs = pinconfig; 1517 (*map)[i].data.configs.num_configs = configlen; 1518 1519 i++; 1520 } 1521 1522 *num_maps = nmaps; 1523 1524 return 0; 1525} 1526 1527static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev, 1528 struct pinctrl_map *map, 1529 unsigned num_maps) 1530{ 1531 int i; 1532 1533 for (i = 0; i < num_maps; i++) { 1534 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) 1535 kfree(map[i].data.configs.configs); 1536 } 1537 1538 kfree(map); 1539} 1540 1541static const struct pinctrl_ops sunxi_pctrl_ops = { 1542 .dt_node_to_map = sunxi_pctrl_dt_node_to_map, 1543 .dt_free_map = sunxi_pctrl_dt_free_map, 1544 .get_groups_count = sunxi_pctrl_get_groups_count, 1545 .get_group_name = sunxi_pctrl_get_group_name, 1546 .get_group_pins = sunxi_pctrl_get_group_pins, 1547}; 1548 1549static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev, 1550 unsigned group, 1551 unsigned long *config) 1552{ 1553 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1554 1555 *config = pctl->groups[group].config; 1556 1557 return 0; 1558} 1559 1560static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, 1561 unsigned group, 1562 unsigned long config) 1563{ 1564 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1565 struct sunxi_pinctrl_group *g = &pctl->groups[group]; 1566 u32 val, mask; 1567 u16 strength; 1568 u8 dlevel; 1569 1570 switch (pinconf_to_config_param(config)) { 1571 case PIN_CONFIG_DRIVE_STRENGTH: 1572 strength = pinconf_to_config_argument(config); 1573 if (strength > 40) 1574 return -EINVAL; 1575 /* 1576 * We convert from mA to what the register expects: 1577 * 0: 10mA 1578 * 1: 20mA 1579 * 2: 30mA 1580 * 3: 40mA 1581 */ 1582 dlevel = strength / 10 - 1; 1583 val = readl(pctl->membase + sunxi_dlevel_reg(g->pin)); 1584 mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin); 1585 writel((val & ~mask) | dlevel << sunxi_dlevel_offset(g->pin), 1586 pctl->membase + sunxi_dlevel_reg(g->pin)); 1587 break; 1588 case PIN_CONFIG_BIAS_PULL_UP: 1589 val = readl(pctl->membase + sunxi_pull_reg(g->pin)); 1590 mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin); 1591 writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin), 1592 pctl->membase + sunxi_pull_reg(g->pin)); 1593 break; 1594 case PIN_CONFIG_BIAS_PULL_DOWN: 1595 val = readl(pctl->membase + sunxi_pull_reg(g->pin)); 1596 mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin); 1597 writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin), 1598 pctl->membase + sunxi_pull_reg(g->pin)); 1599 break; 1600 default: 1601 break; 1602 } 1603 1604 /* cache the config value */ 1605 g->config = config; 1606 1607 return 0; 1608} 1609 1610static const struct pinconf_ops sunxi_pconf_ops = { 1611 .pin_config_group_get = sunxi_pconf_group_get, 1612 .pin_config_group_set = sunxi_pconf_group_set, 1613}; 1614 1615static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 1616{ 1617 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1618 1619 return pctl->nfunctions; 1620} 1621 1622static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev, 1623 unsigned function) 1624{ 1625 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1626 1627 return pctl->functions[function].name; 1628} 1629 1630static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev, 1631 unsigned function, 1632 const char * const **groups, 1633 unsigned * const num_groups) 1634{ 1635 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1636 1637 *groups = pctl->functions[function].groups; 1638 *num_groups = pctl->functions[function].ngroups; 1639 1640 return 0; 1641} 1642 1643static void sunxi_pmx_set(struct pinctrl_dev *pctldev, 1644 unsigned pin, 1645 u8 config) 1646{ 1647 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1648 1649 u32 val = readl(pctl->membase + sunxi_mux_reg(pin)); 1650 u32 mask = MUX_PINS_MASK << sunxi_mux_offset(pin); 1651 writel((val & ~mask) | config << sunxi_mux_offset(pin), 1652 pctl->membase + sunxi_mux_reg(pin)); 1653} 1654 1655static int sunxi_pmx_enable(struct pinctrl_dev *pctldev, 1656 unsigned function, 1657 unsigned group) 1658{ 1659 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1660 struct sunxi_pinctrl_group *g = pctl->groups + group; 1661 struct sunxi_pinctrl_function *func = pctl->functions + function; 1662 struct sunxi_desc_function *desc = 1663 sunxi_pinctrl_desc_find_function_by_name(pctl, 1664 g->name, 1665 func->name); 1666 1667 if (!desc) 1668 return -EINVAL; 1669 1670 sunxi_pmx_set(pctldev, g->pin, desc->muxval); 1671 1672 return 0; 1673} 1674 1675static int 1676sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 1677 struct pinctrl_gpio_range *range, 1678 unsigned offset, 1679 bool input) 1680{ 1681 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1682 struct sunxi_desc_function *desc; 1683 char pin_name[SUNXI_PIN_NAME_MAX_LEN]; 1684 const char *func; 1685 u8 bank, pin; 1686 int ret; 1687 1688 bank = (offset) / PINS_PER_BANK; 1689 pin = (offset) % PINS_PER_BANK; 1690 1691 ret = sprintf(pin_name, "P%c%d", 'A' + bank, pin); 1692 if (!ret) 1693 goto error; 1694 1695 if (input) 1696 func = "gpio_in"; 1697 else 1698 func = "gpio_out"; 1699 1700 desc = sunxi_pinctrl_desc_find_function_by_name(pctl, 1701 pin_name, 1702 func); 1703 if (!desc) { 1704 ret = -EINVAL; 1705 goto error; 1706 } 1707 1708 sunxi_pmx_set(pctldev, offset, desc->muxval); 1709 1710 ret = 0; 1711 1712error: 1713 return ret; 1714} 1715 1716static const struct pinmux_ops sunxi_pmx_ops = { 1717 .get_functions_count = sunxi_pmx_get_funcs_cnt, 1718 .get_function_name = sunxi_pmx_get_func_name, 1719 .get_function_groups = sunxi_pmx_get_func_groups, 1720 .enable = sunxi_pmx_enable, 1721 .gpio_set_direction = sunxi_pmx_gpio_set_direction, 1722}; 1723 1724static struct pinctrl_desc sunxi_pctrl_desc = { 1725 .confops = &sunxi_pconf_ops, 1726 .pctlops = &sunxi_pctrl_ops, 1727 .pmxops = &sunxi_pmx_ops, 1728}; 1729 1730static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset) 1731{ 1732 return pinctrl_request_gpio(chip->base + offset); 1733} 1734 1735static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset) 1736{ 1737 pinctrl_free_gpio(chip->base + offset); 1738} 1739 1740static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip, 1741 unsigned offset) 1742{ 1743 return pinctrl_gpio_direction_input(chip->base + offset); 1744} 1745 1746static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) 1747{ 1748 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); 1749 1750 u32 reg = sunxi_data_reg(offset); 1751 u8 index = sunxi_data_offset(offset); 1752 u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; 1753 1754 return val; 1755} 1756 1757static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip, 1758 unsigned offset, int value) 1759{ 1760 return pinctrl_gpio_direction_output(chip->base + offset); 1761} 1762 1763static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, 1764 unsigned offset, int value) 1765{ 1766 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); 1767 u32 reg = sunxi_data_reg(offset); 1768 u8 index = sunxi_data_offset(offset); 1769 1770 writel((value & DATA_PINS_MASK) << index, pctl->membase + reg); 1771} 1772 1773static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, 1774 const struct of_phandle_args *gpiospec, 1775 u32 *flags) 1776{ 1777 int pin, base; 1778 1779 base = PINS_PER_BANK * gpiospec->args[0]; 1780 pin = base + gpiospec->args[1]; 1781 1782 if (pin > (gc->base + gc->ngpio)) 1783 return -EINVAL; 1784 1785 if (flags) 1786 *flags = gpiospec->args[2]; 1787 1788 return pin; 1789} 1790 1791static struct gpio_chip sunxi_pinctrl_gpio_chip = { 1792 .owner = THIS_MODULE, 1793 .request = sunxi_pinctrl_gpio_request, 1794 .free = sunxi_pinctrl_gpio_free, 1795 .direction_input = sunxi_pinctrl_gpio_direction_input, 1796 .direction_output = sunxi_pinctrl_gpio_direction_output, 1797 .get = sunxi_pinctrl_gpio_get, 1798 .set = sunxi_pinctrl_gpio_set, 1799 .of_xlate = sunxi_pinctrl_gpio_of_xlate, 1800 .of_gpio_n_cells = 3, 1801 .can_sleep = 0, 1802}; 1803 1804static struct of_device_id sunxi_pinctrl_match[] = { 1805 { .compatible = "allwinner,sun4i-a10-pinctrl", .data = (void *)&sun4i_a10_pinctrl_data }, 1806 { .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data }, 1807 {} 1808}; 1809MODULE_DEVICE_TABLE(of, sunxi_pinctrl_match); 1810 1811static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, 1812 const char *name) 1813{ 1814 struct sunxi_pinctrl_function *func = pctl->functions; 1815 1816 while (func->name) { 1817 /* function already there */ 1818 if (strcmp(func->name, name) == 0) { 1819 func->ngroups++; 1820 return -EEXIST; 1821 } 1822 func++; 1823 } 1824 1825 func->name = name; 1826 func->ngroups = 1; 1827 1828 pctl->nfunctions++; 1829 1830 return 0; 1831} 1832 1833static int sunxi_pinctrl_build_state(struct platform_device *pdev) 1834{ 1835 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev); 1836 int i; 1837 1838 pctl->ngroups = pctl->desc->npins; 1839 1840 /* Allocate groups */ 1841 pctl->groups = devm_kzalloc(&pdev->dev, 1842 pctl->ngroups * sizeof(*pctl->groups), 1843 GFP_KERNEL); 1844 if (!pctl->groups) 1845 return -ENOMEM; 1846 1847 for (i = 0; i < pctl->desc->npins; i++) { 1848 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1849 struct sunxi_pinctrl_group *group = pctl->groups + i; 1850 1851 group->name = pin->pin.name; 1852 group->pin = pin->pin.number; 1853 } 1854 1855 /* 1856 * We suppose that we won't have any more functions than pins, 1857 * we'll reallocate that later anyway 1858 */ 1859 pctl->functions = devm_kzalloc(&pdev->dev, 1860 pctl->desc->npins * sizeof(*pctl->functions), 1861 GFP_KERNEL); 1862 if (!pctl->functions) 1863 return -ENOMEM; 1864 1865 /* Count functions and their associated groups */ 1866 for (i = 0; i < pctl->desc->npins; i++) { 1867 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1868 struct sunxi_desc_function *func = pin->functions; 1869 1870 while (func->name) { 1871 sunxi_pinctrl_add_function(pctl, func->name); 1872 func++; 1873 } 1874 } 1875 1876 pctl->functions = krealloc(pctl->functions, 1877 pctl->nfunctions * sizeof(*pctl->functions), 1878 GFP_KERNEL); 1879 1880 for (i = 0; i < pctl->desc->npins; i++) { 1881 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1882 struct sunxi_desc_function *func = pin->functions; 1883 1884 while (func->name) { 1885 struct sunxi_pinctrl_function *func_item; 1886 const char **func_grp; 1887 1888 func_item = sunxi_pinctrl_find_function_by_name(pctl, 1889 func->name); 1890 if (!func_item) 1891 return -EINVAL; 1892 1893 if (!func_item->groups) { 1894 func_item->groups = 1895 devm_kzalloc(&pdev->dev, 1896 func_item->ngroups * sizeof(*func_item->groups), 1897 GFP_KERNEL); 1898 if (!func_item->groups) 1899 return -ENOMEM; 1900 } 1901 1902 func_grp = func_item->groups; 1903 while (*func_grp) 1904 func_grp++; 1905 1906 *func_grp = pin->pin.name; 1907 func++; 1908 } 1909 } 1910 1911 return 0; 1912} 1913 1914static int sunxi_pinctrl_probe(struct platform_device *pdev) 1915{ 1916 struct device_node *node = pdev->dev.of_node; 1917 const struct of_device_id *device; 1918 struct pinctrl_pin_desc *pins; 1919 struct sunxi_pinctrl *pctl; 1920 int i, ret, last_pin; 1921 struct clk *clk; 1922 1923 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); 1924 if (!pctl) 1925 return -ENOMEM; 1926 platform_set_drvdata(pdev, pctl); 1927 1928 pctl->membase = of_iomap(node, 0); 1929 if (!pctl->membase) 1930 return -ENOMEM; 1931 1932 device = of_match_device(sunxi_pinctrl_match, &pdev->dev); 1933 if (!device) 1934 return -ENODEV; 1935 1936 pctl->desc = (struct sunxi_pinctrl_desc *)device->data; 1937 1938 ret = sunxi_pinctrl_build_state(pdev); 1939 if (ret) { 1940 dev_err(&pdev->dev, "dt probe failed: %d\n", ret); 1941 return ret; 1942 } 1943 1944 pins = devm_kzalloc(&pdev->dev, 1945 pctl->desc->npins * sizeof(*pins), 1946 GFP_KERNEL); 1947 if (!pins) 1948 return -ENOMEM; 1949 1950 for (i = 0; i < pctl->desc->npins; i++) 1951 pins[i] = pctl->desc->pins[i].pin; 1952 1953 sunxi_pctrl_desc.name = dev_name(&pdev->dev); 1954 sunxi_pctrl_desc.owner = THIS_MODULE; 1955 sunxi_pctrl_desc.pins = pins; 1956 sunxi_pctrl_desc.npins = pctl->desc->npins; 1957 pctl->dev = &pdev->dev; 1958 pctl->pctl_dev = pinctrl_register(&sunxi_pctrl_desc, 1959 &pdev->dev, pctl); 1960 if (!pctl->pctl_dev) { 1961 dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); 1962 return -EINVAL; 1963 } 1964 1965 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); 1966 if (!pctl->chip) { 1967 ret = -ENOMEM; 1968 goto pinctrl_error; 1969 } 1970 1971 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; 1972 pctl->chip = &sunxi_pinctrl_gpio_chip; 1973 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK); 1974 pctl->chip->label = dev_name(&pdev->dev); 1975 pctl->chip->dev = &pdev->dev; 1976 pctl->chip->base = 0; 1977 1978 ret = gpiochip_add(pctl->chip); 1979 if (ret) 1980 goto pinctrl_error; 1981 1982 for (i = 0; i < pctl->desc->npins; i++) { 1983 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1984 1985 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 1986 pin->pin.number, 1987 pin->pin.number, 1); 1988 if (ret) 1989 goto gpiochip_error; 1990 } 1991 1992 clk = devm_clk_get(&pdev->dev, NULL); 1993 if (IS_ERR(clk)) 1994 goto gpiochip_error; 1995 1996 clk_prepare_enable(clk); 1997 1998 dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); 1999 2000 return 0; 2001 2002gpiochip_error: 2003 ret = gpiochip_remove(pctl->chip); 2004pinctrl_error: 2005 pinctrl_unregister(pctl->pctl_dev); 2006 return ret; 2007} 2008 2009static struct platform_driver sunxi_pinctrl_driver = { 2010 .probe = sunxi_pinctrl_probe, 2011 .driver = { 2012 .name = "sunxi-pinctrl", 2013 .owner = THIS_MODULE, 2014 .of_match_table = sunxi_pinctrl_match, 2015 }, 2016}; 2017module_platform_driver(sunxi_pinctrl_driver); 2018 2019MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com"); 2020MODULE_DESCRIPTION("Allwinner A1X pinctrl driver"); 2021MODULE_LICENSE("GPL");