tjh.dev / kernel
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kernel / drivers / gpu / drm / radeon / radeon_asic.h
at v3.10-rc2 554 lines 26 kB view raw
1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28#ifndef __RADEON_ASIC_H__ 29#define __RADEON_ASIC_H__ 30 31/* 32 * common functions 33 */ 34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); 35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 36uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); 37void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 38 39uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); 40void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 41uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); 42void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); 43void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 44 45void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 46u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder); 47void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 48u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder); 49 50 51/* 52 * r100,rv100,rs100,rv200,rs200 53 */ 54struct r100_mc_save { 55 u32 GENMO_WT; 56 u32 CRTC_EXT_CNTL; 57 u32 CRTC_GEN_CNTL; 58 u32 CRTC2_GEN_CNTL; 59 u32 CUR_OFFSET; 60 u32 CUR2_OFFSET; 61}; 62int r100_init(struct radeon_device *rdev); 63void r100_fini(struct radeon_device *rdev); 64int r100_suspend(struct radeon_device *rdev); 65int r100_resume(struct radeon_device *rdev); 66void r100_vga_set_state(struct radeon_device *rdev, bool state); 67bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 68int r100_asic_reset(struct radeon_device *rdev); 69u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); 70void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 71int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 72void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 73int r100_irq_set(struct radeon_device *rdev); 74int r100_irq_process(struct radeon_device *rdev); 75void r100_fence_ring_emit(struct radeon_device *rdev, 76 struct radeon_fence *fence); 77void r100_semaphore_ring_emit(struct radeon_device *rdev, 78 struct radeon_ring *cp, 79 struct radeon_semaphore *semaphore, 80 bool emit_wait); 81int r100_cs_parse(struct radeon_cs_parser *p); 82void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 83uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); 84int r100_copy_blit(struct radeon_device *rdev, 85 uint64_t src_offset, 86 uint64_t dst_offset, 87 unsigned num_gpu_pages, 88 struct radeon_fence **fence); 89int r100_set_surface_reg(struct radeon_device *rdev, int reg, 90 uint32_t tiling_flags, uint32_t pitch, 91 uint32_t offset, uint32_t obj_size); 92void r100_clear_surface_reg(struct radeon_device *rdev, int reg); 93void r100_bandwidth_update(struct radeon_device *rdev); 94void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 95int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 96void r100_hpd_init(struct radeon_device *rdev); 97void r100_hpd_fini(struct radeon_device *rdev); 98bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 99void r100_hpd_set_polarity(struct radeon_device *rdev, 100 enum radeon_hpd_id hpd); 101int r100_debugfs_rbbm_init(struct radeon_device *rdev); 102int r100_debugfs_cp_init(struct radeon_device *rdev); 103void r100_cp_disable(struct radeon_device *rdev); 104int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 105void r100_cp_fini(struct radeon_device *rdev); 106int r100_pci_gart_init(struct radeon_device *rdev); 107void r100_pci_gart_fini(struct radeon_device *rdev); 108int r100_pci_gart_enable(struct radeon_device *rdev); 109void r100_pci_gart_disable(struct radeon_device *rdev); 110int r100_debugfs_mc_info_init(struct radeon_device *rdev); 111int r100_gui_wait_for_idle(struct radeon_device *rdev); 112int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 113void r100_irq_disable(struct radeon_device *rdev); 114void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); 115void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); 116void r100_vram_init_sizes(struct radeon_device *rdev); 117int r100_cp_reset(struct radeon_device *rdev); 118void r100_vga_render_disable(struct radeon_device *rdev); 119void r100_restore_sanity(struct radeon_device *rdev); 120int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 121 struct radeon_cs_packet *pkt, 122 struct radeon_bo *robj); 123int r100_cs_parse_packet0(struct radeon_cs_parser *p, 124 struct radeon_cs_packet *pkt, 125 const unsigned *auth, unsigned n, 126 radeon_packet0_check_t check); 127int r100_cs_packet_parse(struct radeon_cs_parser *p, 128 struct radeon_cs_packet *pkt, 129 unsigned idx); 130void r100_enable_bm(struct radeon_device *rdev); 131void r100_set_common_regs(struct radeon_device *rdev); 132void r100_bm_disable(struct radeon_device *rdev); 133extern bool r100_gui_idle(struct radeon_device *rdev); 134extern void r100_pm_misc(struct radeon_device *rdev); 135extern void r100_pm_prepare(struct radeon_device *rdev); 136extern void r100_pm_finish(struct radeon_device *rdev); 137extern void r100_pm_init_profile(struct radeon_device *rdev); 138extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); 139extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc); 140extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 141extern void r100_post_page_flip(struct radeon_device *rdev, int crtc); 142extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); 143extern int r100_mc_wait_for_idle(struct radeon_device *rdev); 144 145/* 146 * r200,rv250,rs300,rv280 147 */ 148extern int r200_copy_dma(struct radeon_device *rdev, 149 uint64_t src_offset, 150 uint64_t dst_offset, 151 unsigned num_gpu_pages, 152 struct radeon_fence **fence); 153void r200_set_safe_registers(struct radeon_device *rdev); 154 155/* 156 * r300,r350,rv350,rv380 157 */ 158extern int r300_init(struct radeon_device *rdev); 159extern void r300_fini(struct radeon_device *rdev); 160extern int r300_suspend(struct radeon_device *rdev); 161extern int r300_resume(struct radeon_device *rdev); 162extern int r300_asic_reset(struct radeon_device *rdev); 163extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 164extern void r300_fence_ring_emit(struct radeon_device *rdev, 165 struct radeon_fence *fence); 166extern int r300_cs_parse(struct radeon_cs_parser *p); 167extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); 168extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 169extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); 170extern int rv370_get_pcie_lanes(struct radeon_device *rdev); 171extern void r300_set_reg_safe(struct radeon_device *rdev); 172extern void r300_mc_program(struct radeon_device *rdev); 173extern void r300_mc_init(struct radeon_device *rdev); 174extern void r300_clock_startup(struct radeon_device *rdev); 175extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 176extern int rv370_pcie_gart_init(struct radeon_device *rdev); 177extern void rv370_pcie_gart_fini(struct radeon_device *rdev); 178extern int rv370_pcie_gart_enable(struct radeon_device *rdev); 179extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 180extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 181 182/* 183 * r420,r423,rv410 184 */ 185extern int r420_init(struct radeon_device *rdev); 186extern void r420_fini(struct radeon_device *rdev); 187extern int r420_suspend(struct radeon_device *rdev); 188extern int r420_resume(struct radeon_device *rdev); 189extern void r420_pm_init_profile(struct radeon_device *rdev); 190extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 191extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 192extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 193extern void r420_pipes_init(struct radeon_device *rdev); 194 195/* 196 * rs400,rs480 197 */ 198extern int rs400_init(struct radeon_device *rdev); 199extern void rs400_fini(struct radeon_device *rdev); 200extern int rs400_suspend(struct radeon_device *rdev); 201extern int rs400_resume(struct radeon_device *rdev); 202void rs400_gart_tlb_flush(struct radeon_device *rdev); 203int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 204uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); 205void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 206int rs400_gart_init(struct radeon_device *rdev); 207int rs400_gart_enable(struct radeon_device *rdev); 208void rs400_gart_adjust_size(struct radeon_device *rdev); 209void rs400_gart_disable(struct radeon_device *rdev); 210void rs400_gart_fini(struct radeon_device *rdev); 211extern int rs400_mc_wait_for_idle(struct radeon_device *rdev); 212 213/* 214 * rs600. 215 */ 216extern int rs600_asic_reset(struct radeon_device *rdev); 217extern int rs600_init(struct radeon_device *rdev); 218extern void rs600_fini(struct radeon_device *rdev); 219extern int rs600_suspend(struct radeon_device *rdev); 220extern int rs600_resume(struct radeon_device *rdev); 221int rs600_irq_set(struct radeon_device *rdev); 222int rs600_irq_process(struct radeon_device *rdev); 223void rs600_irq_disable(struct radeon_device *rdev); 224u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); 225void rs600_gart_tlb_flush(struct radeon_device *rdev); 226int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 227uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); 228void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 229void rs600_bandwidth_update(struct radeon_device *rdev); 230void rs600_hpd_init(struct radeon_device *rdev); 231void rs600_hpd_fini(struct radeon_device *rdev); 232bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 233void rs600_hpd_set_polarity(struct radeon_device *rdev, 234 enum radeon_hpd_id hpd); 235extern void rs600_pm_misc(struct radeon_device *rdev); 236extern void rs600_pm_prepare(struct radeon_device *rdev); 237extern void rs600_pm_finish(struct radeon_device *rdev); 238extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc); 239extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 240extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc); 241void rs600_set_safe_registers(struct radeon_device *rdev); 242extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc); 243extern int rs600_mc_wait_for_idle(struct radeon_device *rdev); 244 245/* 246 * rs690,rs740 247 */ 248int rs690_init(struct radeon_device *rdev); 249void rs690_fini(struct radeon_device *rdev); 250int rs690_resume(struct radeon_device *rdev); 251int rs690_suspend(struct radeon_device *rdev); 252uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); 253void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 254void rs690_bandwidth_update(struct radeon_device *rdev); 255void rs690_line_buffer_adjust(struct radeon_device *rdev, 256 struct drm_display_mode *mode1, 257 struct drm_display_mode *mode2); 258extern int rs690_mc_wait_for_idle(struct radeon_device *rdev); 259 260/* 261 * rv515 262 */ 263struct rv515_mc_save { 264 u32 vga_render_control; 265 u32 vga_hdp_control; 266 bool crtc_enabled[2]; 267}; 268 269int rv515_init(struct radeon_device *rdev); 270void rv515_fini(struct radeon_device *rdev); 271uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); 272void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 273void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 274void rv515_bandwidth_update(struct radeon_device *rdev); 275int rv515_resume(struct radeon_device *rdev); 276int rv515_suspend(struct radeon_device *rdev); 277void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 278void rv515_vga_render_disable(struct radeon_device *rdev); 279void rv515_set_safe_registers(struct radeon_device *rdev); 280void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); 281void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); 282void rv515_clock_startup(struct radeon_device *rdev); 283void rv515_debugfs(struct radeon_device *rdev); 284int rv515_mc_wait_for_idle(struct radeon_device *rdev); 285 286/* 287 * r520,rv530,rv560,rv570,r580 288 */ 289int r520_init(struct radeon_device *rdev); 290int r520_resume(struct radeon_device *rdev); 291int r520_mc_wait_for_idle(struct radeon_device *rdev); 292 293/* 294 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 295 */ 296int r600_init(struct radeon_device *rdev); 297void r600_fini(struct radeon_device *rdev); 298int r600_suspend(struct radeon_device *rdev); 299int r600_resume(struct radeon_device *rdev); 300void r600_vga_set_state(struct radeon_device *rdev, bool state); 301int r600_wb_init(struct radeon_device *rdev); 302void r600_wb_fini(struct radeon_device *rdev); 303void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 304uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 305void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 306int r600_cs_parse(struct radeon_cs_parser *p); 307int r600_dma_cs_parse(struct radeon_cs_parser *p); 308void r600_fence_ring_emit(struct radeon_device *rdev, 309 struct radeon_fence *fence); 310void r600_semaphore_ring_emit(struct radeon_device *rdev, 311 struct radeon_ring *cp, 312 struct radeon_semaphore *semaphore, 313 bool emit_wait); 314void r600_dma_fence_ring_emit(struct radeon_device *rdev, 315 struct radeon_fence *fence); 316void r600_dma_semaphore_ring_emit(struct radeon_device *rdev, 317 struct radeon_ring *ring, 318 struct radeon_semaphore *semaphore, 319 bool emit_wait); 320void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 321bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 322bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 323int r600_asic_reset(struct radeon_device *rdev); 324int r600_set_surface_reg(struct radeon_device *rdev, int reg, 325 uint32_t tiling_flags, uint32_t pitch, 326 uint32_t offset, uint32_t obj_size); 327void r600_clear_surface_reg(struct radeon_device *rdev, int reg); 328int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 329int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 330void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 331int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 332int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 333int r600_uvd_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 334int r600_copy_blit(struct radeon_device *rdev, 335 uint64_t src_offset, uint64_t dst_offset, 336 unsigned num_gpu_pages, struct radeon_fence **fence); 337int r600_copy_dma(struct radeon_device *rdev, 338 uint64_t src_offset, uint64_t dst_offset, 339 unsigned num_gpu_pages, struct radeon_fence **fence); 340void r600_hpd_init(struct radeon_device *rdev); 341void r600_hpd_fini(struct radeon_device *rdev); 342bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 343void r600_hpd_set_polarity(struct radeon_device *rdev, 344 enum radeon_hpd_id hpd); 345extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo); 346extern bool r600_gui_idle(struct radeon_device *rdev); 347extern void r600_pm_misc(struct radeon_device *rdev); 348extern void r600_pm_init_profile(struct radeon_device *rdev); 349extern void rs780_pm_init_profile(struct radeon_device *rdev); 350extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); 351extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); 352extern int r600_get_pcie_lanes(struct radeon_device *rdev); 353bool r600_card_posted(struct radeon_device *rdev); 354void r600_cp_stop(struct radeon_device *rdev); 355int r600_cp_start(struct radeon_device *rdev); 356void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); 357int r600_cp_resume(struct radeon_device *rdev); 358void r600_cp_fini(struct radeon_device *rdev); 359int r600_count_pipe_bits(uint32_t val); 360int r600_mc_wait_for_idle(struct radeon_device *rdev); 361int r600_pcie_gart_init(struct radeon_device *rdev); 362void r600_scratch_init(struct radeon_device *rdev); 363int r600_blit_init(struct radeon_device *rdev); 364void r600_blit_fini(struct radeon_device *rdev); 365int r600_init_microcode(struct radeon_device *rdev); 366/* r600 irq */ 367int r600_irq_process(struct radeon_device *rdev); 368int r600_irq_init(struct radeon_device *rdev); 369void r600_irq_fini(struct radeon_device *rdev); 370void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 371int r600_irq_set(struct radeon_device *rdev); 372void r600_irq_suspend(struct radeon_device *rdev); 373void r600_disable_interrupts(struct radeon_device *rdev); 374void r600_rlc_stop(struct radeon_device *rdev); 375/* r600 audio */ 376int r600_audio_init(struct radeon_device *rdev); 377struct r600_audio r600_audio_status(struct radeon_device *rdev); 378void r600_audio_fini(struct radeon_device *rdev); 379int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); 380void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); 381void r600_hdmi_enable(struct drm_encoder *encoder, bool enable); 382void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 383/* r600 blit */ 384int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages, 385 struct radeon_fence **fence, struct radeon_sa_bo **vb, 386 struct radeon_semaphore **sem); 387void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence, 388 struct radeon_sa_bo *vb, struct radeon_semaphore *sem); 389void r600_kms_blit_copy(struct radeon_device *rdev, 390 u64 src_gpu_addr, u64 dst_gpu_addr, 391 unsigned num_gpu_pages, 392 struct radeon_sa_bo *vb); 393int r600_mc_wait_for_idle(struct radeon_device *rdev); 394u32 r600_get_xclk(struct radeon_device *rdev); 395uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev); 396 397/* uvd */ 398int r600_uvd_init(struct radeon_device *rdev); 399int r600_uvd_rbc_start(struct radeon_device *rdev); 400void r600_uvd_rbc_stop(struct radeon_device *rdev); 401int r600_uvd_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 402void r600_uvd_fence_emit(struct radeon_device *rdev, 403 struct radeon_fence *fence); 404void r600_uvd_semaphore_emit(struct radeon_device *rdev, 405 struct radeon_ring *ring, 406 struct radeon_semaphore *semaphore, 407 bool emit_wait); 408void r600_uvd_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 409 410/* 411 * rv770,rv730,rv710,rv740 412 */ 413int rv770_init(struct radeon_device *rdev); 414void rv770_fini(struct radeon_device *rdev); 415int rv770_suspend(struct radeon_device *rdev); 416int rv770_resume(struct radeon_device *rdev); 417void rv770_pm_misc(struct radeon_device *rdev); 418u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 419void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 420void r700_cp_stop(struct radeon_device *rdev); 421void r700_cp_fini(struct radeon_device *rdev); 422int rv770_copy_dma(struct radeon_device *rdev, 423 uint64_t src_offset, uint64_t dst_offset, 424 unsigned num_gpu_pages, 425 struct radeon_fence **fence); 426u32 rv770_get_xclk(struct radeon_device *rdev); 427int rv770_uvd_resume(struct radeon_device *rdev); 428int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 429 430/* 431 * evergreen 432 */ 433struct evergreen_mc_save { 434 u32 vga_render_control; 435 u32 vga_hdp_control; 436 bool crtc_enabled[RADEON_MAX_CRTCS]; 437}; 438 439void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); 440int evergreen_init(struct radeon_device *rdev); 441void evergreen_fini(struct radeon_device *rdev); 442int evergreen_suspend(struct radeon_device *rdev); 443int evergreen_resume(struct radeon_device *rdev); 444bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 445bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 446int evergreen_asic_reset(struct radeon_device *rdev); 447void evergreen_bandwidth_update(struct radeon_device *rdev); 448void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 449void evergreen_hpd_init(struct radeon_device *rdev); 450void evergreen_hpd_fini(struct radeon_device *rdev); 451bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 452void evergreen_hpd_set_polarity(struct radeon_device *rdev, 453 enum radeon_hpd_id hpd); 454u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); 455int evergreen_irq_set(struct radeon_device *rdev); 456int evergreen_irq_process(struct radeon_device *rdev); 457extern int evergreen_cs_parse(struct radeon_cs_parser *p); 458extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p); 459extern void evergreen_pm_misc(struct radeon_device *rdev); 460extern void evergreen_pm_prepare(struct radeon_device *rdev); 461extern void evergreen_pm_finish(struct radeon_device *rdev); 462extern void sumo_pm_init_profile(struct radeon_device *rdev); 463extern void btc_pm_init_profile(struct radeon_device *rdev); 464int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 465int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 466extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc); 467extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 468extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); 469extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); 470void evergreen_disable_interrupt_state(struct radeon_device *rdev); 471int evergreen_blit_init(struct radeon_device *rdev); 472int evergreen_mc_wait_for_idle(struct radeon_device *rdev); 473void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, 474 struct radeon_fence *fence); 475void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, 476 struct radeon_ib *ib); 477int evergreen_copy_dma(struct radeon_device *rdev, 478 uint64_t src_offset, uint64_t dst_offset, 479 unsigned num_gpu_pages, 480 struct radeon_fence **fence); 481void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable); 482void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 483 484/* 485 * cayman 486 */ 487void cayman_fence_ring_emit(struct radeon_device *rdev, 488 struct radeon_fence *fence); 489void cayman_uvd_semaphore_emit(struct radeon_device *rdev, 490 struct radeon_ring *ring, 491 struct radeon_semaphore *semaphore, 492 bool emit_wait); 493void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); 494int cayman_init(struct radeon_device *rdev); 495void cayman_fini(struct radeon_device *rdev); 496int cayman_suspend(struct radeon_device *rdev); 497int cayman_resume(struct radeon_device *rdev); 498int cayman_asic_reset(struct radeon_device *rdev); 499void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 500int cayman_vm_init(struct radeon_device *rdev); 501void cayman_vm_fini(struct radeon_device *rdev); 502void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 503uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); 504void cayman_vm_set_page(struct radeon_device *rdev, 505 struct radeon_ib *ib, 506 uint64_t pe, 507 uint64_t addr, unsigned count, 508 uint32_t incr, uint32_t flags); 509int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 510int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 511void cayman_dma_ring_ib_execute(struct radeon_device *rdev, 512 struct radeon_ib *ib); 513bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 514bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 515void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 516 517/* DCE6 - SI */ 518void dce6_bandwidth_update(struct radeon_device *rdev); 519 520/* 521 * si 522 */ 523void si_fence_ring_emit(struct radeon_device *rdev, 524 struct radeon_fence *fence); 525void si_pcie_gart_tlb_flush(struct radeon_device *rdev); 526int si_init(struct radeon_device *rdev); 527void si_fini(struct radeon_device *rdev); 528int si_suspend(struct radeon_device *rdev); 529int si_resume(struct radeon_device *rdev); 530bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 531bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 532int si_asic_reset(struct radeon_device *rdev); 533void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 534int si_irq_set(struct radeon_device *rdev); 535int si_irq_process(struct radeon_device *rdev); 536int si_vm_init(struct radeon_device *rdev); 537void si_vm_fini(struct radeon_device *rdev); 538void si_vm_set_page(struct radeon_device *rdev, 539 struct radeon_ib *ib, 540 uint64_t pe, 541 uint64_t addr, unsigned count, 542 uint32_t incr, uint32_t flags); 543void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 544int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 545int si_copy_dma(struct radeon_device *rdev, 546 uint64_t src_offset, uint64_t dst_offset, 547 unsigned num_gpu_pages, 548 struct radeon_fence **fence); 549void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 550u32 si_get_xclk(struct radeon_device *rdev); 551uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev); 552int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 553 554#endif