tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * Device Tree Include file for Marvell Armada 370 family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 *
14 * Contains definitions specific to the Armada 370 SoC that are not
15 * common to all Armada SoCs.
16 */
17
18/include/ "armada-370-xp.dtsi"
19/include/ "skeleton.dtsi"
20
21/ {
22 model = "Marvell Armada 370 family SoC";
23 compatible = "marvell,armada370", "marvell,armada-370-xp";
24
25 aliases {
26 gpio0 = &gpio0;
27 gpio1 = &gpio1;
28 gpio2 = &gpio2;
29 };
30
31 soc {
32 ranges = <0 0xd0000000 0x100000>;
33 internal-regs {
34 system-controller@18200 {
35 compatible = "marvell,armada-370-xp-system-controller";
36 reg = <0x18200 0x100>;
37 };
38
39 L2: l2-cache {
40 compatible = "marvell,aurora-outer-cache";
41 reg = <0xd0008000 0x1000>;
42 cache-id-part = <0x100>;
43 wt-override;
44 };
45
46 mpic: interrupt-controller@20000 {
47 reg = <0x20a00 0x1d0>, <0x21870 0x58>;
48 };
49
50 pinctrl {
51 compatible = "marvell,mv88f6710-pinctrl";
52 reg = <0x18000 0x38>;
53
54 sdio_pins1: sdio-pins1 {
55 marvell,pins = "mpp9", "mpp11", "mpp12",
56 "mpp13", "mpp14", "mpp15";
57 marvell,function = "sd0";
58 };
59
60 sdio_pins2: sdio-pins2 {
61 marvell,pins = "mpp47", "mpp48", "mpp49",
62 "mpp50", "mpp51", "mpp52";
63 marvell,function = "sd0";
64 };
65
66 sdio_pins3: sdio-pins3 {
67 marvell,pins = "mpp48", "mpp49", "mpp50",
68 "mpp51", "mpp52", "mpp53";
69 marvell,function = "sd0";
70 };
71 };
72
73 gpio0: gpio@18100 {
74 compatible = "marvell,orion-gpio";
75 reg = <0x18100 0x40>;
76 ngpios = <32>;
77 gpio-controller;
78 #gpio-cells = <2>;
79 interrupt-controller;
80 #interrupts-cells = <2>;
81 interrupts = <82>, <83>, <84>, <85>;
82 };
83
84 gpio1: gpio@18140 {
85 compatible = "marvell,orion-gpio";
86 reg = <0x18140 0x40>;
87 ngpios = <32>;
88 gpio-controller;
89 #gpio-cells = <2>;
90 interrupt-controller;
91 #interrupts-cells = <2>;
92 interrupts = <87>, <88>, <89>, <90>;
93 };
94
95 gpio2: gpio@18180 {
96 compatible = "marvell,orion-gpio";
97 reg = <0x18180 0x40>;
98 ngpios = <2>;
99 gpio-controller;
100 #gpio-cells = <2>;
101 interrupt-controller;
102 #interrupts-cells = <2>;
103 interrupts = <91>;
104 };
105
106 coreclk: mvebu-sar@18230 {
107 compatible = "marvell,armada-370-core-clock";
108 reg = <0x18230 0x08>;
109 #clock-cells = <1>;
110 };
111
112 gateclk: clock-gating-control@18220 {
113 compatible = "marvell,armada-370-gating-clock";
114 reg = <0x18220 0x4>;
115 clocks = <&coreclk 0>;
116 #clock-cells = <1>;
117 };
118
119 xor@60800 {
120 compatible = "marvell,orion-xor";
121 reg = <0x60800 0x100
122 0x60A00 0x100>;
123 status = "okay";
124
125 xor00 {
126 interrupts = <51>;
127 dmacap,memcpy;
128 dmacap,xor;
129 };
130 xor01 {
131 interrupts = <52>;
132 dmacap,memcpy;
133 dmacap,xor;
134 dmacap,memset;
135 };
136 };
137
138 xor@60900 {
139 compatible = "marvell,orion-xor";
140 reg = <0x60900 0x100
141 0x60b00 0x100>;
142 status = "okay";
143
144 xor10 {
145 interrupts = <94>;
146 dmacap,memcpy;
147 dmacap,xor;
148 };
149 xor11 {
150 interrupts = <95>;
151 dmacap,memcpy;
152 dmacap,xor;
153 dmacap,memset;
154 };
155 };
156
157 usb@50000 {
158 clocks = <&coreclk 0>;
159 };
160
161 usb@51000 {
162 clocks = <&coreclk 0>;
163 };
164
165 thermal@18300 {
166 compatible = "marvell,armada370-thermal";
167 reg = <0x18300 0x4
168 0x18304 0x4>;
169 status = "okay";
170 };
171
172 pcie-controller {
173 compatible = "marvell,armada-370-pcie";
174 status = "disabled";
175 device_type = "pci";
176
177 #address-cells = <3>;
178 #size-cells = <2>;
179
180 bus-range = <0x00 0xff>;
181
182 reg = <0x40000 0x2000>, <0x80000 0x2000>;
183
184 reg-names = "pcie0.0", "pcie1.0";
185
186 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
187 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
188 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
189 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
190
191 pcie@1,0 {
192 device_type = "pci";
193 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
194 reg = <0x0800 0 0 0 0>;
195 #address-cells = <3>;
196 #size-cells = <2>;
197 #interrupt-cells = <1>;
198 ranges;
199 interrupt-map-mask = <0 0 0 0>;
200 interrupt-map = <0 0 0 0 &mpic 58>;
201 marvell,pcie-port = <0>;
202 marvell,pcie-lane = <0>;
203 clocks = <&gateclk 5>;
204 status = "disabled";
205 };
206
207 pcie@2,0 {
208 device_type = "pci";
209 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
210 reg = <0x1000 0 0 0 0>;
211 #address-cells = <3>;
212 #size-cells = <2>;
213 #interrupt-cells = <1>;
214 ranges;
215 interrupt-map-mask = <0 0 0 0>;
216 interrupt-map = <0 0 0 0 &mpic 62>;
217 marvell,pcie-port = <1>;
218 marvell,pcie-lane = <0>;
219 clocks = <&gateclk 9>;
220 status = "disabled";
221 };
222 };
223 };
224 };
225};