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1/* 2 * Handles the Intel 27x USB Device Controller (UDC) 3 * 4 * Inspired by original driver by Frank Becker, David Brownell, and others. 5 * Copyright (C) 2008 Robert Jarzmik 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 * 21 */ 22#include <linux/module.h> 23#include <linux/kernel.h> 24#include <linux/types.h> 25#include <linux/errno.h> 26#include <linux/platform_device.h> 27#include <linux/delay.h> 28#include <linux/list.h> 29#include <linux/interrupt.h> 30#include <linux/proc_fs.h> 31#include <linux/clk.h> 32#include <linux/irq.h> 33#include <linux/gpio.h> 34#include <linux/slab.h> 35#include <linux/prefetch.h> 36 37#include <asm/byteorder.h> 38#include <mach/hardware.h> 39 40#include <linux/usb.h> 41#include <linux/usb/ch9.h> 42#include <linux/usb/gadget.h> 43#include <mach/udc.h> 44 45#include "pxa27x_udc.h" 46 47/* 48 * This driver handles the USB Device Controller (UDC) in Intel's PXA 27x 49 * series processors. 50 * 51 * Such controller drivers work with a gadget driver. The gadget driver 52 * returns descriptors, implements configuration and data protocols used 53 * by the host to interact with this device, and allocates endpoints to 54 * the different protocol interfaces. The controller driver virtualizes 55 * usb hardware so that the gadget drivers will be more portable. 56 * 57 * This UDC hardware wants to implement a bit too much USB protocol. The 58 * biggest issues are: that the endpoints have to be set up before the 59 * controller can be enabled (minor, and not uncommon); and each endpoint 60 * can only have one configuration, interface and alternative interface 61 * number (major, and very unusual). Once set up, these cannot be changed 62 * without a controller reset. 63 * 64 * The workaround is to setup all combinations necessary for the gadgets which 65 * will work with this driver. This is done in pxa_udc structure, statically. 66 * See pxa_udc, udc_usb_ep versus pxa_ep, and matching function find_pxa_ep. 67 * (You could modify this if needed. Some drivers have a "fifo_mode" module 68 * parameter to facilitate such changes.) 69 * 70 * The combinations have been tested with these gadgets : 71 * - zero gadget 72 * - file storage gadget 73 * - ether gadget 74 * 75 * The driver doesn't use DMA, only IO access and IRQ callbacks. No use is 76 * made of UDC's double buffering either. USB "On-The-Go" is not implemented. 77 * 78 * All the requests are handled the same way : 79 * - the drivers tries to handle the request directly to the IO 80 * - if the IO fifo is not big enough, the remaining is send/received in 81 * interrupt handling. 82 */ 83 84#define DRIVER_VERSION "2008-04-18" 85#define DRIVER_DESC "PXA 27x USB Device Controller driver" 86 87static const char driver_name[] = "pxa27x_udc"; 88static struct pxa_udc *the_controller; 89 90static void handle_ep(struct pxa_ep *ep); 91 92/* 93 * Debug filesystem 94 */ 95#ifdef CONFIG_USB_GADGET_DEBUG_FS 96 97#include <linux/debugfs.h> 98#include <linux/uaccess.h> 99#include <linux/seq_file.h> 100 101static int state_dbg_show(struct seq_file *s, void *p) 102{ 103 struct pxa_udc *udc = s->private; 104 int pos = 0, ret; 105 u32 tmp; 106 107 ret = -ENODEV; 108 if (!udc->driver) 109 goto out; 110 111 /* basic device status */ 112 pos += seq_printf(s, DRIVER_DESC "\n" 113 "%s version: %s\nGadget driver: %s\n", 114 driver_name, DRIVER_VERSION, 115 udc->driver ? udc->driver->driver.name : "(none)"); 116 117 tmp = udc_readl(udc, UDCCR); 118 pos += seq_printf(s, 119 "udccr=0x%0x(%s%s%s%s%s%s%s%s%s%s), " 120 "con=%d,inter=%d,altinter=%d\n", tmp, 121 (tmp & UDCCR_OEN) ? " oen":"", 122 (tmp & UDCCR_AALTHNP) ? " aalthnp":"", 123 (tmp & UDCCR_AHNP) ? " rem" : "", 124 (tmp & UDCCR_BHNP) ? " rstir" : "", 125 (tmp & UDCCR_DWRE) ? " dwre" : "", 126 (tmp & UDCCR_SMAC) ? " smac" : "", 127 (tmp & UDCCR_EMCE) ? " emce" : "", 128 (tmp & UDCCR_UDR) ? " udr" : "", 129 (tmp & UDCCR_UDA) ? " uda" : "", 130 (tmp & UDCCR_UDE) ? " ude" : "", 131 (tmp & UDCCR_ACN) >> UDCCR_ACN_S, 132 (tmp & UDCCR_AIN) >> UDCCR_AIN_S, 133 (tmp & UDCCR_AAISN) >> UDCCR_AAISN_S); 134 /* registers for device and ep0 */ 135 pos += seq_printf(s, "udcicr0=0x%08x udcicr1=0x%08x\n", 136 udc_readl(udc, UDCICR0), udc_readl(udc, UDCICR1)); 137 pos += seq_printf(s, "udcisr0=0x%08x udcisr1=0x%08x\n", 138 udc_readl(udc, UDCISR0), udc_readl(udc, UDCISR1)); 139 pos += seq_printf(s, "udcfnr=%d\n", udc_readl(udc, UDCFNR)); 140 pos += seq_printf(s, "irqs: reset=%lu, suspend=%lu, resume=%lu, " 141 "reconfig=%lu\n", 142 udc->stats.irqs_reset, udc->stats.irqs_suspend, 143 udc->stats.irqs_resume, udc->stats.irqs_reconfig); 144 145 ret = 0; 146out: 147 return ret; 148} 149 150static int queues_dbg_show(struct seq_file *s, void *p) 151{ 152 struct pxa_udc *udc = s->private; 153 struct pxa_ep *ep; 154 struct pxa27x_request *req; 155 int pos = 0, i, maxpkt, ret; 156 157 ret = -ENODEV; 158 if (!udc->driver) 159 goto out; 160 161 /* dump endpoint queues */ 162 for (i = 0; i < NR_PXA_ENDPOINTS; i++) { 163 ep = &udc->pxa_ep[i]; 164 maxpkt = ep->fifo_size; 165 pos += seq_printf(s, "%-12s max_pkt=%d %s\n", 166 EPNAME(ep), maxpkt, "pio"); 167 168 if (list_empty(&ep->queue)) { 169 pos += seq_printf(s, "\t(nothing queued)\n"); 170 continue; 171 } 172 173 list_for_each_entry(req, &ep->queue, queue) { 174 pos += seq_printf(s, "\treq %p len %d/%d buf %p\n", 175 &req->req, req->req.actual, 176 req->req.length, req->req.buf); 177 } 178 } 179 180 ret = 0; 181out: 182 return ret; 183} 184 185static int eps_dbg_show(struct seq_file *s, void *p) 186{ 187 struct pxa_udc *udc = s->private; 188 struct pxa_ep *ep; 189 int pos = 0, i, ret; 190 u32 tmp; 191 192 ret = -ENODEV; 193 if (!udc->driver) 194 goto out; 195 196 ep = &udc->pxa_ep[0]; 197 tmp = udc_ep_readl(ep, UDCCSR); 198 pos += seq_printf(s, "udccsr0=0x%03x(%s%s%s%s%s%s%s)\n", tmp, 199 (tmp & UDCCSR0_SA) ? " sa" : "", 200 (tmp & UDCCSR0_RNE) ? " rne" : "", 201 (tmp & UDCCSR0_FST) ? " fst" : "", 202 (tmp & UDCCSR0_SST) ? " sst" : "", 203 (tmp & UDCCSR0_DME) ? " dme" : "", 204 (tmp & UDCCSR0_IPR) ? " ipr" : "", 205 (tmp & UDCCSR0_OPC) ? " opc" : ""); 206 for (i = 0; i < NR_PXA_ENDPOINTS; i++) { 207 ep = &udc->pxa_ep[i]; 208 tmp = i? udc_ep_readl(ep, UDCCR) : udc_readl(udc, UDCCR); 209 pos += seq_printf(s, "%-12s: " 210 "IN %lu(%lu reqs), OUT %lu(%lu reqs), " 211 "irqs=%lu, udccr=0x%08x, udccsr=0x%03x, " 212 "udcbcr=%d\n", 213 EPNAME(ep), 214 ep->stats.in_bytes, ep->stats.in_ops, 215 ep->stats.out_bytes, ep->stats.out_ops, 216 ep->stats.irqs, 217 tmp, udc_ep_readl(ep, UDCCSR), 218 udc_ep_readl(ep, UDCBCR)); 219 } 220 221 ret = 0; 222out: 223 return ret; 224} 225 226static int eps_dbg_open(struct inode *inode, struct file *file) 227{ 228 return single_open(file, eps_dbg_show, inode->i_private); 229} 230 231static int queues_dbg_open(struct inode *inode, struct file *file) 232{ 233 return single_open(file, queues_dbg_show, inode->i_private); 234} 235 236static int state_dbg_open(struct inode *inode, struct file *file) 237{ 238 return single_open(file, state_dbg_show, inode->i_private); 239} 240 241static const struct file_operations state_dbg_fops = { 242 .owner = THIS_MODULE, 243 .open = state_dbg_open, 244 .llseek = seq_lseek, 245 .read = seq_read, 246 .release = single_release, 247}; 248 249static const struct file_operations queues_dbg_fops = { 250 .owner = THIS_MODULE, 251 .open = queues_dbg_open, 252 .llseek = seq_lseek, 253 .read = seq_read, 254 .release = single_release, 255}; 256 257static const struct file_operations eps_dbg_fops = { 258 .owner = THIS_MODULE, 259 .open = eps_dbg_open, 260 .llseek = seq_lseek, 261 .read = seq_read, 262 .release = single_release, 263}; 264 265static void pxa_init_debugfs(struct pxa_udc *udc) 266{ 267 struct dentry *root, *state, *queues, *eps; 268 269 root = debugfs_create_dir(udc->gadget.name, NULL); 270 if (IS_ERR(root) || !root) 271 goto err_root; 272 273 state = debugfs_create_file("udcstate", 0400, root, udc, 274 &state_dbg_fops); 275 if (!state) 276 goto err_state; 277 queues = debugfs_create_file("queues", 0400, root, udc, 278 &queues_dbg_fops); 279 if (!queues) 280 goto err_queues; 281 eps = debugfs_create_file("epstate", 0400, root, udc, 282 &eps_dbg_fops); 283 if (!eps) 284 goto err_eps; 285 286 udc->debugfs_root = root; 287 udc->debugfs_state = state; 288 udc->debugfs_queues = queues; 289 udc->debugfs_eps = eps; 290 return; 291err_eps: 292 debugfs_remove(eps); 293err_queues: 294 debugfs_remove(queues); 295err_state: 296 debugfs_remove(root); 297err_root: 298 dev_err(udc->dev, "debugfs is not available\n"); 299} 300 301static void pxa_cleanup_debugfs(struct pxa_udc *udc) 302{ 303 debugfs_remove(udc->debugfs_eps); 304 debugfs_remove(udc->debugfs_queues); 305 debugfs_remove(udc->debugfs_state); 306 debugfs_remove(udc->debugfs_root); 307 udc->debugfs_eps = NULL; 308 udc->debugfs_queues = NULL; 309 udc->debugfs_state = NULL; 310 udc->debugfs_root = NULL; 311} 312 313#else 314static inline void pxa_init_debugfs(struct pxa_udc *udc) 315{ 316} 317 318static inline void pxa_cleanup_debugfs(struct pxa_udc *udc) 319{ 320} 321#endif 322 323/** 324 * is_match_usb_pxa - check if usb_ep and pxa_ep match 325 * @udc_usb_ep: usb endpoint 326 * @ep: pxa endpoint 327 * @config: configuration required in pxa_ep 328 * @interface: interface required in pxa_ep 329 * @altsetting: altsetting required in pxa_ep 330 * 331 * Returns 1 if all criteria match between pxa and usb endpoint, 0 otherwise 332 */ 333static int is_match_usb_pxa(struct udc_usb_ep *udc_usb_ep, struct pxa_ep *ep, 334 int config, int interface, int altsetting) 335{ 336 if (usb_endpoint_num(&udc_usb_ep->desc) != ep->addr) 337 return 0; 338 if (usb_endpoint_dir_in(&udc_usb_ep->desc) != ep->dir_in) 339 return 0; 340 if (usb_endpoint_type(&udc_usb_ep->desc) != ep->type) 341 return 0; 342 if ((ep->config != config) || (ep->interface != interface) 343 || (ep->alternate != altsetting)) 344 return 0; 345 return 1; 346} 347 348/** 349 * find_pxa_ep - find pxa_ep structure matching udc_usb_ep 350 * @udc: pxa udc 351 * @udc_usb_ep: udc_usb_ep structure 352 * 353 * Match udc_usb_ep and all pxa_ep available, to see if one matches. 354 * This is necessary because of the strong pxa hardware restriction requiring 355 * that once pxa endpoints are initialized, their configuration is freezed, and 356 * no change can be made to their address, direction, or in which configuration, 357 * interface or altsetting they are active ... which differs from more usual 358 * models which have endpoints be roughly just addressable fifos, and leave 359 * configuration events up to gadget drivers (like all control messages). 360 * 361 * Note that there is still a blurred point here : 362 * - we rely on UDCCR register "active interface" and "active altsetting". 363 * This is a nonsense in regard of USB spec, where multiple interfaces are 364 * active at the same time. 365 * - if we knew for sure that the pxa can handle multiple interface at the 366 * same time, assuming Intel's Developer Guide is wrong, this function 367 * should be reviewed, and a cache of couples (iface, altsetting) should 368 * be kept in the pxa_udc structure. In this case this function would match 369 * against the cache of couples instead of the "last altsetting" set up. 370 * 371 * Returns the matched pxa_ep structure or NULL if none found 372 */ 373static struct pxa_ep *find_pxa_ep(struct pxa_udc *udc, 374 struct udc_usb_ep *udc_usb_ep) 375{ 376 int i; 377 struct pxa_ep *ep; 378 int cfg = udc->config; 379 int iface = udc->last_interface; 380 int alt = udc->last_alternate; 381 382 if (udc_usb_ep == &udc->udc_usb_ep[0]) 383 return &udc->pxa_ep[0]; 384 385 for (i = 1; i < NR_PXA_ENDPOINTS; i++) { 386 ep = &udc->pxa_ep[i]; 387 if (is_match_usb_pxa(udc_usb_ep, ep, cfg, iface, alt)) 388 return ep; 389 } 390 return NULL; 391} 392 393/** 394 * update_pxa_ep_matches - update pxa_ep cached values in all udc_usb_ep 395 * @udc: pxa udc 396 * 397 * Context: in_interrupt() 398 * 399 * Updates all pxa_ep fields in udc_usb_ep structures, if this field was 400 * previously set up (and is not NULL). The update is necessary is a 401 * configuration change or altsetting change was issued by the USB host. 402 */ 403static void update_pxa_ep_matches(struct pxa_udc *udc) 404{ 405 int i; 406 struct udc_usb_ep *udc_usb_ep; 407 408 for (i = 1; i < NR_USB_ENDPOINTS; i++) { 409 udc_usb_ep = &udc->udc_usb_ep[i]; 410 if (udc_usb_ep->pxa_ep) 411 udc_usb_ep->pxa_ep = find_pxa_ep(udc, udc_usb_ep); 412 } 413} 414 415/** 416 * pio_irq_enable - Enables irq generation for one endpoint 417 * @ep: udc endpoint 418 */ 419static void pio_irq_enable(struct pxa_ep *ep) 420{ 421 struct pxa_udc *udc = ep->dev; 422 int index = EPIDX(ep); 423 u32 udcicr0 = udc_readl(udc, UDCICR0); 424 u32 udcicr1 = udc_readl(udc, UDCICR1); 425 426 if (index < 16) 427 udc_writel(udc, UDCICR0, udcicr0 | (3 << (index * 2))); 428 else 429 udc_writel(udc, UDCICR1, udcicr1 | (3 << ((index - 16) * 2))); 430} 431 432/** 433 * pio_irq_disable - Disables irq generation for one endpoint 434 * @ep: udc endpoint 435 */ 436static void pio_irq_disable(struct pxa_ep *ep) 437{ 438 struct pxa_udc *udc = ep->dev; 439 int index = EPIDX(ep); 440 u32 udcicr0 = udc_readl(udc, UDCICR0); 441 u32 udcicr1 = udc_readl(udc, UDCICR1); 442 443 if (index < 16) 444 udc_writel(udc, UDCICR0, udcicr0 & ~(3 << (index * 2))); 445 else 446 udc_writel(udc, UDCICR1, udcicr1 & ~(3 << ((index - 16) * 2))); 447} 448 449/** 450 * udc_set_mask_UDCCR - set bits in UDCCR 451 * @udc: udc device 452 * @mask: bits to set in UDCCR 453 * 454 * Sets bits in UDCCR, leaving DME and FST bits as they were. 455 */ 456static inline void udc_set_mask_UDCCR(struct pxa_udc *udc, int mask) 457{ 458 u32 udccr = udc_readl(udc, UDCCR); 459 udc_writel(udc, UDCCR, 460 (udccr & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS)); 461} 462 463/** 464 * udc_clear_mask_UDCCR - clears bits in UDCCR 465 * @udc: udc device 466 * @mask: bit to clear in UDCCR 467 * 468 * Clears bits in UDCCR, leaving DME and FST bits as they were. 469 */ 470static inline void udc_clear_mask_UDCCR(struct pxa_udc *udc, int mask) 471{ 472 u32 udccr = udc_readl(udc, UDCCR); 473 udc_writel(udc, UDCCR, 474 (udccr & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS)); 475} 476 477/** 478 * ep_write_UDCCSR - set bits in UDCCSR 479 * @udc: udc device 480 * @mask: bits to set in UDCCR 481 * 482 * Sets bits in UDCCSR (UDCCSR0 and UDCCSR*). 483 * 484 * A specific case is applied to ep0 : the ACM bit is always set to 1, for 485 * SET_INTERFACE and SET_CONFIGURATION. 486 */ 487static inline void ep_write_UDCCSR(struct pxa_ep *ep, int mask) 488{ 489 if (is_ep0(ep)) 490 mask |= UDCCSR0_ACM; 491 udc_ep_writel(ep, UDCCSR, mask); 492} 493 494/** 495 * ep_count_bytes_remain - get how many bytes in udc endpoint 496 * @ep: udc endpoint 497 * 498 * Returns number of bytes in OUT fifos. Broken for IN fifos (-EOPNOTSUPP) 499 */ 500static int ep_count_bytes_remain(struct pxa_ep *ep) 501{ 502 if (ep->dir_in) 503 return -EOPNOTSUPP; 504 return udc_ep_readl(ep, UDCBCR) & 0x3ff; 505} 506 507/** 508 * ep_is_empty - checks if ep has byte ready for reading 509 * @ep: udc endpoint 510 * 511 * If endpoint is the control endpoint, checks if there are bytes in the 512 * control endpoint fifo. If endpoint is a data endpoint, checks if bytes 513 * are ready for reading on OUT endpoint. 514 * 515 * Returns 0 if ep not empty, 1 if ep empty, -EOPNOTSUPP if IN endpoint 516 */ 517static int ep_is_empty(struct pxa_ep *ep) 518{ 519 int ret; 520 521 if (!is_ep0(ep) && ep->dir_in) 522 return -EOPNOTSUPP; 523 if (is_ep0(ep)) 524 ret = !(udc_ep_readl(ep, UDCCSR) & UDCCSR0_RNE); 525 else 526 ret = !(udc_ep_readl(ep, UDCCSR) & UDCCSR_BNE); 527 return ret; 528} 529 530/** 531 * ep_is_full - checks if ep has place to write bytes 532 * @ep: udc endpoint 533 * 534 * If endpoint is not the control endpoint and is an IN endpoint, checks if 535 * there is place to write bytes into the endpoint. 536 * 537 * Returns 0 if ep not full, 1 if ep full, -EOPNOTSUPP if OUT endpoint 538 */ 539static int ep_is_full(struct pxa_ep *ep) 540{ 541 if (is_ep0(ep)) 542 return (udc_ep_readl(ep, UDCCSR) & UDCCSR0_IPR); 543 if (!ep->dir_in) 544 return -EOPNOTSUPP; 545 return (!(udc_ep_readl(ep, UDCCSR) & UDCCSR_BNF)); 546} 547 548/** 549 * epout_has_pkt - checks if OUT endpoint fifo has a packet available 550 * @ep: pxa endpoint 551 * 552 * Returns 1 if a complete packet is available, 0 if not, -EOPNOTSUPP for IN ep. 553 */ 554static int epout_has_pkt(struct pxa_ep *ep) 555{ 556 if (!is_ep0(ep) && ep->dir_in) 557 return -EOPNOTSUPP; 558 if (is_ep0(ep)) 559 return (udc_ep_readl(ep, UDCCSR) & UDCCSR0_OPC); 560 return (udc_ep_readl(ep, UDCCSR) & UDCCSR_PC); 561} 562 563/** 564 * set_ep0state - Set ep0 automata state 565 * @dev: udc device 566 * @state: state 567 */ 568static void set_ep0state(struct pxa_udc *udc, int state) 569{ 570 struct pxa_ep *ep = &udc->pxa_ep[0]; 571 char *old_stname = EP0_STNAME(udc); 572 573 udc->ep0state = state; 574 ep_dbg(ep, "state=%s->%s, udccsr0=0x%03x, udcbcr=%d\n", old_stname, 575 EP0_STNAME(udc), udc_ep_readl(ep, UDCCSR), 576 udc_ep_readl(ep, UDCBCR)); 577} 578 579/** 580 * ep0_idle - Put control endpoint into idle state 581 * @dev: udc device 582 */ 583static void ep0_idle(struct pxa_udc *dev) 584{ 585 set_ep0state(dev, WAIT_FOR_SETUP); 586} 587 588/** 589 * inc_ep_stats_reqs - Update ep stats counts 590 * @ep: physical endpoint 591 * @req: usb request 592 * @is_in: ep direction (USB_DIR_IN or 0) 593 * 594 */ 595static void inc_ep_stats_reqs(struct pxa_ep *ep, int is_in) 596{ 597 if (is_in) 598 ep->stats.in_ops++; 599 else 600 ep->stats.out_ops++; 601} 602 603/** 604 * inc_ep_stats_bytes - Update ep stats counts 605 * @ep: physical endpoint 606 * @count: bytes transferred on endpoint 607 * @is_in: ep direction (USB_DIR_IN or 0) 608 */ 609static void inc_ep_stats_bytes(struct pxa_ep *ep, int count, int is_in) 610{ 611 if (is_in) 612 ep->stats.in_bytes += count; 613 else 614 ep->stats.out_bytes += count; 615} 616 617/** 618 * pxa_ep_setup - Sets up an usb physical endpoint 619 * @ep: pxa27x physical endpoint 620 * 621 * Find the physical pxa27x ep, and setup its UDCCR 622 */ 623static __init void pxa_ep_setup(struct pxa_ep *ep) 624{ 625 u32 new_udccr; 626 627 new_udccr = ((ep->config << UDCCONR_CN_S) & UDCCONR_CN) 628 | ((ep->interface << UDCCONR_IN_S) & UDCCONR_IN) 629 | ((ep->alternate << UDCCONR_AISN_S) & UDCCONR_AISN) 630 | ((EPADDR(ep) << UDCCONR_EN_S) & UDCCONR_EN) 631 | ((EPXFERTYPE(ep) << UDCCONR_ET_S) & UDCCONR_ET) 632 | ((ep->dir_in) ? UDCCONR_ED : 0) 633 | ((ep->fifo_size << UDCCONR_MPS_S) & UDCCONR_MPS) 634 | UDCCONR_EE; 635 636 udc_ep_writel(ep, UDCCR, new_udccr); 637} 638 639/** 640 * pxa_eps_setup - Sets up all usb physical endpoints 641 * @dev: udc device 642 * 643 * Setup all pxa physical endpoints, except ep0 644 */ 645static __init void pxa_eps_setup(struct pxa_udc *dev) 646{ 647 unsigned int i; 648 649 dev_dbg(dev->dev, "%s: dev=%p\n", __func__, dev); 650 651 for (i = 1; i < NR_PXA_ENDPOINTS; i++) 652 pxa_ep_setup(&dev->pxa_ep[i]); 653} 654 655/** 656 * pxa_ep_alloc_request - Allocate usb request 657 * @_ep: usb endpoint 658 * @gfp_flags: 659 * 660 * For the pxa27x, these can just wrap kmalloc/kfree. gadget drivers 661 * must still pass correctly initialized endpoints, since other controller 662 * drivers may care about how it's currently set up (dma issues etc). 663 */ 664static struct usb_request * 665pxa_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags) 666{ 667 struct pxa27x_request *req; 668 669 req = kzalloc(sizeof *req, gfp_flags); 670 if (!req) 671 return NULL; 672 673 INIT_LIST_HEAD(&req->queue); 674 req->in_use = 0; 675 req->udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep); 676 677 return &req->req; 678} 679 680/** 681 * pxa_ep_free_request - Free usb request 682 * @_ep: usb endpoint 683 * @_req: usb request 684 * 685 * Wrapper around kfree to free _req 686 */ 687static void pxa_ep_free_request(struct usb_ep *_ep, struct usb_request *_req) 688{ 689 struct pxa27x_request *req; 690 691 req = container_of(_req, struct pxa27x_request, req); 692 WARN_ON(!list_empty(&req->queue)); 693 kfree(req); 694} 695 696/** 697 * ep_add_request - add a request to the endpoint's queue 698 * @ep: usb endpoint 699 * @req: usb request 700 * 701 * Context: ep->lock held 702 * 703 * Queues the request in the endpoint's queue, and enables the interrupts 704 * on the endpoint. 705 */ 706static void ep_add_request(struct pxa_ep *ep, struct pxa27x_request *req) 707{ 708 if (unlikely(!req)) 709 return; 710 ep_vdbg(ep, "req:%p, lg=%d, udccsr=0x%03x\n", req, 711 req->req.length, udc_ep_readl(ep, UDCCSR)); 712 713 req->in_use = 1; 714 list_add_tail(&req->queue, &ep->queue); 715 pio_irq_enable(ep); 716} 717 718/** 719 * ep_del_request - removes a request from the endpoint's queue 720 * @ep: usb endpoint 721 * @req: usb request 722 * 723 * Context: ep->lock held 724 * 725 * Unqueue the request from the endpoint's queue. If there are no more requests 726 * on the endpoint, and if it's not the control endpoint, interrupts are 727 * disabled on the endpoint. 728 */ 729static void ep_del_request(struct pxa_ep *ep, struct pxa27x_request *req) 730{ 731 if (unlikely(!req)) 732 return; 733 ep_vdbg(ep, "req:%p, lg=%d, udccsr=0x%03x\n", req, 734 req->req.length, udc_ep_readl(ep, UDCCSR)); 735 736 list_del_init(&req->queue); 737 req->in_use = 0; 738 if (!is_ep0(ep) && list_empty(&ep->queue)) 739 pio_irq_disable(ep); 740} 741 742/** 743 * req_done - Complete an usb request 744 * @ep: pxa physical endpoint 745 * @req: pxa request 746 * @status: usb request status sent to gadget API 747 * @pflags: flags of previous spinlock_irq_save() or NULL if no lock held 748 * 749 * Context: ep->lock held if flags not NULL, else ep->lock released 750 * 751 * Retire a pxa27x usb request. Endpoint must be locked. 752 */ 753static void req_done(struct pxa_ep *ep, struct pxa27x_request *req, int status, 754 unsigned long *pflags) 755{ 756 unsigned long flags; 757 758 ep_del_request(ep, req); 759 if (likely(req->req.status == -EINPROGRESS)) 760 req->req.status = status; 761 else 762 status = req->req.status; 763 764 if (status && status != -ESHUTDOWN) 765 ep_dbg(ep, "complete req %p stat %d len %u/%u\n", 766 &req->req, status, 767 req->req.actual, req->req.length); 768 769 if (pflags) 770 spin_unlock_irqrestore(&ep->lock, *pflags); 771 local_irq_save(flags); 772 req->req.complete(&req->udc_usb_ep->usb_ep, &req->req); 773 local_irq_restore(flags); 774 if (pflags) 775 spin_lock_irqsave(&ep->lock, *pflags); 776} 777 778/** 779 * ep_end_out_req - Ends endpoint OUT request 780 * @ep: physical endpoint 781 * @req: pxa request 782 * @pflags: flags of previous spinlock_irq_save() or NULL if no lock held 783 * 784 * Context: ep->lock held or released (see req_done()) 785 * 786 * Ends endpoint OUT request (completes usb request). 787 */ 788static void ep_end_out_req(struct pxa_ep *ep, struct pxa27x_request *req, 789 unsigned long *pflags) 790{ 791 inc_ep_stats_reqs(ep, !USB_DIR_IN); 792 req_done(ep, req, 0, pflags); 793} 794 795/** 796 * ep0_end_out_req - Ends control endpoint OUT request (ends data stage) 797 * @ep: physical endpoint 798 * @req: pxa request 799 * @pflags: flags of previous spinlock_irq_save() or NULL if no lock held 800 * 801 * Context: ep->lock held or released (see req_done()) 802 * 803 * Ends control endpoint OUT request (completes usb request), and puts 804 * control endpoint into idle state 805 */ 806static void ep0_end_out_req(struct pxa_ep *ep, struct pxa27x_request *req, 807 unsigned long *pflags) 808{ 809 set_ep0state(ep->dev, OUT_STATUS_STAGE); 810 ep_end_out_req(ep, req, pflags); 811 ep0_idle(ep->dev); 812} 813 814/** 815 * ep_end_in_req - Ends endpoint IN request 816 * @ep: physical endpoint 817 * @req: pxa request 818 * @pflags: flags of previous spinlock_irq_save() or NULL if no lock held 819 * 820 * Context: ep->lock held or released (see req_done()) 821 * 822 * Ends endpoint IN request (completes usb request). 823 */ 824static void ep_end_in_req(struct pxa_ep *ep, struct pxa27x_request *req, 825 unsigned long *pflags) 826{ 827 inc_ep_stats_reqs(ep, USB_DIR_IN); 828 req_done(ep, req, 0, pflags); 829} 830 831/** 832 * ep0_end_in_req - Ends control endpoint IN request (ends data stage) 833 * @ep: physical endpoint 834 * @req: pxa request 835 * @pflags: flags of previous spinlock_irq_save() or NULL if no lock held 836 * 837 * Context: ep->lock held or released (see req_done()) 838 * 839 * Ends control endpoint IN request (completes usb request), and puts 840 * control endpoint into status state 841 */ 842static void ep0_end_in_req(struct pxa_ep *ep, struct pxa27x_request *req, 843 unsigned long *pflags) 844{ 845 set_ep0state(ep->dev, IN_STATUS_STAGE); 846 ep_end_in_req(ep, req, pflags); 847} 848 849/** 850 * nuke - Dequeue all requests 851 * @ep: pxa endpoint 852 * @status: usb request status 853 * 854 * Context: ep->lock released 855 * 856 * Dequeues all requests on an endpoint. As a side effect, interrupts will be 857 * disabled on that endpoint (because no more requests). 858 */ 859static void nuke(struct pxa_ep *ep, int status) 860{ 861 struct pxa27x_request *req; 862 unsigned long flags; 863 864 spin_lock_irqsave(&ep->lock, flags); 865 while (!list_empty(&ep->queue)) { 866 req = list_entry(ep->queue.next, struct pxa27x_request, queue); 867 req_done(ep, req, status, &flags); 868 } 869 spin_unlock_irqrestore(&ep->lock, flags); 870} 871 872/** 873 * read_packet - transfer 1 packet from an OUT endpoint into request 874 * @ep: pxa physical endpoint 875 * @req: usb request 876 * 877 * Takes bytes from OUT endpoint and transfers them info the usb request. 878 * If there is less space in request than bytes received in OUT endpoint, 879 * bytes are left in the OUT endpoint. 880 * 881 * Returns how many bytes were actually transferred 882 */ 883static int read_packet(struct pxa_ep *ep, struct pxa27x_request *req) 884{ 885 u32 *buf; 886 int bytes_ep, bufferspace, count, i; 887 888 bytes_ep = ep_count_bytes_remain(ep); 889 bufferspace = req->req.length - req->req.actual; 890 891 buf = (u32 *)(req->req.buf + req->req.actual); 892 prefetchw(buf); 893 894 if (likely(!ep_is_empty(ep))) 895 count = min(bytes_ep, bufferspace); 896 else /* zlp */ 897 count = 0; 898 899 for (i = count; i > 0; i -= 4) 900 *buf++ = udc_ep_readl(ep, UDCDR); 901 req->req.actual += count; 902 903 ep_write_UDCCSR(ep, UDCCSR_PC); 904 905 return count; 906} 907 908/** 909 * write_packet - transfer 1 packet from request into an IN endpoint 910 * @ep: pxa physical endpoint 911 * @req: usb request 912 * @max: max bytes that fit into endpoint 913 * 914 * Takes bytes from usb request, and transfers them into the physical 915 * endpoint. If there are no bytes to transfer, doesn't write anything 916 * to physical endpoint. 917 * 918 * Returns how many bytes were actually transferred. 919 */ 920static int write_packet(struct pxa_ep *ep, struct pxa27x_request *req, 921 unsigned int max) 922{ 923 int length, count, remain, i; 924 u32 *buf; 925 u8 *buf_8; 926 927 buf = (u32 *)(req->req.buf + req->req.actual); 928 prefetch(buf); 929 930 length = min(req->req.length - req->req.actual, max); 931 req->req.actual += length; 932 933 remain = length & 0x3; 934 count = length & ~(0x3); 935 for (i = count; i > 0 ; i -= 4) 936 udc_ep_writel(ep, UDCDR, *buf++); 937 938 buf_8 = (u8 *)buf; 939 for (i = remain; i > 0; i--) 940 udc_ep_writeb(ep, UDCDR, *buf_8++); 941 942 ep_vdbg(ep, "length=%d+%d, udccsr=0x%03x\n", count, remain, 943 udc_ep_readl(ep, UDCCSR)); 944 945 return length; 946} 947 948/** 949 * read_fifo - Transfer packets from OUT endpoint into usb request 950 * @ep: pxa physical endpoint 951 * @req: usb request 952 * 953 * Context: callable when in_interrupt() 954 * 955 * Unload as many packets as possible from the fifo we use for usb OUT 956 * transfers and put them into the request. Caller should have made sure 957 * there's at least one packet ready. 958 * Doesn't complete the request, that's the caller's job 959 * 960 * Returns 1 if the request completed, 0 otherwise 961 */ 962static int read_fifo(struct pxa_ep *ep, struct pxa27x_request *req) 963{ 964 int count, is_short, completed = 0; 965 966 while (epout_has_pkt(ep)) { 967 count = read_packet(ep, req); 968 inc_ep_stats_bytes(ep, count, !USB_DIR_IN); 969 970 is_short = (count < ep->fifo_size); 971 ep_dbg(ep, "read udccsr:%03x, count:%d bytes%s req %p %d/%d\n", 972 udc_ep_readl(ep, UDCCSR), count, is_short ? "/S" : "", 973 &req->req, req->req.actual, req->req.length); 974 975 /* completion */ 976 if (is_short || req->req.actual == req->req.length) { 977 completed = 1; 978 break; 979 } 980 /* finished that packet. the next one may be waiting... */ 981 } 982 return completed; 983} 984 985/** 986 * write_fifo - transfer packets from usb request into an IN endpoint 987 * @ep: pxa physical endpoint 988 * @req: pxa usb request 989 * 990 * Write to an IN endpoint fifo, as many packets as possible. 991 * irqs will use this to write the rest later. 992 * caller guarantees at least one packet buffer is ready (or a zlp). 993 * Doesn't complete the request, that's the caller's job 994 * 995 * Returns 1 if request fully transferred, 0 if partial transfer 996 */ 997static int write_fifo(struct pxa_ep *ep, struct pxa27x_request *req) 998{ 999 unsigned max; 1000 int count, is_short, is_last = 0, completed = 0, totcount = 0; 1001 u32 udccsr; 1002 1003 max = ep->fifo_size; 1004 do { 1005 is_short = 0; 1006 1007 udccsr = udc_ep_readl(ep, UDCCSR); 1008 if (udccsr & UDCCSR_PC) { 1009 ep_vdbg(ep, "Clearing Transmit Complete, udccsr=%x\n", 1010 udccsr); 1011 ep_write_UDCCSR(ep, UDCCSR_PC); 1012 } 1013 if (udccsr & UDCCSR_TRN) { 1014 ep_vdbg(ep, "Clearing Underrun on, udccsr=%x\n", 1015 udccsr); 1016 ep_write_UDCCSR(ep, UDCCSR_TRN); 1017 } 1018 1019 count = write_packet(ep, req, max); 1020 inc_ep_stats_bytes(ep, count, USB_DIR_IN); 1021 totcount += count; 1022 1023 /* last packet is usually short (or a zlp) */ 1024 if (unlikely(count < max)) { 1025 is_last = 1; 1026 is_short = 1; 1027 } else { 1028 if (likely(req->req.length > req->req.actual) 1029 || req->req.zero) 1030 is_last = 0; 1031 else 1032 is_last = 1; 1033 /* interrupt/iso maxpacket may not fill the fifo */ 1034 is_short = unlikely(max < ep->fifo_size); 1035 } 1036 1037 if (is_short) 1038 ep_write_UDCCSR(ep, UDCCSR_SP); 1039 1040 /* requests complete when all IN data is in the FIFO */ 1041 if (is_last) { 1042 completed = 1; 1043 break; 1044 } 1045 } while (!ep_is_full(ep)); 1046 1047 ep_dbg(ep, "wrote count:%d bytes%s%s, left:%d req=%p\n", 1048 totcount, is_last ? "/L" : "", is_short ? "/S" : "", 1049 req->req.length - req->req.actual, &req->req); 1050 1051 return completed; 1052} 1053 1054/** 1055 * read_ep0_fifo - Transfer packets from control endpoint into usb request 1056 * @ep: control endpoint 1057 * @req: pxa usb request 1058 * 1059 * Special ep0 version of the above read_fifo. Reads as many bytes from control 1060 * endpoint as can be read, and stores them into usb request (limited by request 1061 * maximum length). 1062 * 1063 * Returns 0 if usb request only partially filled, 1 if fully filled 1064 */ 1065static int read_ep0_fifo(struct pxa_ep *ep, struct pxa27x_request *req) 1066{ 1067 int count, is_short, completed = 0; 1068 1069 while (epout_has_pkt(ep)) { 1070 count = read_packet(ep, req); 1071 ep_write_UDCCSR(ep, UDCCSR0_OPC); 1072 inc_ep_stats_bytes(ep, count, !USB_DIR_IN); 1073 1074 is_short = (count < ep->fifo_size); 1075 ep_dbg(ep, "read udccsr:%03x, count:%d bytes%s req %p %d/%d\n", 1076 udc_ep_readl(ep, UDCCSR), count, is_short ? "/S" : "", 1077 &req->req, req->req.actual, req->req.length); 1078 1079 if (is_short || req->req.actual >= req->req.length) { 1080 completed = 1; 1081 break; 1082 } 1083 } 1084 1085 return completed; 1086} 1087 1088/** 1089 * write_ep0_fifo - Send a request to control endpoint (ep0 in) 1090 * @ep: control endpoint 1091 * @req: request 1092 * 1093 * Context: callable when in_interrupt() 1094 * 1095 * Sends a request (or a part of the request) to the control endpoint (ep0 in). 1096 * If the request doesn't fit, the remaining part will be sent from irq. 1097 * The request is considered fully written only if either : 1098 * - last write transferred all remaining bytes, but fifo was not fully filled 1099 * - last write was a 0 length write 1100 * 1101 * Returns 1 if request fully written, 0 if request only partially sent 1102 */ 1103static int write_ep0_fifo(struct pxa_ep *ep, struct pxa27x_request *req) 1104{ 1105 unsigned count; 1106 int is_last, is_short; 1107 1108 count = write_packet(ep, req, EP0_FIFO_SIZE); 1109 inc_ep_stats_bytes(ep, count, USB_DIR_IN); 1110 1111 is_short = (count < EP0_FIFO_SIZE); 1112 is_last = ((count == 0) || (count < EP0_FIFO_SIZE)); 1113 1114 /* Sends either a short packet or a 0 length packet */ 1115 if (unlikely(is_short)) 1116 ep_write_UDCCSR(ep, UDCCSR0_IPR); 1117 1118 ep_dbg(ep, "in %d bytes%s%s, %d left, req=%p, udccsr0=0x%03x\n", 1119 count, is_short ? "/S" : "", is_last ? "/L" : "", 1120 req->req.length - req->req.actual, 1121 &req->req, udc_ep_readl(ep, UDCCSR)); 1122 1123 return is_last; 1124} 1125 1126/** 1127 * pxa_ep_queue - Queue a request into an IN endpoint 1128 * @_ep: usb endpoint 1129 * @_req: usb request 1130 * @gfp_flags: flags 1131 * 1132 * Context: normally called when !in_interrupt, but callable when in_interrupt() 1133 * in the special case of ep0 setup : 1134 * (irq->handle_ep0_ctrl_req->gadget_setup->pxa_ep_queue) 1135 * 1136 * Returns 0 if succedeed, error otherwise 1137 */ 1138static int pxa_ep_queue(struct usb_ep *_ep, struct usb_request *_req, 1139 gfp_t gfp_flags) 1140{ 1141 struct udc_usb_ep *udc_usb_ep; 1142 struct pxa_ep *ep; 1143 struct pxa27x_request *req; 1144 struct pxa_udc *dev; 1145 unsigned long flags; 1146 int rc = 0; 1147 int is_first_req; 1148 unsigned length; 1149 int recursion_detected; 1150 1151 req = container_of(_req, struct pxa27x_request, req); 1152 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep); 1153 1154 if (unlikely(!_req || !_req->complete || !_req->buf)) 1155 return -EINVAL; 1156 1157 if (unlikely(!_ep)) 1158 return -EINVAL; 1159 1160 dev = udc_usb_ep->dev; 1161 ep = udc_usb_ep->pxa_ep; 1162 if (unlikely(!ep)) 1163 return -EINVAL; 1164 1165 dev = ep->dev; 1166 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) { 1167 ep_dbg(ep, "bogus device state\n"); 1168 return -ESHUTDOWN; 1169 } 1170 1171 /* iso is always one packet per request, that's the only way 1172 * we can report per-packet status. that also helps with dma. 1173 */ 1174 if (unlikely(EPXFERTYPE_is_ISO(ep) 1175 && req->req.length > ep->fifo_size)) 1176 return -EMSGSIZE; 1177 1178 spin_lock_irqsave(&ep->lock, flags); 1179 recursion_detected = ep->in_handle_ep; 1180 1181 is_first_req = list_empty(&ep->queue); 1182 ep_dbg(ep, "queue req %p(first=%s), len %d buf %p\n", 1183 _req, is_first_req ? "yes" : "no", 1184 _req->length, _req->buf); 1185 1186 if (!ep->enabled) { 1187 _req->status = -ESHUTDOWN; 1188 rc = -ESHUTDOWN; 1189 goto out_locked; 1190 } 1191 1192 if (req->in_use) { 1193 ep_err(ep, "refusing to queue req %p (already queued)\n", req); 1194 goto out_locked; 1195 } 1196 1197 length = _req->length; 1198 _req->status = -EINPROGRESS; 1199 _req->actual = 0; 1200 1201 ep_add_request(ep, req); 1202 spin_unlock_irqrestore(&ep->lock, flags); 1203 1204 if (is_ep0(ep)) { 1205 switch (dev->ep0state) { 1206 case WAIT_ACK_SET_CONF_INTERF: 1207 if (length == 0) { 1208 ep_end_in_req(ep, req, NULL); 1209 } else { 1210 ep_err(ep, "got a request of %d bytes while" 1211 "in state WAIT_ACK_SET_CONF_INTERF\n", 1212 length); 1213 ep_del_request(ep, req); 1214 rc = -EL2HLT; 1215 } 1216 ep0_idle(ep->dev); 1217 break; 1218 case IN_DATA_STAGE: 1219 if (!ep_is_full(ep)) 1220 if (write_ep0_fifo(ep, req)) 1221 ep0_end_in_req(ep, req, NULL); 1222 break; 1223 case OUT_DATA_STAGE: 1224 if ((length == 0) || !epout_has_pkt(ep)) 1225 if (read_ep0_fifo(ep, req)) 1226 ep0_end_out_req(ep, req, NULL); 1227 break; 1228 default: 1229 ep_err(ep, "odd state %s to send me a request\n", 1230 EP0_STNAME(ep->dev)); 1231 ep_del_request(ep, req); 1232 rc = -EL2HLT; 1233 break; 1234 } 1235 } else { 1236 if (!recursion_detected) 1237 handle_ep(ep); 1238 } 1239 1240out: 1241 return rc; 1242out_locked: 1243 spin_unlock_irqrestore(&ep->lock, flags); 1244 goto out; 1245} 1246 1247/** 1248 * pxa_ep_dequeue - Dequeue one request 1249 * @_ep: usb endpoint 1250 * @_req: usb request 1251 * 1252 * Return 0 if no error, -EINVAL or -ECONNRESET otherwise 1253 */ 1254static int pxa_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) 1255{ 1256 struct pxa_ep *ep; 1257 struct udc_usb_ep *udc_usb_ep; 1258 struct pxa27x_request *req; 1259 unsigned long flags; 1260 int rc = -EINVAL; 1261 1262 if (!_ep) 1263 return rc; 1264 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep); 1265 ep = udc_usb_ep->pxa_ep; 1266 if (!ep || is_ep0(ep)) 1267 return rc; 1268 1269 spin_lock_irqsave(&ep->lock, flags); 1270 1271 /* make sure it's actually queued on this endpoint */ 1272 list_for_each_entry(req, &ep->queue, queue) { 1273 if (&req->req == _req) { 1274 rc = 0; 1275 break; 1276 } 1277 } 1278 1279 spin_unlock_irqrestore(&ep->lock, flags); 1280 if (!rc) 1281 req_done(ep, req, -ECONNRESET, NULL); 1282 return rc; 1283} 1284 1285/** 1286 * pxa_ep_set_halt - Halts operations on one endpoint 1287 * @_ep: usb endpoint 1288 * @value: 1289 * 1290 * Returns 0 if no error, -EINVAL, -EROFS, -EAGAIN otherwise 1291 */ 1292static int pxa_ep_set_halt(struct usb_ep *_ep, int value) 1293{ 1294 struct pxa_ep *ep; 1295 struct udc_usb_ep *udc_usb_ep; 1296 unsigned long flags; 1297 int rc; 1298 1299 1300 if (!_ep) 1301 return -EINVAL; 1302 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep); 1303 ep = udc_usb_ep->pxa_ep; 1304 if (!ep || is_ep0(ep)) 1305 return -EINVAL; 1306 1307 if (value == 0) { 1308 /* 1309 * This path (reset toggle+halt) is needed to implement 1310 * SET_INTERFACE on normal hardware. but it can't be 1311 * done from software on the PXA UDC, and the hardware 1312 * forgets to do it as part of SET_INTERFACE automagic. 1313 */ 1314 ep_dbg(ep, "only host can clear halt\n"); 1315 return -EROFS; 1316 } 1317 1318 spin_lock_irqsave(&ep->lock, flags); 1319 1320 rc = -EAGAIN; 1321 if (ep->dir_in && (ep_is_full(ep) || !list_empty(&ep->queue))) 1322 goto out; 1323 1324 /* FST, FEF bits are the same for control and non control endpoints */ 1325 rc = 0; 1326 ep_write_UDCCSR(ep, UDCCSR_FST | UDCCSR_FEF); 1327 if (is_ep0(ep)) 1328 set_ep0state(ep->dev, STALL); 1329 1330out: 1331 spin_unlock_irqrestore(&ep->lock, flags); 1332 return rc; 1333} 1334 1335/** 1336 * pxa_ep_fifo_status - Get how many bytes in physical endpoint 1337 * @_ep: usb endpoint 1338 * 1339 * Returns number of bytes in OUT fifos. Broken for IN fifos. 1340 */ 1341static int pxa_ep_fifo_status(struct usb_ep *_ep) 1342{ 1343 struct pxa_ep *ep; 1344 struct udc_usb_ep *udc_usb_ep; 1345 1346 if (!_ep) 1347 return -ENODEV; 1348 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep); 1349 ep = udc_usb_ep->pxa_ep; 1350 if (!ep || is_ep0(ep)) 1351 return -ENODEV; 1352 1353 if (ep->dir_in) 1354 return -EOPNOTSUPP; 1355 if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN || ep_is_empty(ep)) 1356 return 0; 1357 else 1358 return ep_count_bytes_remain(ep) + 1; 1359} 1360 1361/** 1362 * pxa_ep_fifo_flush - Flushes one endpoint 1363 * @_ep: usb endpoint 1364 * 1365 * Discards all data in one endpoint(IN or OUT), except control endpoint. 1366 */ 1367static void pxa_ep_fifo_flush(struct usb_ep *_ep) 1368{ 1369 struct pxa_ep *ep; 1370 struct udc_usb_ep *udc_usb_ep; 1371 unsigned long flags; 1372 1373 if (!_ep) 1374 return; 1375 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep); 1376 ep = udc_usb_ep->pxa_ep; 1377 if (!ep || is_ep0(ep)) 1378 return; 1379 1380 spin_lock_irqsave(&ep->lock, flags); 1381 1382 if (unlikely(!list_empty(&ep->queue))) 1383 ep_dbg(ep, "called while queue list not empty\n"); 1384 ep_dbg(ep, "called\n"); 1385 1386 /* for OUT, just read and discard the FIFO contents. */ 1387 if (!ep->dir_in) { 1388 while (!ep_is_empty(ep)) 1389 udc_ep_readl(ep, UDCDR); 1390 } else { 1391 /* most IN status is the same, but ISO can't stall */ 1392 ep_write_UDCCSR(ep, 1393 UDCCSR_PC | UDCCSR_FEF | UDCCSR_TRN 1394 | (EPXFERTYPE_is_ISO(ep) ? 0 : UDCCSR_SST)); 1395 } 1396 1397 spin_unlock_irqrestore(&ep->lock, flags); 1398} 1399 1400/** 1401 * pxa_ep_enable - Enables usb endpoint 1402 * @_ep: usb endpoint 1403 * @desc: usb endpoint descriptor 1404 * 1405 * Nothing much to do here, as ep configuration is done once and for all 1406 * before udc is enabled. After udc enable, no physical endpoint configuration 1407 * can be changed. 1408 * Function makes sanity checks and flushes the endpoint. 1409 */ 1410static int pxa_ep_enable(struct usb_ep *_ep, 1411 const struct usb_endpoint_descriptor *desc) 1412{ 1413 struct pxa_ep *ep; 1414 struct udc_usb_ep *udc_usb_ep; 1415 struct pxa_udc *udc; 1416 1417 if (!_ep || !desc) 1418 return -EINVAL; 1419 1420 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep); 1421 if (udc_usb_ep->pxa_ep) { 1422 ep = udc_usb_ep->pxa_ep; 1423 ep_warn(ep, "usb_ep %s already enabled, doing nothing\n", 1424 _ep->name); 1425 } else { 1426 ep = find_pxa_ep(udc_usb_ep->dev, udc_usb_ep); 1427 } 1428 1429 if (!ep || is_ep0(ep)) { 1430 dev_err(udc_usb_ep->dev->dev, 1431 "unable to match pxa_ep for ep %s\n", 1432 _ep->name); 1433 return -EINVAL; 1434 } 1435 1436 if ((desc->bDescriptorType != USB_DT_ENDPOINT) 1437 || (ep->type != usb_endpoint_type(desc))) { 1438 ep_err(ep, "type mismatch\n"); 1439 return -EINVAL; 1440 } 1441 1442 if (ep->fifo_size < le16_to_cpu(desc->wMaxPacketSize)) { 1443 ep_err(ep, "bad maxpacket\n"); 1444 return -ERANGE; 1445 } 1446 1447 udc_usb_ep->pxa_ep = ep; 1448 udc = ep->dev; 1449 1450 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { 1451 ep_err(ep, "bogus device state\n"); 1452 return -ESHUTDOWN; 1453 } 1454 1455 ep->enabled = 1; 1456 1457 /* flush fifo (mostly for OUT buffers) */ 1458 pxa_ep_fifo_flush(_ep); 1459 1460 ep_dbg(ep, "enabled\n"); 1461 return 0; 1462} 1463 1464/** 1465 * pxa_ep_disable - Disable usb endpoint 1466 * @_ep: usb endpoint 1467 * 1468 * Same as for pxa_ep_enable, no physical endpoint configuration can be 1469 * changed. 1470 * Function flushes the endpoint and related requests. 1471 */ 1472static int pxa_ep_disable(struct usb_ep *_ep) 1473{ 1474 struct pxa_ep *ep; 1475 struct udc_usb_ep *udc_usb_ep; 1476 1477 if (!_ep) 1478 return -EINVAL; 1479 1480 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep); 1481 ep = udc_usb_ep->pxa_ep; 1482 if (!ep || is_ep0(ep) || !list_empty(&ep->queue)) 1483 return -EINVAL; 1484 1485 ep->enabled = 0; 1486 nuke(ep, -ESHUTDOWN); 1487 1488 pxa_ep_fifo_flush(_ep); 1489 udc_usb_ep->pxa_ep = NULL; 1490 1491 ep_dbg(ep, "disabled\n"); 1492 return 0; 1493} 1494 1495static struct usb_ep_ops pxa_ep_ops = { 1496 .enable = pxa_ep_enable, 1497 .disable = pxa_ep_disable, 1498 1499 .alloc_request = pxa_ep_alloc_request, 1500 .free_request = pxa_ep_free_request, 1501 1502 .queue = pxa_ep_queue, 1503 .dequeue = pxa_ep_dequeue, 1504 1505 .set_halt = pxa_ep_set_halt, 1506 .fifo_status = pxa_ep_fifo_status, 1507 .fifo_flush = pxa_ep_fifo_flush, 1508}; 1509 1510/** 1511 * dplus_pullup - Connect or disconnect pullup resistor to D+ pin 1512 * @udc: udc device 1513 * @on: 0 if disconnect pullup resistor, 1 otherwise 1514 * Context: any 1515 * 1516 * Handle D+ pullup resistor, make the device visible to the usb bus, and 1517 * declare it as a full speed usb device 1518 */ 1519static void dplus_pullup(struct pxa_udc *udc, int on) 1520{ 1521 if (on) { 1522 if (gpio_is_valid(udc->mach->gpio_pullup)) 1523 gpio_set_value(udc->mach->gpio_pullup, 1524 !udc->mach->gpio_pullup_inverted); 1525 if (udc->mach->udc_command) 1526 udc->mach->udc_command(PXA2XX_UDC_CMD_CONNECT); 1527 } else { 1528 if (gpio_is_valid(udc->mach->gpio_pullup)) 1529 gpio_set_value(udc->mach->gpio_pullup, 1530 udc->mach->gpio_pullup_inverted); 1531 if (udc->mach->udc_command) 1532 udc->mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT); 1533 } 1534 udc->pullup_on = on; 1535} 1536 1537/** 1538 * pxa_udc_get_frame - Returns usb frame number 1539 * @_gadget: usb gadget 1540 */ 1541static int pxa_udc_get_frame(struct usb_gadget *_gadget) 1542{ 1543 struct pxa_udc *udc = to_gadget_udc(_gadget); 1544 1545 return (udc_readl(udc, UDCFNR) & 0x7ff); 1546} 1547 1548/** 1549 * pxa_udc_wakeup - Force udc device out of suspend 1550 * @_gadget: usb gadget 1551 * 1552 * Returns 0 if successful, error code otherwise 1553 */ 1554static int pxa_udc_wakeup(struct usb_gadget *_gadget) 1555{ 1556 struct pxa_udc *udc = to_gadget_udc(_gadget); 1557 1558 /* host may not have enabled remote wakeup */ 1559 if ((udc_readl(udc, UDCCR) & UDCCR_DWRE) == 0) 1560 return -EHOSTUNREACH; 1561 udc_set_mask_UDCCR(udc, UDCCR_UDR); 1562 return 0; 1563} 1564 1565static void udc_enable(struct pxa_udc *udc); 1566static void udc_disable(struct pxa_udc *udc); 1567 1568/** 1569 * should_enable_udc - Tells if UDC should be enabled 1570 * @udc: udc device 1571 * Context: any 1572 * 1573 * The UDC should be enabled if : 1574 1575 * - the pullup resistor is connected 1576 * - and a gadget driver is bound 1577 * - and vbus is sensed (or no vbus sense is available) 1578 * 1579 * Returns 1 if UDC should be enabled, 0 otherwise 1580 */ 1581static int should_enable_udc(struct pxa_udc *udc) 1582{ 1583 int put_on; 1584 1585 put_on = ((udc->pullup_on) && (udc->driver)); 1586 put_on &= ((udc->vbus_sensed) || (!udc->transceiver)); 1587 return put_on; 1588} 1589 1590/** 1591 * should_disable_udc - Tells if UDC should be disabled 1592 * @udc: udc device 1593 * Context: any 1594 * 1595 * The UDC should be disabled if : 1596 * - the pullup resistor is not connected 1597 * - or no gadget driver is bound 1598 * - or no vbus is sensed (when vbus sesing is available) 1599 * 1600 * Returns 1 if UDC should be disabled 1601 */ 1602static int should_disable_udc(struct pxa_udc *udc) 1603{ 1604 int put_off; 1605 1606 put_off = ((!udc->pullup_on) || (!udc->driver)); 1607 put_off |= ((!udc->vbus_sensed) && (udc->transceiver)); 1608 return put_off; 1609} 1610 1611/** 1612 * pxa_udc_pullup - Offer manual D+ pullup control 1613 * @_gadget: usb gadget using the control 1614 * @is_active: 0 if disconnect, else connect D+ pullup resistor 1615 * Context: !in_interrupt() 1616 * 1617 * Returns 0 if OK, -EOPNOTSUPP if udc driver doesn't handle D+ pullup 1618 */ 1619static int pxa_udc_pullup(struct usb_gadget *_gadget, int is_active) 1620{ 1621 struct pxa_udc *udc = to_gadget_udc(_gadget); 1622 1623 if (!gpio_is_valid(udc->mach->gpio_pullup) && !udc->mach->udc_command) 1624 return -EOPNOTSUPP; 1625 1626 dplus_pullup(udc, is_active); 1627 1628 if (should_enable_udc(udc)) 1629 udc_enable(udc); 1630 if (should_disable_udc(udc)) 1631 udc_disable(udc); 1632 return 0; 1633} 1634 1635static void udc_enable(struct pxa_udc *udc); 1636static void udc_disable(struct pxa_udc *udc); 1637 1638/** 1639 * pxa_udc_vbus_session - Called by external transceiver to enable/disable udc 1640 * @_gadget: usb gadget 1641 * @is_active: 0 if should disable the udc, 1 if should enable 1642 * 1643 * Enables the udc, and optionnaly activates D+ pullup resistor. Or disables the 1644 * udc, and deactivates D+ pullup resistor. 1645 * 1646 * Returns 0 1647 */ 1648static int pxa_udc_vbus_session(struct usb_gadget *_gadget, int is_active) 1649{ 1650 struct pxa_udc *udc = to_gadget_udc(_gadget); 1651 1652 udc->vbus_sensed = is_active; 1653 if (should_enable_udc(udc)) 1654 udc_enable(udc); 1655 if (should_disable_udc(udc)) 1656 udc_disable(udc); 1657 1658 return 0; 1659} 1660 1661/** 1662 * pxa_udc_vbus_draw - Called by gadget driver after SET_CONFIGURATION completed 1663 * @_gadget: usb gadget 1664 * @mA: current drawn 1665 * 1666 * Context: !in_interrupt() 1667 * 1668 * Called after a configuration was chosen by a USB host, to inform how much 1669 * current can be drawn by the device from VBus line. 1670 * 1671 * Returns 0 or -EOPNOTSUPP if no transceiver is handling the udc 1672 */ 1673static int pxa_udc_vbus_draw(struct usb_gadget *_gadget, unsigned mA) 1674{ 1675 struct pxa_udc *udc; 1676 1677 udc = to_gadget_udc(_gadget); 1678 if (udc->transceiver) 1679 return otg_set_power(udc->transceiver, mA); 1680 return -EOPNOTSUPP; 1681} 1682 1683static int pxa27x_udc_start(struct usb_gadget_driver *driver, 1684 int (*bind)(struct usb_gadget *)); 1685static int pxa27x_udc_stop(struct usb_gadget_driver *driver); 1686 1687static const struct usb_gadget_ops pxa_udc_ops = { 1688 .get_frame = pxa_udc_get_frame, 1689 .wakeup = pxa_udc_wakeup, 1690 .pullup = pxa_udc_pullup, 1691 .vbus_session = pxa_udc_vbus_session, 1692 .vbus_draw = pxa_udc_vbus_draw, 1693 .start = pxa27x_udc_start, 1694 .stop = pxa27x_udc_stop, 1695}; 1696 1697/** 1698 * udc_disable - disable udc device controller 1699 * @udc: udc device 1700 * Context: any 1701 * 1702 * Disables the udc device : disables clocks, udc interrupts, control endpoint 1703 * interrupts. 1704 */ 1705static void udc_disable(struct pxa_udc *udc) 1706{ 1707 if (!udc->enabled) 1708 return; 1709 1710 udc_writel(udc, UDCICR0, 0); 1711 udc_writel(udc, UDCICR1, 0); 1712 1713 udc_clear_mask_UDCCR(udc, UDCCR_UDE); 1714 clk_disable(udc->clk); 1715 1716 ep0_idle(udc); 1717 udc->gadget.speed = USB_SPEED_UNKNOWN; 1718 1719 udc->enabled = 0; 1720} 1721 1722/** 1723 * udc_init_data - Initialize udc device data structures 1724 * @dev: udc device 1725 * 1726 * Initializes gadget endpoint list, endpoints locks. No action is taken 1727 * on the hardware. 1728 */ 1729static __init void udc_init_data(struct pxa_udc *dev) 1730{ 1731 int i; 1732 struct pxa_ep *ep; 1733 1734 /* device/ep0 records init */ 1735 INIT_LIST_HEAD(&dev->gadget.ep_list); 1736 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list); 1737 dev->udc_usb_ep[0].pxa_ep = &dev->pxa_ep[0]; 1738 ep0_idle(dev); 1739 1740 /* PXA endpoints init */ 1741 for (i = 0; i < NR_PXA_ENDPOINTS; i++) { 1742 ep = &dev->pxa_ep[i]; 1743 1744 ep->enabled = is_ep0(ep); 1745 INIT_LIST_HEAD(&ep->queue); 1746 spin_lock_init(&ep->lock); 1747 } 1748 1749 /* USB endpoints init */ 1750 for (i = 1; i < NR_USB_ENDPOINTS; i++) 1751 list_add_tail(&dev->udc_usb_ep[i].usb_ep.ep_list, 1752 &dev->gadget.ep_list); 1753} 1754 1755/** 1756 * udc_enable - Enables the udc device 1757 * @dev: udc device 1758 * 1759 * Enables the udc device : enables clocks, udc interrupts, control endpoint 1760 * interrupts, sets usb as UDC client and setups endpoints. 1761 */ 1762static void udc_enable(struct pxa_udc *udc) 1763{ 1764 if (udc->enabled) 1765 return; 1766 1767 udc_writel(udc, UDCICR0, 0); 1768 udc_writel(udc, UDCICR1, 0); 1769 udc_clear_mask_UDCCR(udc, UDCCR_UDE); 1770 1771 clk_enable(udc->clk); 1772 1773 ep0_idle(udc); 1774 udc->gadget.speed = USB_SPEED_FULL; 1775 memset(&udc->stats, 0, sizeof(udc->stats)); 1776 1777 udc_set_mask_UDCCR(udc, UDCCR_UDE); 1778 ep_write_UDCCSR(&udc->pxa_ep[0], UDCCSR0_ACM); 1779 udelay(2); 1780 if (udc_readl(udc, UDCCR) & UDCCR_EMCE) 1781 dev_err(udc->dev, "Configuration errors, udc disabled\n"); 1782 1783 /* 1784 * Caller must be able to sleep in order to cope with startup transients 1785 */ 1786 msleep(100); 1787 1788 /* enable suspend/resume and reset irqs */ 1789 udc_writel(udc, UDCICR1, 1790 UDCICR1_IECC | UDCICR1_IERU 1791 | UDCICR1_IESU | UDCICR1_IERS); 1792 1793 /* enable ep0 irqs */ 1794 pio_irq_enable(&udc->pxa_ep[0]); 1795 1796 udc->enabled = 1; 1797} 1798 1799/** 1800 * pxa27x_start - Register gadget driver 1801 * @driver: gadget driver 1802 * @bind: bind function 1803 * 1804 * When a driver is successfully registered, it will receive control requests 1805 * including set_configuration(), which enables non-control requests. Then 1806 * usb traffic follows until a disconnect is reported. Then a host may connect 1807 * again, or the driver might get unbound. 1808 * 1809 * Note that the udc is not automatically enabled. Check function 1810 * should_enable_udc(). 1811 * 1812 * Returns 0 if no error, -EINVAL, -ENODEV, -EBUSY otherwise 1813 */ 1814static int pxa27x_udc_start(struct usb_gadget_driver *driver, 1815 int (*bind)(struct usb_gadget *)) 1816{ 1817 struct pxa_udc *udc = the_controller; 1818 int retval; 1819 1820 if (!driver || driver->speed < USB_SPEED_FULL || !bind 1821 || !driver->disconnect || !driver->setup) 1822 return -EINVAL; 1823 if (!udc) 1824 return -ENODEV; 1825 if (udc->driver) 1826 return -EBUSY; 1827 1828 /* first hook up the driver ... */ 1829 udc->driver = driver; 1830 udc->gadget.dev.driver = &driver->driver; 1831 dplus_pullup(udc, 1); 1832 1833 retval = device_add(&udc->gadget.dev); 1834 if (retval) { 1835 dev_err(udc->dev, "device_add error %d\n", retval); 1836 goto add_fail; 1837 } 1838 retval = bind(&udc->gadget); 1839 if (retval) { 1840 dev_err(udc->dev, "bind to driver %s --> error %d\n", 1841 driver->driver.name, retval); 1842 goto bind_fail; 1843 } 1844 dev_dbg(udc->dev, "registered gadget driver '%s'\n", 1845 driver->driver.name); 1846 1847 if (udc->transceiver) { 1848 retval = otg_set_peripheral(udc->transceiver, &udc->gadget); 1849 if (retval) { 1850 dev_err(udc->dev, "can't bind to transceiver\n"); 1851 goto transceiver_fail; 1852 } 1853 } 1854 1855 if (should_enable_udc(udc)) 1856 udc_enable(udc); 1857 return 0; 1858 1859transceiver_fail: 1860 if (driver->unbind) 1861 driver->unbind(&udc->gadget); 1862bind_fail: 1863 device_del(&udc->gadget.dev); 1864add_fail: 1865 udc->driver = NULL; 1866 udc->gadget.dev.driver = NULL; 1867 return retval; 1868} 1869 1870/** 1871 * stop_activity - Stops udc endpoints 1872 * @udc: udc device 1873 * @driver: gadget driver 1874 * 1875 * Disables all udc endpoints (even control endpoint), report disconnect to 1876 * the gadget user. 1877 */ 1878static void stop_activity(struct pxa_udc *udc, struct usb_gadget_driver *driver) 1879{ 1880 int i; 1881 1882 /* don't disconnect drivers more than once */ 1883 if (udc->gadget.speed == USB_SPEED_UNKNOWN) 1884 driver = NULL; 1885 udc->gadget.speed = USB_SPEED_UNKNOWN; 1886 1887 for (i = 0; i < NR_USB_ENDPOINTS; i++) 1888 pxa_ep_disable(&udc->udc_usb_ep[i].usb_ep); 1889 1890 if (driver) 1891 driver->disconnect(&udc->gadget); 1892} 1893 1894/** 1895 * pxa27x_udc_stop - Unregister the gadget driver 1896 * @driver: gadget driver 1897 * 1898 * Returns 0 if no error, -ENODEV, -EINVAL otherwise 1899 */ 1900static int pxa27x_udc_stop(struct usb_gadget_driver *driver) 1901{ 1902 struct pxa_udc *udc = the_controller; 1903 1904 if (!udc) 1905 return -ENODEV; 1906 if (!driver || driver != udc->driver || !driver->unbind) 1907 return -EINVAL; 1908 1909 stop_activity(udc, driver); 1910 udc_disable(udc); 1911 dplus_pullup(udc, 0); 1912 1913 driver->unbind(&udc->gadget); 1914 udc->driver = NULL; 1915 1916 device_del(&udc->gadget.dev); 1917 dev_info(udc->dev, "unregistered gadget driver '%s'\n", 1918 driver->driver.name); 1919 1920 if (udc->transceiver) 1921 return otg_set_peripheral(udc->transceiver, NULL); 1922 return 0; 1923} 1924 1925/** 1926 * handle_ep0_ctrl_req - handle control endpoint control request 1927 * @udc: udc device 1928 * @req: control request 1929 */ 1930static void handle_ep0_ctrl_req(struct pxa_udc *udc, 1931 struct pxa27x_request *req) 1932{ 1933 struct pxa_ep *ep = &udc->pxa_ep[0]; 1934 union { 1935 struct usb_ctrlrequest r; 1936 u32 word[2]; 1937 } u; 1938 int i; 1939 int have_extrabytes = 0; 1940 unsigned long flags; 1941 1942 nuke(ep, -EPROTO); 1943 spin_lock_irqsave(&ep->lock, flags); 1944 1945 /* 1946 * In the PXA320 manual, in the section about Back-to-Back setup 1947 * packets, it describes this situation. The solution is to set OPC to 1948 * get rid of the status packet, and then continue with the setup 1949 * packet. Generalize to pxa27x CPUs. 1950 */ 1951 if (epout_has_pkt(ep) && (ep_count_bytes_remain(ep) == 0)) 1952 ep_write_UDCCSR(ep, UDCCSR0_OPC); 1953 1954 /* read SETUP packet */ 1955 for (i = 0; i < 2; i++) { 1956 if (unlikely(ep_is_empty(ep))) 1957 goto stall; 1958 u.word[i] = udc_ep_readl(ep, UDCDR); 1959 } 1960 1961 have_extrabytes = !ep_is_empty(ep); 1962 while (!ep_is_empty(ep)) { 1963 i = udc_ep_readl(ep, UDCDR); 1964 ep_err(ep, "wrong to have extra bytes for setup : 0x%08x\n", i); 1965 } 1966 1967 ep_dbg(ep, "SETUP %02x.%02x v%04x i%04x l%04x\n", 1968 u.r.bRequestType, u.r.bRequest, 1969 le16_to_cpu(u.r.wValue), le16_to_cpu(u.r.wIndex), 1970 le16_to_cpu(u.r.wLength)); 1971 if (unlikely(have_extrabytes)) 1972 goto stall; 1973 1974 if (u.r.bRequestType & USB_DIR_IN) 1975 set_ep0state(udc, IN_DATA_STAGE); 1976 else 1977 set_ep0state(udc, OUT_DATA_STAGE); 1978 1979 /* Tell UDC to enter Data Stage */ 1980 ep_write_UDCCSR(ep, UDCCSR0_SA | UDCCSR0_OPC); 1981 1982 spin_unlock_irqrestore(&ep->lock, flags); 1983 i = udc->driver->setup(&udc->gadget, &u.r); 1984 spin_lock_irqsave(&ep->lock, flags); 1985 if (i < 0) 1986 goto stall; 1987out: 1988 spin_unlock_irqrestore(&ep->lock, flags); 1989 return; 1990stall: 1991 ep_dbg(ep, "protocol STALL, udccsr0=%03x err %d\n", 1992 udc_ep_readl(ep, UDCCSR), i); 1993 ep_write_UDCCSR(ep, UDCCSR0_FST | UDCCSR0_FTF); 1994 set_ep0state(udc, STALL); 1995 goto out; 1996} 1997 1998/** 1999 * handle_ep0 - Handle control endpoint data transfers 2000 * @udc: udc device 2001 * @fifo_irq: 1 if triggered by fifo service type irq 2002 * @opc_irq: 1 if triggered by output packet complete type irq 2003 * 2004 * Context : when in_interrupt() or with ep->lock held 2005 * 2006 * Tries to transfer all pending request data into the endpoint and/or 2007 * transfer all pending data in the endpoint into usb requests. 2008 * Handles states of ep0 automata. 2009 * 2010 * PXA27x hardware handles several standard usb control requests without 2011 * driver notification. The requests fully handled by hardware are : 2012 * SET_ADDRESS, SET_FEATURE, CLEAR_FEATURE, GET_CONFIGURATION, GET_INTERFACE, 2013 * GET_STATUS 2014 * The requests handled by hardware, but with irq notification are : 2015 * SYNCH_FRAME, SET_CONFIGURATION, SET_INTERFACE 2016 * The remaining standard requests really handled by handle_ep0 are : 2017 * GET_DESCRIPTOR, SET_DESCRIPTOR, specific requests. 2018 * Requests standardized outside of USB 2.0 chapter 9 are handled more 2019 * uniformly, by gadget drivers. 2020 * 2021 * The control endpoint state machine is _not_ USB spec compliant, it's even 2022 * hardly compliant with Intel PXA270 developers guide. 2023 * The key points which inferred this state machine are : 2024 * - on every setup token, bit UDCCSR0_SA is raised and held until cleared by 2025 * software. 2026 * - on every OUT packet received, UDCCSR0_OPC is raised and held until 2027 * cleared by software. 2028 * - clearing UDCCSR0_OPC always flushes ep0. If in setup stage, never do it 2029 * before reading ep0. 2030 * This is true only for PXA27x. This is not true anymore for PXA3xx family 2031 * (check Back-to-Back setup packet in developers guide). 2032 * - irq can be called on a "packet complete" event (opc_irq=1), while 2033 * UDCCSR0_OPC is not yet raised (delta can be as big as 100ms 2034 * from experimentation). 2035 * - as UDCCSR0_SA can be activated while in irq handling, and clearing 2036 * UDCCSR0_OPC would flush the setup data, we almost never clear UDCCSR0_OPC 2037 * => we never actually read the "status stage" packet of an IN data stage 2038 * => this is not documented in Intel documentation 2039 * - hardware as no idea of STATUS STAGE, it only handle SETUP STAGE and DATA 2040 * STAGE. The driver add STATUS STAGE to send last zero length packet in 2041 * OUT_STATUS_STAGE. 2042 * - special attention was needed for IN_STATUS_STAGE. If a packet complete 2043 * event is detected, we terminate the status stage without ackowledging the 2044 * packet (not to risk to loose a potential SETUP packet) 2045 */ 2046static void handle_ep0(struct pxa_udc *udc, int fifo_irq, int opc_irq) 2047{ 2048 u32 udccsr0; 2049 struct pxa_ep *ep = &udc->pxa_ep[0]; 2050 struct pxa27x_request *req = NULL; 2051 int completed = 0; 2052 2053 if (!list_empty(&ep->queue)) 2054 req = list_entry(ep->queue.next, struct pxa27x_request, queue); 2055 2056 udccsr0 = udc_ep_readl(ep, UDCCSR); 2057 ep_dbg(ep, "state=%s, req=%p, udccsr0=0x%03x, udcbcr=%d, irq_msk=%x\n", 2058 EP0_STNAME(udc), req, udccsr0, udc_ep_readl(ep, UDCBCR), 2059 (fifo_irq << 1 | opc_irq)); 2060 2061 if (udccsr0 & UDCCSR0_SST) { 2062 ep_dbg(ep, "clearing stall status\n"); 2063 nuke(ep, -EPIPE); 2064 ep_write_UDCCSR(ep, UDCCSR0_SST); 2065 ep0_idle(udc); 2066 } 2067 2068 if (udccsr0 & UDCCSR0_SA) { 2069 nuke(ep, 0); 2070 set_ep0state(udc, SETUP_STAGE); 2071 } 2072 2073 switch (udc->ep0state) { 2074 case WAIT_FOR_SETUP: 2075 /* 2076 * Hardware bug : beware, we cannot clear OPC, since we would 2077 * miss a potential OPC irq for a setup packet. 2078 * So, we only do ... nothing, and hope for a next irq with 2079 * UDCCSR0_SA set. 2080 */ 2081 break; 2082 case SETUP_STAGE: 2083 udccsr0 &= UDCCSR0_CTRL_REQ_MASK; 2084 if (likely(udccsr0 == UDCCSR0_CTRL_REQ_MASK)) 2085 handle_ep0_ctrl_req(udc, req); 2086 break; 2087 case IN_DATA_STAGE: /* GET_DESCRIPTOR */ 2088 if (epout_has_pkt(ep)) 2089 ep_write_UDCCSR(ep, UDCCSR0_OPC); 2090 if (req && !ep_is_full(ep)) 2091 completed = write_ep0_fifo(ep, req); 2092 if (completed) 2093 ep0_end_in_req(ep, req, NULL); 2094 break; 2095 case OUT_DATA_STAGE: /* SET_DESCRIPTOR */ 2096 if (epout_has_pkt(ep) && req) 2097 completed = read_ep0_fifo(ep, req); 2098 if (completed) 2099 ep0_end_out_req(ep, req, NULL); 2100 break; 2101 case STALL: 2102 ep_write_UDCCSR(ep, UDCCSR0_FST); 2103 break; 2104 case IN_STATUS_STAGE: 2105 /* 2106 * Hardware bug : beware, we cannot clear OPC, since we would 2107 * miss a potential PC irq for a setup packet. 2108 * So, we only put the ep0 into WAIT_FOR_SETUP state. 2109 */ 2110 if (opc_irq) 2111 ep0_idle(udc); 2112 break; 2113 case OUT_STATUS_STAGE: 2114 case WAIT_ACK_SET_CONF_INTERF: 2115 ep_warn(ep, "should never get in %s state here!!!\n", 2116 EP0_STNAME(ep->dev)); 2117 ep0_idle(udc); 2118 break; 2119 } 2120} 2121 2122/** 2123 * handle_ep - Handle endpoint data tranfers 2124 * @ep: pxa physical endpoint 2125 * 2126 * Tries to transfer all pending request data into the endpoint and/or 2127 * transfer all pending data in the endpoint into usb requests. 2128 * 2129 * Is always called when in_interrupt() and with ep->lock released. 2130 */ 2131static void handle_ep(struct pxa_ep *ep) 2132{ 2133 struct pxa27x_request *req; 2134 int completed; 2135 u32 udccsr; 2136 int is_in = ep->dir_in; 2137 int loop = 0; 2138 unsigned long flags; 2139 2140 spin_lock_irqsave(&ep->lock, flags); 2141 if (ep->in_handle_ep) 2142 goto recursion_detected; 2143 ep->in_handle_ep = 1; 2144 2145 do { 2146 completed = 0; 2147 udccsr = udc_ep_readl(ep, UDCCSR); 2148 2149 if (likely(!list_empty(&ep->queue))) 2150 req = list_entry(ep->queue.next, 2151 struct pxa27x_request, queue); 2152 else 2153 req = NULL; 2154 2155 ep_dbg(ep, "req:%p, udccsr 0x%03x loop=%d\n", 2156 req, udccsr, loop++); 2157 2158 if (unlikely(udccsr & (UDCCSR_SST | UDCCSR_TRN))) 2159 udc_ep_writel(ep, UDCCSR, 2160 udccsr & (UDCCSR_SST | UDCCSR_TRN)); 2161 if (!req) 2162 break; 2163 2164 if (unlikely(is_in)) { 2165 if (likely(!ep_is_full(ep))) 2166 completed = write_fifo(ep, req); 2167 } else { 2168 if (likely(epout_has_pkt(ep))) 2169 completed = read_fifo(ep, req); 2170 } 2171 2172 if (completed) { 2173 if (is_in) 2174 ep_end_in_req(ep, req, &flags); 2175 else 2176 ep_end_out_req(ep, req, &flags); 2177 } 2178 } while (completed); 2179 2180 ep->in_handle_ep = 0; 2181recursion_detected: 2182 spin_unlock_irqrestore(&ep->lock, flags); 2183} 2184 2185/** 2186 * pxa27x_change_configuration - Handle SET_CONF usb request notification 2187 * @udc: udc device 2188 * @config: usb configuration 2189 * 2190 * Post the request to upper level. 2191 * Don't use any pxa specific harware configuration capabilities 2192 */ 2193static void pxa27x_change_configuration(struct pxa_udc *udc, int config) 2194{ 2195 struct usb_ctrlrequest req ; 2196 2197 dev_dbg(udc->dev, "config=%d\n", config); 2198 2199 udc->config = config; 2200 udc->last_interface = 0; 2201 udc->last_alternate = 0; 2202 2203 req.bRequestType = 0; 2204 req.bRequest = USB_REQ_SET_CONFIGURATION; 2205 req.wValue = config; 2206 req.wIndex = 0; 2207 req.wLength = 0; 2208 2209 set_ep0state(udc, WAIT_ACK_SET_CONF_INTERF); 2210 udc->driver->setup(&udc->gadget, &req); 2211 ep_write_UDCCSR(&udc->pxa_ep[0], UDCCSR0_AREN); 2212} 2213 2214/** 2215 * pxa27x_change_interface - Handle SET_INTERF usb request notification 2216 * @udc: udc device 2217 * @iface: interface number 2218 * @alt: alternate setting number 2219 * 2220 * Post the request to upper level. 2221 * Don't use any pxa specific harware configuration capabilities 2222 */ 2223static void pxa27x_change_interface(struct pxa_udc *udc, int iface, int alt) 2224{ 2225 struct usb_ctrlrequest req; 2226 2227 dev_dbg(udc->dev, "interface=%d, alternate setting=%d\n", iface, alt); 2228 2229 udc->last_interface = iface; 2230 udc->last_alternate = alt; 2231 2232 req.bRequestType = USB_RECIP_INTERFACE; 2233 req.bRequest = USB_REQ_SET_INTERFACE; 2234 req.wValue = alt; 2235 req.wIndex = iface; 2236 req.wLength = 0; 2237 2238 set_ep0state(udc, WAIT_ACK_SET_CONF_INTERF); 2239 udc->driver->setup(&udc->gadget, &req); 2240 ep_write_UDCCSR(&udc->pxa_ep[0], UDCCSR0_AREN); 2241} 2242 2243/* 2244 * irq_handle_data - Handle data transfer 2245 * @irq: irq IRQ number 2246 * @udc: dev pxa_udc device structure 2247 * 2248 * Called from irq handler, transferts data to or from endpoint to queue 2249 */ 2250static void irq_handle_data(int irq, struct pxa_udc *udc) 2251{ 2252 int i; 2253 struct pxa_ep *ep; 2254 u32 udcisr0 = udc_readl(udc, UDCISR0) & UDCCISR0_EP_MASK; 2255 u32 udcisr1 = udc_readl(udc, UDCISR1) & UDCCISR1_EP_MASK; 2256 2257 if (udcisr0 & UDCISR_INT_MASK) { 2258 udc->pxa_ep[0].stats.irqs++; 2259 udc_writel(udc, UDCISR0, UDCISR_INT(0, UDCISR_INT_MASK)); 2260 handle_ep0(udc, !!(udcisr0 & UDCICR_FIFOERR), 2261 !!(udcisr0 & UDCICR_PKTCOMPL)); 2262 } 2263 2264 udcisr0 >>= 2; 2265 for (i = 1; udcisr0 != 0 && i < 16; udcisr0 >>= 2, i++) { 2266 if (!(udcisr0 & UDCISR_INT_MASK)) 2267 continue; 2268 2269 udc_writel(udc, UDCISR0, UDCISR_INT(i, UDCISR_INT_MASK)); 2270 2271 WARN_ON(i >= ARRAY_SIZE(udc->pxa_ep)); 2272 if (i < ARRAY_SIZE(udc->pxa_ep)) { 2273 ep = &udc->pxa_ep[i]; 2274 ep->stats.irqs++; 2275 handle_ep(ep); 2276 } 2277 } 2278 2279 for (i = 16; udcisr1 != 0 && i < 24; udcisr1 >>= 2, i++) { 2280 udc_writel(udc, UDCISR1, UDCISR_INT(i - 16, UDCISR_INT_MASK)); 2281 if (!(udcisr1 & UDCISR_INT_MASK)) 2282 continue; 2283 2284 WARN_ON(i >= ARRAY_SIZE(udc->pxa_ep)); 2285 if (i < ARRAY_SIZE(udc->pxa_ep)) { 2286 ep = &udc->pxa_ep[i]; 2287 ep->stats.irqs++; 2288 handle_ep(ep); 2289 } 2290 } 2291 2292} 2293 2294/** 2295 * irq_udc_suspend - Handle IRQ "UDC Suspend" 2296 * @udc: udc device 2297 */ 2298static void irq_udc_suspend(struct pxa_udc *udc) 2299{ 2300 udc_writel(udc, UDCISR1, UDCISR1_IRSU); 2301 udc->stats.irqs_suspend++; 2302 2303 if (udc->gadget.speed != USB_SPEED_UNKNOWN 2304 && udc->driver && udc->driver->suspend) 2305 udc->driver->suspend(&udc->gadget); 2306 ep0_idle(udc); 2307} 2308 2309/** 2310 * irq_udc_resume - Handle IRQ "UDC Resume" 2311 * @udc: udc device 2312 */ 2313static void irq_udc_resume(struct pxa_udc *udc) 2314{ 2315 udc_writel(udc, UDCISR1, UDCISR1_IRRU); 2316 udc->stats.irqs_resume++; 2317 2318 if (udc->gadget.speed != USB_SPEED_UNKNOWN 2319 && udc->driver && udc->driver->resume) 2320 udc->driver->resume(&udc->gadget); 2321} 2322 2323/** 2324 * irq_udc_reconfig - Handle IRQ "UDC Change Configuration" 2325 * @udc: udc device 2326 */ 2327static void irq_udc_reconfig(struct pxa_udc *udc) 2328{ 2329 unsigned config, interface, alternate, config_change; 2330 u32 udccr = udc_readl(udc, UDCCR); 2331 2332 udc_writel(udc, UDCISR1, UDCISR1_IRCC); 2333 udc->stats.irqs_reconfig++; 2334 2335 config = (udccr & UDCCR_ACN) >> UDCCR_ACN_S; 2336 config_change = (config != udc->config); 2337 pxa27x_change_configuration(udc, config); 2338 2339 interface = (udccr & UDCCR_AIN) >> UDCCR_AIN_S; 2340 alternate = (udccr & UDCCR_AAISN) >> UDCCR_AAISN_S; 2341 pxa27x_change_interface(udc, interface, alternate); 2342 2343 if (config_change) 2344 update_pxa_ep_matches(udc); 2345 udc_set_mask_UDCCR(udc, UDCCR_SMAC); 2346} 2347 2348/** 2349 * irq_udc_reset - Handle IRQ "UDC Reset" 2350 * @udc: udc device 2351 */ 2352static void irq_udc_reset(struct pxa_udc *udc) 2353{ 2354 u32 udccr = udc_readl(udc, UDCCR); 2355 struct pxa_ep *ep = &udc->pxa_ep[0]; 2356 2357 dev_info(udc->dev, "USB reset\n"); 2358 udc_writel(udc, UDCISR1, UDCISR1_IRRS); 2359 udc->stats.irqs_reset++; 2360 2361 if ((udccr & UDCCR_UDA) == 0) { 2362 dev_dbg(udc->dev, "USB reset start\n"); 2363 stop_activity(udc, udc->driver); 2364 } 2365 udc->gadget.speed = USB_SPEED_FULL; 2366 memset(&udc->stats, 0, sizeof udc->stats); 2367 2368 nuke(ep, -EPROTO); 2369 ep_write_UDCCSR(ep, UDCCSR0_FTF | UDCCSR0_OPC); 2370 ep0_idle(udc); 2371} 2372 2373/** 2374 * pxa_udc_irq - Main irq handler 2375 * @irq: irq number 2376 * @_dev: udc device 2377 * 2378 * Handles all udc interrupts 2379 */ 2380static irqreturn_t pxa_udc_irq(int irq, void *_dev) 2381{ 2382 struct pxa_udc *udc = _dev; 2383 u32 udcisr0 = udc_readl(udc, UDCISR0); 2384 u32 udcisr1 = udc_readl(udc, UDCISR1); 2385 u32 udccr = udc_readl(udc, UDCCR); 2386 u32 udcisr1_spec; 2387 2388 dev_vdbg(udc->dev, "Interrupt, UDCISR0:0x%08x, UDCISR1:0x%08x, " 2389 "UDCCR:0x%08x\n", udcisr0, udcisr1, udccr); 2390 2391 udcisr1_spec = udcisr1 & 0xf8000000; 2392 if (unlikely(udcisr1_spec & UDCISR1_IRSU)) 2393 irq_udc_suspend(udc); 2394 if (unlikely(udcisr1_spec & UDCISR1_IRRU)) 2395 irq_udc_resume(udc); 2396 if (unlikely(udcisr1_spec & UDCISR1_IRCC)) 2397 irq_udc_reconfig(udc); 2398 if (unlikely(udcisr1_spec & UDCISR1_IRRS)) 2399 irq_udc_reset(udc); 2400 2401 if ((udcisr0 & UDCCISR0_EP_MASK) | (udcisr1 & UDCCISR1_EP_MASK)) 2402 irq_handle_data(irq, udc); 2403 2404 return IRQ_HANDLED; 2405} 2406 2407static struct pxa_udc memory = { 2408 .gadget = { 2409 .ops = &pxa_udc_ops, 2410 .ep0 = &memory.udc_usb_ep[0].usb_ep, 2411 .name = driver_name, 2412 .dev = { 2413 .init_name = "gadget", 2414 }, 2415 }, 2416 2417 .udc_usb_ep = { 2418 USB_EP_CTRL, 2419 USB_EP_OUT_BULK(1), 2420 USB_EP_IN_BULK(2), 2421 USB_EP_IN_ISO(3), 2422 USB_EP_OUT_ISO(4), 2423 USB_EP_IN_INT(5), 2424 }, 2425 2426 .pxa_ep = { 2427 PXA_EP_CTRL, 2428 /* Endpoints for gadget zero */ 2429 PXA_EP_OUT_BULK(1, 1, 3, 0, 0), 2430 PXA_EP_IN_BULK(2, 2, 3, 0, 0), 2431 /* Endpoints for ether gadget, file storage gadget */ 2432 PXA_EP_OUT_BULK(3, 1, 1, 0, 0), 2433 PXA_EP_IN_BULK(4, 2, 1, 0, 0), 2434 PXA_EP_IN_ISO(5, 3, 1, 0, 0), 2435 PXA_EP_OUT_ISO(6, 4, 1, 0, 0), 2436 PXA_EP_IN_INT(7, 5, 1, 0, 0), 2437 /* Endpoints for RNDIS, serial */ 2438 PXA_EP_OUT_BULK(8, 1, 2, 0, 0), 2439 PXA_EP_IN_BULK(9, 2, 2, 0, 0), 2440 PXA_EP_IN_INT(10, 5, 2, 0, 0), 2441 /* 2442 * All the following endpoints are only for completion. They 2443 * won't never work, as multiple interfaces are really broken on 2444 * the pxa. 2445 */ 2446 PXA_EP_OUT_BULK(11, 1, 2, 1, 0), 2447 PXA_EP_IN_BULK(12, 2, 2, 1, 0), 2448 /* Endpoint for CDC Ether */ 2449 PXA_EP_OUT_BULK(13, 1, 1, 1, 1), 2450 PXA_EP_IN_BULK(14, 2, 1, 1, 1), 2451 } 2452}; 2453 2454/** 2455 * pxa_udc_probe - probes the udc device 2456 * @_dev: platform device 2457 * 2458 * Perform basic init : allocates udc clock, creates sysfs files, requests 2459 * irq. 2460 */ 2461static int __init pxa_udc_probe(struct platform_device *pdev) 2462{ 2463 struct resource *regs; 2464 struct pxa_udc *udc = &memory; 2465 int retval = 0, gpio; 2466 2467 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2468 if (!regs) 2469 return -ENXIO; 2470 udc->irq = platform_get_irq(pdev, 0); 2471 if (udc->irq < 0) 2472 return udc->irq; 2473 2474 udc->dev = &pdev->dev; 2475 udc->mach = pdev->dev.platform_data; 2476 udc->transceiver = otg_get_transceiver(); 2477 2478 gpio = udc->mach->gpio_pullup; 2479 if (gpio_is_valid(gpio)) { 2480 retval = gpio_request(gpio, "USB D+ pullup"); 2481 if (retval == 0) 2482 gpio_direction_output(gpio, 2483 udc->mach->gpio_pullup_inverted); 2484 } 2485 if (retval) { 2486 dev_err(&pdev->dev, "Couldn't request gpio %d : %d\n", 2487 gpio, retval); 2488 return retval; 2489 } 2490 2491 udc->clk = clk_get(&pdev->dev, NULL); 2492 if (IS_ERR(udc->clk)) { 2493 retval = PTR_ERR(udc->clk); 2494 goto err_clk; 2495 } 2496 2497 retval = -ENOMEM; 2498 udc->regs = ioremap(regs->start, resource_size(regs)); 2499 if (!udc->regs) { 2500 dev_err(&pdev->dev, "Unable to map UDC I/O memory\n"); 2501 goto err_map; 2502 } 2503 2504 device_initialize(&udc->gadget.dev); 2505 udc->gadget.dev.parent = &pdev->dev; 2506 udc->gadget.dev.dma_mask = NULL; 2507 udc->vbus_sensed = 0; 2508 2509 the_controller = udc; 2510 platform_set_drvdata(pdev, udc); 2511 udc_init_data(udc); 2512 pxa_eps_setup(udc); 2513 2514 /* irq setup after old hardware state is cleaned up */ 2515 retval = request_irq(udc->irq, pxa_udc_irq, 2516 IRQF_SHARED, driver_name, udc); 2517 if (retval != 0) { 2518 dev_err(udc->dev, "%s: can't get irq %i, err %d\n", 2519 driver_name, IRQ_USB, retval); 2520 goto err_irq; 2521 } 2522 retval = usb_add_gadget_udc(&pdev->dev, &udc->gadget); 2523 if (retval) 2524 goto err_add_udc; 2525 2526 pxa_init_debugfs(udc); 2527 return 0; 2528err_add_udc: 2529 free_irq(udc->irq, udc); 2530err_irq: 2531 iounmap(udc->regs); 2532err_map: 2533 clk_put(udc->clk); 2534 udc->clk = NULL; 2535err_clk: 2536 return retval; 2537} 2538 2539/** 2540 * pxa_udc_remove - removes the udc device driver 2541 * @_dev: platform device 2542 */ 2543static int __exit pxa_udc_remove(struct platform_device *_dev) 2544{ 2545 struct pxa_udc *udc = platform_get_drvdata(_dev); 2546 int gpio = udc->mach->gpio_pullup; 2547 2548 usb_del_gadget_udc(&udc->gadget); 2549 usb_gadget_unregister_driver(udc->driver); 2550 free_irq(udc->irq, udc); 2551 pxa_cleanup_debugfs(udc); 2552 if (gpio_is_valid(gpio)) 2553 gpio_free(gpio); 2554 2555 otg_put_transceiver(udc->transceiver); 2556 2557 udc->transceiver = NULL; 2558 platform_set_drvdata(_dev, NULL); 2559 the_controller = NULL; 2560 clk_put(udc->clk); 2561 iounmap(udc->regs); 2562 2563 return 0; 2564} 2565 2566static void pxa_udc_shutdown(struct platform_device *_dev) 2567{ 2568 struct pxa_udc *udc = platform_get_drvdata(_dev); 2569 2570 if (udc_readl(udc, UDCCR) & UDCCR_UDE) 2571 udc_disable(udc); 2572} 2573 2574#ifdef CONFIG_PXA27x 2575extern void pxa27x_clear_otgph(void); 2576#else 2577#define pxa27x_clear_otgph() do {} while (0) 2578#endif 2579 2580#ifdef CONFIG_PM 2581/** 2582 * pxa_udc_suspend - Suspend udc device 2583 * @_dev: platform device 2584 * @state: suspend state 2585 * 2586 * Suspends udc : saves configuration registers (UDCCR*), then disables the udc 2587 * device. 2588 */ 2589static int pxa_udc_suspend(struct platform_device *_dev, pm_message_t state) 2590{ 2591 int i; 2592 struct pxa_udc *udc = platform_get_drvdata(_dev); 2593 struct pxa_ep *ep; 2594 2595 ep = &udc->pxa_ep[0]; 2596 udc->udccsr0 = udc_ep_readl(ep, UDCCSR); 2597 for (i = 1; i < NR_PXA_ENDPOINTS; i++) { 2598 ep = &udc->pxa_ep[i]; 2599 ep->udccsr_value = udc_ep_readl(ep, UDCCSR); 2600 ep->udccr_value = udc_ep_readl(ep, UDCCR); 2601 ep_dbg(ep, "udccsr:0x%03x, udccr:0x%x\n", 2602 ep->udccsr_value, ep->udccr_value); 2603 } 2604 2605 udc_disable(udc); 2606 udc->pullup_resume = udc->pullup_on; 2607 dplus_pullup(udc, 0); 2608 2609 return 0; 2610} 2611 2612/** 2613 * pxa_udc_resume - Resume udc device 2614 * @_dev: platform device 2615 * 2616 * Resumes udc : restores configuration registers (UDCCR*), then enables the udc 2617 * device. 2618 */ 2619static int pxa_udc_resume(struct platform_device *_dev) 2620{ 2621 int i; 2622 struct pxa_udc *udc = platform_get_drvdata(_dev); 2623 struct pxa_ep *ep; 2624 2625 ep = &udc->pxa_ep[0]; 2626 udc_ep_writel(ep, UDCCSR, udc->udccsr0 & (UDCCSR0_FST | UDCCSR0_DME)); 2627 for (i = 1; i < NR_PXA_ENDPOINTS; i++) { 2628 ep = &udc->pxa_ep[i]; 2629 udc_ep_writel(ep, UDCCSR, ep->udccsr_value); 2630 udc_ep_writel(ep, UDCCR, ep->udccr_value); 2631 ep_dbg(ep, "udccsr:0x%03x, udccr:0x%x\n", 2632 ep->udccsr_value, ep->udccr_value); 2633 } 2634 2635 dplus_pullup(udc, udc->pullup_resume); 2636 if (should_enable_udc(udc)) 2637 udc_enable(udc); 2638 /* 2639 * We do not handle OTG yet. 2640 * 2641 * OTGPH bit is set when sleep mode is entered. 2642 * it indicates that OTG pad is retaining its state. 2643 * Upon exit from sleep mode and before clearing OTGPH, 2644 * Software must configure the USB OTG pad, UDC, and UHC 2645 * to the state they were in before entering sleep mode. 2646 */ 2647 pxa27x_clear_otgph(); 2648 2649 return 0; 2650} 2651#endif 2652 2653/* work with hotplug and coldplug */ 2654MODULE_ALIAS("platform:pxa27x-udc"); 2655 2656static struct platform_driver udc_driver = { 2657 .driver = { 2658 .name = "pxa27x-udc", 2659 .owner = THIS_MODULE, 2660 }, 2661 .remove = __exit_p(pxa_udc_remove), 2662 .shutdown = pxa_udc_shutdown, 2663#ifdef CONFIG_PM 2664 .suspend = pxa_udc_suspend, 2665 .resume = pxa_udc_resume 2666#endif 2667}; 2668 2669static int __init udc_init(void) 2670{ 2671 if (!cpu_is_pxa27x() && !cpu_is_pxa3xx()) 2672 return -ENODEV; 2673 2674 printk(KERN_INFO "%s: version %s\n", driver_name, DRIVER_VERSION); 2675 return platform_driver_probe(&udc_driver, pxa_udc_probe); 2676} 2677module_init(udc_init); 2678 2679 2680static void __exit udc_exit(void) 2681{ 2682 platform_driver_unregister(&udc_driver); 2683} 2684module_exit(udc_exit); 2685 2686MODULE_DESCRIPTION(DRIVER_DESC); 2687MODULE_AUTHOR("Robert Jarzmik"); 2688MODULE_LICENSE("GPL");