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1#ifndef _ASM_X86_IO_APIC_H
2#define _ASM_X86_IO_APIC_H
3
4#include <linux/types.h>
5#include <asm/mpspec.h>
6#include <asm/apicdef.h>
7#include <asm/irq_vectors.h>
8
9/*
10 * Intel IO-APIC support for SMP and UP systems.
11 *
12 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
13 */
14
15/* I/O Unit Redirection Table */
16#define IO_APIC_REDIR_VECTOR_MASK 0x000FF
17#define IO_APIC_REDIR_DEST_LOGICAL 0x00800
18#define IO_APIC_REDIR_DEST_PHYSICAL 0x00000
19#define IO_APIC_REDIR_SEND_PENDING (1 << 12)
20#define IO_APIC_REDIR_REMOTE_IRR (1 << 14)
21#define IO_APIC_REDIR_LEVEL_TRIGGER (1 << 15)
22#define IO_APIC_REDIR_MASKED (1 << 16)
23
24/*
25 * The structure of the IO-APIC:
26 */
27union IO_APIC_reg_00 {
28 u32 raw;
29 struct {
30 u32 __reserved_2 : 14,
31 LTS : 1,
32 delivery_type : 1,
33 __reserved_1 : 8,
34 ID : 8;
35 } __attribute__ ((packed)) bits;
36};
37
38union IO_APIC_reg_01 {
39 u32 raw;
40 struct {
41 u32 version : 8,
42 __reserved_2 : 7,
43 PRQ : 1,
44 entries : 8,
45 __reserved_1 : 8;
46 } __attribute__ ((packed)) bits;
47};
48
49union IO_APIC_reg_02 {
50 u32 raw;
51 struct {
52 u32 __reserved_2 : 24,
53 arbitration : 4,
54 __reserved_1 : 4;
55 } __attribute__ ((packed)) bits;
56};
57
58union IO_APIC_reg_03 {
59 u32 raw;
60 struct {
61 u32 boot_DT : 1,
62 __reserved_1 : 31;
63 } __attribute__ ((packed)) bits;
64};
65
66struct IO_APIC_route_entry {
67 __u32 vector : 8,
68 delivery_mode : 3, /* 000: FIXED
69 * 001: lowest prio
70 * 111: ExtINT
71 */
72 dest_mode : 1, /* 0: physical, 1: logical */
73 delivery_status : 1,
74 polarity : 1,
75 irr : 1,
76 trigger : 1, /* 0: edge, 1: level */
77 mask : 1, /* 0: enabled, 1: disabled */
78 __reserved_2 : 15;
79
80 __u32 __reserved_3 : 24,
81 dest : 8;
82} __attribute__ ((packed));
83
84struct IR_IO_APIC_route_entry {
85 __u64 vector : 8,
86 zero : 3,
87 index2 : 1,
88 delivery_status : 1,
89 polarity : 1,
90 irr : 1,
91 trigger : 1,
92 mask : 1,
93 reserved : 31,
94 format : 1,
95 index : 15;
96} __attribute__ ((packed));
97
98#define IOAPIC_AUTO -1
99#define IOAPIC_EDGE 0
100#define IOAPIC_LEVEL 1
101
102#ifdef CONFIG_X86_IO_APIC
103
104/*
105 * # of IO-APICs and # of IRQ routing registers
106 */
107extern int nr_ioapics;
108
109extern int mpc_ioapic_id(int ioapic);
110extern unsigned int mpc_ioapic_addr(int ioapic);
111extern struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic);
112
113#define MP_MAX_IOAPIC_PIN 127
114
115/* # of MP IRQ source entries */
116extern int mp_irq_entries;
117
118/* MP IRQ source entries */
119extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
120
121/* non-0 if default (table-less) MP configuration */
122extern int mpc_default_type;
123
124/* Older SiS APIC requires we rewrite the index register */
125extern int sis_apic_bug;
126
127/* 1 if "noapic" boot option passed */
128extern int skip_ioapic_setup;
129
130/* 1 if "noapic" boot option passed */
131extern int noioapicquirk;
132
133/* -1 if "noapic" boot option passed */
134extern int noioapicreroute;
135
136/* 1 if the timer IRQ uses the '8259A Virtual Wire' mode */
137extern int timer_through_8259;
138
139/*
140 * If we use the IO-APIC for IRQ routing, disable automatic
141 * assignment of PCI IRQ's.
142 */
143#define io_apic_assign_pci_irqs \
144 (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
145
146struct io_apic_irq_attr;
147extern int io_apic_set_pci_routing(struct device *dev, int irq,
148 struct io_apic_irq_attr *irq_attr);
149void setup_IO_APIC_irq_extra(u32 gsi);
150extern void ioapic_and_gsi_init(void);
151extern void ioapic_insert_resources(void);
152
153int io_apic_setup_irq_pin_once(unsigned int irq, int node, struct io_apic_irq_attr *attr);
154
155extern int save_ioapic_entries(void);
156extern void mask_ioapic_entries(void);
157extern int restore_ioapic_entries(void);
158
159extern int get_nr_irqs_gsi(void);
160
161extern void setup_ioapic_ids_from_mpc(void);
162extern void setup_ioapic_ids_from_mpc_nocheck(void);
163
164struct mp_ioapic_gsi{
165 u32 gsi_base;
166 u32 gsi_end;
167};
168extern struct mp_ioapic_gsi mp_gsi_routing[];
169extern u32 gsi_top;
170int mp_find_ioapic(u32 gsi);
171int mp_find_ioapic_pin(int ioapic, u32 gsi);
172void __init mp_register_ioapic(int id, u32 address, u32 gsi_base);
173extern void __init pre_init_apic_IRQ0(void);
174
175extern void mp_save_irq(struct mpc_intsrc *m);
176
177extern void disable_ioapic_support(void);
178
179#else /* !CONFIG_X86_IO_APIC */
180
181#define io_apic_assign_pci_irqs 0
182#define setup_ioapic_ids_from_mpc x86_init_noop
183static const int timer_through_8259 = 0;
184static inline void ioapic_and_gsi_init(void) { }
185static inline void ioapic_insert_resources(void) { }
186#define gsi_top (NR_IRQS_LEGACY)
187static inline int mp_find_ioapic(u32 gsi) { return 0; }
188
189struct io_apic_irq_attr;
190static inline int io_apic_set_pci_routing(struct device *dev, int irq,
191 struct io_apic_irq_attr *irq_attr) { return 0; }
192
193static inline int save_ioapic_entries(void)
194{
195 return -ENOMEM;
196}
197
198static inline void mask_ioapic_entries(void) { }
199static inline int restore_ioapic_entries(void)
200{
201 return -ENOMEM;
202}
203
204static inline void mp_save_irq(struct mpc_intsrc *m) { };
205static inline void disable_ioapic_support(void) { }
206#endif
207
208#endif /* _ASM_X86_IO_APIC_H */