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1/* 2 * omap_wdt.c 3 * 4 * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog 5 * 6 * Author: MontaVista Software, Inc. 7 * <gdavis@mvista.com> or <source@mvista.com> 8 * 9 * 2003 (c) MontaVista Software, Inc. This file is licensed under the 10 * terms of the GNU General Public License version 2. This program is 11 * licensed "as is" without any warranty of any kind, whether express 12 * or implied. 13 * 14 * History: 15 * 16 * 20030527: George G. Davis <gdavis@mvista.com> 17 * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c 18 * (c) Copyright 2000 Oleg Drokin <green@crimea.edu> 19 * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk> 20 * 21 * Copyright (c) 2004 Texas Instruments. 22 * 1. Modified to support OMAP1610 32-KHz watchdog timer 23 * 2. Ported to 2.6 kernel 24 * 25 * Copyright (c) 2005 David Brownell 26 * Use the driver model and standard identifiers; handle bigger timeouts. 27 */ 28 29#include <linux/module.h> 30#include <linux/types.h> 31#include <linux/kernel.h> 32#include <linux/fs.h> 33#include <linux/mm.h> 34#include <linux/miscdevice.h> 35#include <linux/watchdog.h> 36#include <linux/reboot.h> 37#include <linux/init.h> 38#include <linux/err.h> 39#include <linux/platform_device.h> 40#include <linux/moduleparam.h> 41#include <linux/bitops.h> 42#include <linux/io.h> 43#include <linux/uaccess.h> 44#include <linux/slab.h> 45#include <linux/pm_runtime.h> 46#include <mach/hardware.h> 47#include <plat/prcm.h> 48 49#include "omap_wdt.h" 50 51static struct platform_device *omap_wdt_dev; 52 53static unsigned timer_margin; 54module_param(timer_margin, uint, 0); 55MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)"); 56 57static unsigned int wdt_trgr_pattern = 0x1234; 58static spinlock_t wdt_lock; 59 60struct omap_wdt_dev { 61 void __iomem *base; /* physical */ 62 struct device *dev; 63 int omap_wdt_users; 64 struct resource *mem; 65 struct miscdevice omap_wdt_miscdev; 66}; 67 68static void omap_wdt_ping(struct omap_wdt_dev *wdev) 69{ 70 void __iomem *base = wdev->base; 71 72 /* wait for posted write to complete */ 73 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08) 74 cpu_relax(); 75 76 wdt_trgr_pattern = ~wdt_trgr_pattern; 77 __raw_writel(wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR)); 78 79 /* wait for posted write to complete */ 80 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08) 81 cpu_relax(); 82 /* reloaded WCRR from WLDR */ 83} 84 85static void omap_wdt_enable(struct omap_wdt_dev *wdev) 86{ 87 void __iomem *base = wdev->base; 88 89 /* Sequence to enable the watchdog */ 90 __raw_writel(0xBBBB, base + OMAP_WATCHDOG_SPR); 91 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10) 92 cpu_relax(); 93 94 __raw_writel(0x4444, base + OMAP_WATCHDOG_SPR); 95 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10) 96 cpu_relax(); 97} 98 99static void omap_wdt_disable(struct omap_wdt_dev *wdev) 100{ 101 void __iomem *base = wdev->base; 102 103 /* sequence required to disable watchdog */ 104 __raw_writel(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ 105 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10) 106 cpu_relax(); 107 108 __raw_writel(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ 109 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10) 110 cpu_relax(); 111} 112 113static void omap_wdt_adjust_timeout(unsigned new_timeout) 114{ 115 if (new_timeout < TIMER_MARGIN_MIN) 116 new_timeout = TIMER_MARGIN_DEFAULT; 117 if (new_timeout > TIMER_MARGIN_MAX) 118 new_timeout = TIMER_MARGIN_MAX; 119 timer_margin = new_timeout; 120} 121 122static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev) 123{ 124 u32 pre_margin = GET_WLDR_VAL(timer_margin); 125 void __iomem *base = wdev->base; 126 127 pm_runtime_get_sync(wdev->dev); 128 129 /* just count up at 32 KHz */ 130 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04) 131 cpu_relax(); 132 133 __raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR); 134 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04) 135 cpu_relax(); 136 137 pm_runtime_put_sync(wdev->dev); 138} 139 140/* 141 * Allow only one task to hold it open 142 */ 143static int omap_wdt_open(struct inode *inode, struct file *file) 144{ 145 struct omap_wdt_dev *wdev = platform_get_drvdata(omap_wdt_dev); 146 void __iomem *base = wdev->base; 147 148 if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users))) 149 return -EBUSY; 150 151 pm_runtime_get_sync(wdev->dev); 152 153 /* initialize prescaler */ 154 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01) 155 cpu_relax(); 156 157 __raw_writel((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL); 158 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01) 159 cpu_relax(); 160 161 file->private_data = (void *) wdev; 162 163 omap_wdt_set_timeout(wdev); 164 omap_wdt_ping(wdev); /* trigger loading of new timeout value */ 165 omap_wdt_enable(wdev); 166 167 pm_runtime_put_sync(wdev->dev); 168 169 return nonseekable_open(inode, file); 170} 171 172static int omap_wdt_release(struct inode *inode, struct file *file) 173{ 174 struct omap_wdt_dev *wdev = file->private_data; 175 176 /* 177 * Shut off the timer unless NOWAYOUT is defined. 178 */ 179#ifndef CONFIG_WATCHDOG_NOWAYOUT 180 pm_runtime_get_sync(wdev->dev); 181 182 omap_wdt_disable(wdev); 183 184 pm_runtime_put_sync(wdev->dev); 185#else 186 printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n"); 187#endif 188 wdev->omap_wdt_users = 0; 189 190 return 0; 191} 192 193static ssize_t omap_wdt_write(struct file *file, const char __user *data, 194 size_t len, loff_t *ppos) 195{ 196 struct omap_wdt_dev *wdev = file->private_data; 197 198 /* Refresh LOAD_TIME. */ 199 if (len) { 200 pm_runtime_get_sync(wdev->dev); 201 spin_lock(&wdt_lock); 202 omap_wdt_ping(wdev); 203 spin_unlock(&wdt_lock); 204 pm_runtime_put_sync(wdev->dev); 205 } 206 return len; 207} 208 209static long omap_wdt_ioctl(struct file *file, unsigned int cmd, 210 unsigned long arg) 211{ 212 struct omap_wdt_dev *wdev; 213 int new_margin; 214 static const struct watchdog_info ident = { 215 .identity = "OMAP Watchdog", 216 .options = WDIOF_SETTIMEOUT, 217 .firmware_version = 0, 218 }; 219 220 wdev = file->private_data; 221 222 switch (cmd) { 223 case WDIOC_GETSUPPORT: 224 return copy_to_user((struct watchdog_info __user *)arg, &ident, 225 sizeof(ident)); 226 case WDIOC_GETSTATUS: 227 return put_user(0, (int __user *)arg); 228 case WDIOC_GETBOOTSTATUS: 229 if (cpu_is_omap16xx()) 230 return put_user(__raw_readw(ARM_SYSST), 231 (int __user *)arg); 232 if (cpu_is_omap24xx()) 233 return put_user(omap_prcm_get_reset_sources(), 234 (int __user *)arg); 235 case WDIOC_KEEPALIVE: 236 pm_runtime_get_sync(wdev->dev); 237 spin_lock(&wdt_lock); 238 omap_wdt_ping(wdev); 239 spin_unlock(&wdt_lock); 240 pm_runtime_put_sync(wdev->dev); 241 return 0; 242 case WDIOC_SETTIMEOUT: 243 if (get_user(new_margin, (int __user *)arg)) 244 return -EFAULT; 245 omap_wdt_adjust_timeout(new_margin); 246 247 pm_runtime_get_sync(wdev->dev); 248 spin_lock(&wdt_lock); 249 omap_wdt_disable(wdev); 250 omap_wdt_set_timeout(wdev); 251 omap_wdt_enable(wdev); 252 253 omap_wdt_ping(wdev); 254 spin_unlock(&wdt_lock); 255 pm_runtime_put_sync(wdev->dev); 256 /* Fall */ 257 case WDIOC_GETTIMEOUT: 258 return put_user(timer_margin, (int __user *)arg); 259 default: 260 return -ENOTTY; 261 } 262} 263 264static const struct file_operations omap_wdt_fops = { 265 .owner = THIS_MODULE, 266 .write = omap_wdt_write, 267 .unlocked_ioctl = omap_wdt_ioctl, 268 .open = omap_wdt_open, 269 .release = omap_wdt_release, 270 .llseek = no_llseek, 271}; 272 273static int __devinit omap_wdt_probe(struct platform_device *pdev) 274{ 275 struct resource *res, *mem; 276 struct omap_wdt_dev *wdev; 277 int ret; 278 279 /* reserve static register mappings */ 280 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 281 if (!res) { 282 ret = -ENOENT; 283 goto err_get_resource; 284 } 285 286 if (omap_wdt_dev) { 287 ret = -EBUSY; 288 goto err_busy; 289 } 290 291 mem = request_mem_region(res->start, resource_size(res), pdev->name); 292 if (!mem) { 293 ret = -EBUSY; 294 goto err_busy; 295 } 296 297 wdev = kzalloc(sizeof(struct omap_wdt_dev), GFP_KERNEL); 298 if (!wdev) { 299 ret = -ENOMEM; 300 goto err_kzalloc; 301 } 302 303 wdev->omap_wdt_users = 0; 304 wdev->mem = mem; 305 wdev->dev = &pdev->dev; 306 307 wdev->base = ioremap(res->start, resource_size(res)); 308 if (!wdev->base) { 309 ret = -ENOMEM; 310 goto err_ioremap; 311 } 312 313 platform_set_drvdata(pdev, wdev); 314 315 pm_runtime_enable(wdev->dev); 316 pm_runtime_get_sync(wdev->dev); 317 318 omap_wdt_disable(wdev); 319 omap_wdt_adjust_timeout(timer_margin); 320 321 wdev->omap_wdt_miscdev.parent = &pdev->dev; 322 wdev->omap_wdt_miscdev.minor = WATCHDOG_MINOR; 323 wdev->omap_wdt_miscdev.name = "watchdog"; 324 wdev->omap_wdt_miscdev.fops = &omap_wdt_fops; 325 326 ret = misc_register(&(wdev->omap_wdt_miscdev)); 327 if (ret) 328 goto err_misc; 329 330 pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n", 331 __raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF, 332 timer_margin); 333 334 pm_runtime_put_sync(wdev->dev); 335 336 omap_wdt_dev = pdev; 337 338 return 0; 339 340err_misc: 341 platform_set_drvdata(pdev, NULL); 342 iounmap(wdev->base); 343 344err_ioremap: 345 wdev->base = NULL; 346 kfree(wdev); 347 348err_kzalloc: 349 release_mem_region(res->start, resource_size(res)); 350 351err_busy: 352err_get_resource: 353 354 return ret; 355} 356 357static void omap_wdt_shutdown(struct platform_device *pdev) 358{ 359 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev); 360 361 if (wdev->omap_wdt_users) { 362 pm_runtime_get_sync(wdev->dev); 363 omap_wdt_disable(wdev); 364 pm_runtime_put_sync(wdev->dev); 365 } 366} 367 368static int __devexit omap_wdt_remove(struct platform_device *pdev) 369{ 370 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev); 371 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 372 373 if (!res) 374 return -ENOENT; 375 376 misc_deregister(&(wdev->omap_wdt_miscdev)); 377 release_mem_region(res->start, resource_size(res)); 378 platform_set_drvdata(pdev, NULL); 379 380 iounmap(wdev->base); 381 382 kfree(wdev); 383 omap_wdt_dev = NULL; 384 385 return 0; 386} 387 388#ifdef CONFIG_PM 389 390/* REVISIT ... not clear this is the best way to handle system suspend; and 391 * it's very inappropriate for selective device suspend (e.g. suspending this 392 * through sysfs rather than by stopping the watchdog daemon). Also, this 393 * may not play well enough with NOWAYOUT... 394 */ 395 396static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state) 397{ 398 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev); 399 400 if (wdev->omap_wdt_users) { 401 pm_runtime_get_sync(wdev->dev); 402 omap_wdt_disable(wdev); 403 pm_runtime_put_sync(wdev->dev); 404 } 405 406 return 0; 407} 408 409static int omap_wdt_resume(struct platform_device *pdev) 410{ 411 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev); 412 413 if (wdev->omap_wdt_users) { 414 pm_runtime_get_sync(wdev->dev); 415 omap_wdt_enable(wdev); 416 omap_wdt_ping(wdev); 417 pm_runtime_put_sync(wdev->dev); 418 } 419 420 return 0; 421} 422 423#else 424#define omap_wdt_suspend NULL 425#define omap_wdt_resume NULL 426#endif 427 428static struct platform_driver omap_wdt_driver = { 429 .probe = omap_wdt_probe, 430 .remove = __devexit_p(omap_wdt_remove), 431 .shutdown = omap_wdt_shutdown, 432 .suspend = omap_wdt_suspend, 433 .resume = omap_wdt_resume, 434 .driver = { 435 .owner = THIS_MODULE, 436 .name = "omap_wdt", 437 }, 438}; 439 440static int __init omap_wdt_init(void) 441{ 442 spin_lock_init(&wdt_lock); 443 return platform_driver_register(&omap_wdt_driver); 444} 445 446static void __exit omap_wdt_exit(void) 447{ 448 platform_driver_unregister(&omap_wdt_driver); 449} 450 451module_init(omap_wdt_init); 452module_exit(omap_wdt_exit); 453 454MODULE_AUTHOR("George G. Davis"); 455MODULE_LICENSE("GPL"); 456MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); 457MODULE_ALIAS("platform:omap_wdt");