tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34
35#include <linux/if_vlan.h>
36
37#include <linux/mlx4/device.h>
38#include <linux/mlx4/cmd.h>
39
40#include "en_port.h"
41#include "mlx4_en.h"
42
43
44int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port,
45 u64 mac, u64 clear, u8 mode)
46{
47 return mlx4_cmd(dev, (mac | (clear << 63)), port, mode,
48 MLX4_CMD_SET_MCAST_FLTR, MLX4_CMD_TIME_CLASS_B);
49}
50
51int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv)
52{
53 struct mlx4_cmd_mailbox *mailbox;
54 struct mlx4_set_vlan_fltr_mbox *filter;
55 int i;
56 int j;
57 int index = 0;
58 u32 entry;
59 int err = 0;
60
61 mailbox = mlx4_alloc_cmd_mailbox(dev);
62 if (IS_ERR(mailbox))
63 return PTR_ERR(mailbox);
64
65 filter = mailbox->buf;
66 memset(filter, 0, sizeof(*filter));
67 for (i = VLAN_FLTR_SIZE - 1; i >= 0; i--) {
68 entry = 0;
69 for (j = 0; j < 32; j++)
70 if (test_bit(index++, priv->active_vlans))
71 entry |= 1 << j;
72 filter->entry[i] = cpu_to_be32(entry);
73 }
74 err = mlx4_cmd(dev, mailbox->dma, priv->port, 0, MLX4_CMD_SET_VLAN_FLTR,
75 MLX4_CMD_TIME_CLASS_B);
76 mlx4_free_cmd_mailbox(dev, mailbox);
77 return err;
78}
79
80
81int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
82 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx)
83{
84 struct mlx4_cmd_mailbox *mailbox;
85 struct mlx4_set_port_general_context *context;
86 int err;
87 u32 in_mod;
88
89 mailbox = mlx4_alloc_cmd_mailbox(dev);
90 if (IS_ERR(mailbox))
91 return PTR_ERR(mailbox);
92 context = mailbox->buf;
93 memset(context, 0, sizeof *context);
94
95 context->flags = SET_PORT_GEN_ALL_VALID;
96 context->mtu = cpu_to_be16(mtu);
97 context->pptx = (pptx * (!pfctx)) << 7;
98 context->pfctx = pfctx;
99 context->pprx = (pprx * (!pfcrx)) << 7;
100 context->pfcrx = pfcrx;
101
102 in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
103 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
104 MLX4_CMD_TIME_CLASS_B);
105
106 mlx4_free_cmd_mailbox(dev, mailbox);
107 return err;
108}
109
110int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
111 u8 promisc)
112{
113 struct mlx4_cmd_mailbox *mailbox;
114 struct mlx4_set_port_rqp_calc_context *context;
115 int err;
116 u32 in_mod;
117 u32 m_promisc = (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) ?
118 MCAST_DIRECT : MCAST_DEFAULT;
119
120 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER &&
121 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER)
122 return 0;
123
124 mailbox = mlx4_alloc_cmd_mailbox(dev);
125 if (IS_ERR(mailbox))
126 return PTR_ERR(mailbox);
127 context = mailbox->buf;
128 memset(context, 0, sizeof *context);
129
130 context->base_qpn = cpu_to_be32(base_qpn);
131 context->n_mac = 0x2;
132 context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_SHIFT |
133 base_qpn);
134 context->mcast = cpu_to_be32(m_promisc << SET_PORT_MC_PROMISC_SHIFT |
135 base_qpn);
136 context->intra_no_vlan = 0;
137 context->no_vlan = MLX4_NO_VLAN_IDX;
138 context->intra_vlan_miss = 0;
139 context->vlan_miss = MLX4_VLAN_MISS_IDX;
140
141 in_mod = MLX4_SET_PORT_RQP_CALC << 8 | port;
142 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
143 MLX4_CMD_TIME_CLASS_B);
144
145 mlx4_free_cmd_mailbox(dev, mailbox);
146 return err;
147}
148
149int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port)
150{
151 struct mlx4_en_query_port_context *qport_context;
152 struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]);
153 struct mlx4_en_port_state *state = &priv->port_state;
154 struct mlx4_cmd_mailbox *mailbox;
155 int err;
156
157 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
158 if (IS_ERR(mailbox))
159 return PTR_ERR(mailbox);
160 memset(mailbox->buf, 0, sizeof(*qport_context));
161 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
162 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B);
163 if (err)
164 goto out;
165 qport_context = mailbox->buf;
166
167 /* This command is always accessed from Ethtool context
168 * already synchronized, no need in locking */
169 state->link_state = !!(qport_context->link_up & MLX4_EN_LINK_UP_MASK);
170 if ((qport_context->link_speed & MLX4_EN_SPEED_MASK) ==
171 MLX4_EN_1G_SPEED)
172 state->link_speed = 1000;
173 else
174 state->link_speed = 10000;
175 state->transciver = qport_context->transceiver;
176
177out:
178 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
179 return err;
180}
181
182int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset)
183{
184 struct mlx4_en_stat_out_mbox *mlx4_en_stats;
185 struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]);
186 struct net_device_stats *stats = &priv->stats;
187 struct mlx4_cmd_mailbox *mailbox;
188 u64 in_mod = reset << 8 | port;
189 int err;
190 int i;
191
192 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
193 if (IS_ERR(mailbox))
194 return PTR_ERR(mailbox);
195 memset(mailbox->buf, 0, sizeof(*mlx4_en_stats));
196 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, in_mod, 0,
197 MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B);
198 if (err)
199 goto out;
200
201 mlx4_en_stats = mailbox->buf;
202
203 spin_lock_bh(&priv->stats_lock);
204
205 stats->rx_packets = 0;
206 stats->rx_bytes = 0;
207 for (i = 0; i < priv->rx_ring_num; i++) {
208 stats->rx_packets += priv->rx_ring[i].packets;
209 stats->rx_bytes += priv->rx_ring[i].bytes;
210 }
211 stats->tx_packets = 0;
212 stats->tx_bytes = 0;
213 for (i = 0; i < priv->tx_ring_num; i++) {
214 stats->tx_packets += priv->tx_ring[i].packets;
215 stats->tx_bytes += priv->tx_ring[i].bytes;
216 }
217
218 stats->rx_errors = be64_to_cpu(mlx4_en_stats->PCS) +
219 be32_to_cpu(mlx4_en_stats->RdropLength) +
220 be32_to_cpu(mlx4_en_stats->RJBBR) +
221 be32_to_cpu(mlx4_en_stats->RCRC) +
222 be32_to_cpu(mlx4_en_stats->RRUNT);
223 stats->tx_errors = be32_to_cpu(mlx4_en_stats->TDROP);
224 stats->multicast = be64_to_cpu(mlx4_en_stats->MCAST_prio_0) +
225 be64_to_cpu(mlx4_en_stats->MCAST_prio_1) +
226 be64_to_cpu(mlx4_en_stats->MCAST_prio_2) +
227 be64_to_cpu(mlx4_en_stats->MCAST_prio_3) +
228 be64_to_cpu(mlx4_en_stats->MCAST_prio_4) +
229 be64_to_cpu(mlx4_en_stats->MCAST_prio_5) +
230 be64_to_cpu(mlx4_en_stats->MCAST_prio_6) +
231 be64_to_cpu(mlx4_en_stats->MCAST_prio_7) +
232 be64_to_cpu(mlx4_en_stats->MCAST_novlan);
233 stats->collisions = 0;
234 stats->rx_length_errors = be32_to_cpu(mlx4_en_stats->RdropLength);
235 stats->rx_over_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
236 stats->rx_crc_errors = be32_to_cpu(mlx4_en_stats->RCRC);
237 stats->rx_frame_errors = 0;
238 stats->rx_fifo_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
239 stats->rx_missed_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
240 stats->tx_aborted_errors = 0;
241 stats->tx_carrier_errors = 0;
242 stats->tx_fifo_errors = 0;
243 stats->tx_heartbeat_errors = 0;
244 stats->tx_window_errors = 0;
245
246 priv->pkstats.broadcast =
247 be64_to_cpu(mlx4_en_stats->RBCAST_prio_0) +
248 be64_to_cpu(mlx4_en_stats->RBCAST_prio_1) +
249 be64_to_cpu(mlx4_en_stats->RBCAST_prio_2) +
250 be64_to_cpu(mlx4_en_stats->RBCAST_prio_3) +
251 be64_to_cpu(mlx4_en_stats->RBCAST_prio_4) +
252 be64_to_cpu(mlx4_en_stats->RBCAST_prio_5) +
253 be64_to_cpu(mlx4_en_stats->RBCAST_prio_6) +
254 be64_to_cpu(mlx4_en_stats->RBCAST_prio_7) +
255 be64_to_cpu(mlx4_en_stats->RBCAST_novlan);
256 priv->pkstats.rx_prio[0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_0);
257 priv->pkstats.rx_prio[1] = be64_to_cpu(mlx4_en_stats->RTOT_prio_1);
258 priv->pkstats.rx_prio[2] = be64_to_cpu(mlx4_en_stats->RTOT_prio_2);
259 priv->pkstats.rx_prio[3] = be64_to_cpu(mlx4_en_stats->RTOT_prio_3);
260 priv->pkstats.rx_prio[4] = be64_to_cpu(mlx4_en_stats->RTOT_prio_4);
261 priv->pkstats.rx_prio[5] = be64_to_cpu(mlx4_en_stats->RTOT_prio_5);
262 priv->pkstats.rx_prio[6] = be64_to_cpu(mlx4_en_stats->RTOT_prio_6);
263 priv->pkstats.rx_prio[7] = be64_to_cpu(mlx4_en_stats->RTOT_prio_7);
264 priv->pkstats.tx_prio[0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_0);
265 priv->pkstats.tx_prio[1] = be64_to_cpu(mlx4_en_stats->TTOT_prio_1);
266 priv->pkstats.tx_prio[2] = be64_to_cpu(mlx4_en_stats->TTOT_prio_2);
267 priv->pkstats.tx_prio[3] = be64_to_cpu(mlx4_en_stats->TTOT_prio_3);
268 priv->pkstats.tx_prio[4] = be64_to_cpu(mlx4_en_stats->TTOT_prio_4);
269 priv->pkstats.tx_prio[5] = be64_to_cpu(mlx4_en_stats->TTOT_prio_5);
270 priv->pkstats.tx_prio[6] = be64_to_cpu(mlx4_en_stats->TTOT_prio_6);
271 priv->pkstats.tx_prio[7] = be64_to_cpu(mlx4_en_stats->TTOT_prio_7);
272 spin_unlock_bh(&priv->stats_lock);
273
274out:
275 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
276 return err;
277}
278