Linux kernel mirror (for testing)
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1/*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX4_DEVICE_H
34#define MLX4_DEVICE_H
35
36#include <linux/pci.h>
37#include <linux/completion.h>
38#include <linux/radix-tree.h>
39
40#include <asm/atomic.h>
41
42#define MAX_MSIX_P_PORT 17
43#define MAX_MSIX 64
44#define MSIX_LEGACY_SZ 4
45#define MIN_MSIX_P_PORT 5
46
47enum {
48 MLX4_FLAG_MSI_X = 1 << 0,
49 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
50};
51
52enum {
53 MLX4_MAX_PORTS = 2
54};
55
56enum {
57 MLX4_BOARD_ID_LEN = 64
58};
59
60enum {
61 MLX4_DEV_CAP_FLAG_RC = 1 << 0,
62 MLX4_DEV_CAP_FLAG_UC = 1 << 1,
63 MLX4_DEV_CAP_FLAG_UD = 1 << 2,
64 MLX4_DEV_CAP_FLAG_SRQ = 1 << 6,
65 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1 << 7,
66 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 << 8,
67 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 << 9,
68 MLX4_DEV_CAP_FLAG_DPDP = 1 << 12,
69 MLX4_DEV_CAP_FLAG_BLH = 1 << 15,
70 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1 << 16,
71 MLX4_DEV_CAP_FLAG_APM = 1 << 17,
72 MLX4_DEV_CAP_FLAG_ATOMIC = 1 << 18,
73 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1 << 19,
74 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1 << 20,
75 MLX4_DEV_CAP_FLAG_UD_MCAST = 1 << 21,
76 MLX4_DEV_CAP_FLAG_IBOE = 1 << 30
77};
78
79enum {
80 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
81 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
82 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
83 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
84 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
85};
86
87enum mlx4_event {
88 MLX4_EVENT_TYPE_COMP = 0x00,
89 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
90 MLX4_EVENT_TYPE_COMM_EST = 0x02,
91 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
92 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
93 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
94 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
95 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
96 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
97 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
98 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
99 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
100 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
101 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
102 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
103 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
104 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
105 MLX4_EVENT_TYPE_CMD = 0x0a
106};
107
108enum {
109 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
110 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
111};
112
113enum {
114 MLX4_PERM_LOCAL_READ = 1 << 10,
115 MLX4_PERM_LOCAL_WRITE = 1 << 11,
116 MLX4_PERM_REMOTE_READ = 1 << 12,
117 MLX4_PERM_REMOTE_WRITE = 1 << 13,
118 MLX4_PERM_ATOMIC = 1 << 14
119};
120
121enum {
122 MLX4_OPCODE_NOP = 0x00,
123 MLX4_OPCODE_SEND_INVAL = 0x01,
124 MLX4_OPCODE_RDMA_WRITE = 0x08,
125 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
126 MLX4_OPCODE_SEND = 0x0a,
127 MLX4_OPCODE_SEND_IMM = 0x0b,
128 MLX4_OPCODE_LSO = 0x0e,
129 MLX4_OPCODE_RDMA_READ = 0x10,
130 MLX4_OPCODE_ATOMIC_CS = 0x11,
131 MLX4_OPCODE_ATOMIC_FA = 0x12,
132 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
133 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
134 MLX4_OPCODE_BIND_MW = 0x18,
135 MLX4_OPCODE_FMR = 0x19,
136 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
137 MLX4_OPCODE_CONFIG_CMD = 0x1f,
138
139 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
140 MLX4_RECV_OPCODE_SEND = 0x01,
141 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
142 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
143
144 MLX4_CQE_OPCODE_ERROR = 0x1e,
145 MLX4_CQE_OPCODE_RESIZE = 0x16,
146};
147
148enum {
149 MLX4_STAT_RATE_OFFSET = 5
150};
151
152enum mlx4_protocol {
153 MLX4_PROT_IB_IPV6 = 0,
154 MLX4_PROT_ETH,
155 MLX4_PROT_IB_IPV4,
156 MLX4_PROT_FCOE
157};
158
159enum {
160 MLX4_MTT_FLAG_PRESENT = 1
161};
162
163enum mlx4_qp_region {
164 MLX4_QP_REGION_FW = 0,
165 MLX4_QP_REGION_ETH_ADDR,
166 MLX4_QP_REGION_FC_ADDR,
167 MLX4_QP_REGION_FC_EXCH,
168 MLX4_NUM_QP_REGION
169};
170
171enum mlx4_port_type {
172 MLX4_PORT_TYPE_IB = 1,
173 MLX4_PORT_TYPE_ETH = 2,
174 MLX4_PORT_TYPE_AUTO = 3
175};
176
177enum mlx4_special_vlan_idx {
178 MLX4_NO_VLAN_IDX = 0,
179 MLX4_VLAN_MISS_IDX,
180 MLX4_VLAN_REGULAR
181};
182
183enum mlx4_steer_type {
184 MLX4_MC_STEER = 0,
185 MLX4_UC_STEER,
186 MLX4_NUM_STEERS
187};
188
189enum {
190 MLX4_NUM_FEXCH = 64 * 1024,
191};
192
193enum {
194 MLX4_MAX_FAST_REG_PAGES = 511,
195};
196
197static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
198{
199 return (major << 32) | (minor << 16) | subminor;
200}
201
202struct mlx4_caps {
203 u64 fw_ver;
204 int num_ports;
205 int vl_cap[MLX4_MAX_PORTS + 1];
206 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
207 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
208 u64 def_mac[MLX4_MAX_PORTS + 1];
209 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
210 int gid_table_len[MLX4_MAX_PORTS + 1];
211 int pkey_table_len[MLX4_MAX_PORTS + 1];
212 int trans_type[MLX4_MAX_PORTS + 1];
213 int vendor_oui[MLX4_MAX_PORTS + 1];
214 int wavelength[MLX4_MAX_PORTS + 1];
215 u64 trans_code[MLX4_MAX_PORTS + 1];
216 int local_ca_ack_delay;
217 int num_uars;
218 int bf_reg_size;
219 int bf_regs_per_page;
220 int max_sq_sg;
221 int max_rq_sg;
222 int num_qps;
223 int max_wqes;
224 int max_sq_desc_sz;
225 int max_rq_desc_sz;
226 int max_qp_init_rdma;
227 int max_qp_dest_rdma;
228 int sqp_start;
229 int num_srqs;
230 int max_srq_wqes;
231 int max_srq_sge;
232 int reserved_srqs;
233 int num_cqs;
234 int max_cqes;
235 int reserved_cqs;
236 int num_eqs;
237 int reserved_eqs;
238 int num_comp_vectors;
239 int comp_pool;
240 int num_mpts;
241 int num_mtt_segs;
242 int mtts_per_seg;
243 int fmr_reserved_mtts;
244 int reserved_mtts;
245 int reserved_mrws;
246 int reserved_uars;
247 int num_mgms;
248 int num_amgms;
249 int reserved_mcgs;
250 int num_qp_per_mgm;
251 int num_pds;
252 int reserved_pds;
253 int mtt_entry_sz;
254 u32 max_msg_sz;
255 u32 page_size_cap;
256 u32 flags;
257 u32 bmme_flags;
258 u32 reserved_lkey;
259 u16 stat_rate_support;
260 int udp_rss;
261 int loopback_support;
262 int vep_uc_steering;
263 int vep_mc_steering;
264 int wol;
265 u8 port_width_cap[MLX4_MAX_PORTS + 1];
266 int max_gso_sz;
267 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
268 int reserved_qps;
269 int reserved_qps_base[MLX4_NUM_QP_REGION];
270 int log_num_macs;
271 int log_num_vlans;
272 int log_num_prios;
273 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
274 u8 supported_type[MLX4_MAX_PORTS + 1];
275 u32 port_mask;
276 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
277};
278
279struct mlx4_buf_list {
280 void *buf;
281 dma_addr_t map;
282};
283
284struct mlx4_buf {
285 struct mlx4_buf_list direct;
286 struct mlx4_buf_list *page_list;
287 int nbufs;
288 int npages;
289 int page_shift;
290};
291
292struct mlx4_mtt {
293 u32 first_seg;
294 int order;
295 int page_shift;
296};
297
298enum {
299 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
300};
301
302struct mlx4_db_pgdir {
303 struct list_head list;
304 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
305 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
306 unsigned long *bits[2];
307 __be32 *db_page;
308 dma_addr_t db_dma;
309};
310
311struct mlx4_ib_user_db_page;
312
313struct mlx4_db {
314 __be32 *db;
315 union {
316 struct mlx4_db_pgdir *pgdir;
317 struct mlx4_ib_user_db_page *user_page;
318 } u;
319 dma_addr_t dma;
320 int index;
321 int order;
322};
323
324struct mlx4_hwq_resources {
325 struct mlx4_db db;
326 struct mlx4_mtt mtt;
327 struct mlx4_buf buf;
328};
329
330struct mlx4_mr {
331 struct mlx4_mtt mtt;
332 u64 iova;
333 u64 size;
334 u32 key;
335 u32 pd;
336 u32 access;
337 int enabled;
338};
339
340struct mlx4_fmr {
341 struct mlx4_mr mr;
342 struct mlx4_mpt_entry *mpt;
343 __be64 *mtts;
344 dma_addr_t dma_handle;
345 int max_pages;
346 int max_maps;
347 int maps;
348 u8 page_shift;
349};
350
351struct mlx4_uar {
352 unsigned long pfn;
353 int index;
354 struct list_head bf_list;
355 unsigned free_bf_bmap;
356 void __iomem *map;
357 void __iomem *bf_map;
358};
359
360struct mlx4_bf {
361 unsigned long offset;
362 int buf_size;
363 struct mlx4_uar *uar;
364 void __iomem *reg;
365};
366
367struct mlx4_cq {
368 void (*comp) (struct mlx4_cq *);
369 void (*event) (struct mlx4_cq *, enum mlx4_event);
370
371 struct mlx4_uar *uar;
372
373 u32 cons_index;
374
375 __be32 *set_ci_db;
376 __be32 *arm_db;
377 int arm_sn;
378
379 int cqn;
380 unsigned vector;
381
382 atomic_t refcount;
383 struct completion free;
384};
385
386struct mlx4_qp {
387 void (*event) (struct mlx4_qp *, enum mlx4_event);
388
389 int qpn;
390
391 atomic_t refcount;
392 struct completion free;
393};
394
395struct mlx4_srq {
396 void (*event) (struct mlx4_srq *, enum mlx4_event);
397
398 int srqn;
399 int max;
400 int max_gs;
401 int wqe_shift;
402
403 atomic_t refcount;
404 struct completion free;
405};
406
407struct mlx4_av {
408 __be32 port_pd;
409 u8 reserved1;
410 u8 g_slid;
411 __be16 dlid;
412 u8 reserved2;
413 u8 gid_index;
414 u8 stat_rate;
415 u8 hop_limit;
416 __be32 sl_tclass_flowlabel;
417 u8 dgid[16];
418};
419
420struct mlx4_eth_av {
421 __be32 port_pd;
422 u8 reserved1;
423 u8 smac_idx;
424 u16 reserved2;
425 u8 reserved3;
426 u8 gid_index;
427 u8 stat_rate;
428 u8 hop_limit;
429 __be32 sl_tclass_flowlabel;
430 u8 dgid[16];
431 u32 reserved4[2];
432 __be16 vlan;
433 u8 mac[6];
434};
435
436union mlx4_ext_av {
437 struct mlx4_av ib;
438 struct mlx4_eth_av eth;
439};
440
441struct mlx4_dev {
442 struct pci_dev *pdev;
443 unsigned long flags;
444 struct mlx4_caps caps;
445 struct radix_tree_root qp_table_tree;
446 u8 rev_id;
447 char board_id[MLX4_BOARD_ID_LEN];
448};
449
450struct mlx4_init_port_param {
451 int set_guid0;
452 int set_node_guid;
453 int set_si_guid;
454 u16 mtu;
455 int port_width_cap;
456 u16 vl_cap;
457 u16 max_gid;
458 u16 max_pkey;
459 u64 guid0;
460 u64 node_guid;
461 u64 si_guid;
462};
463
464#define mlx4_foreach_port(port, dev, type) \
465 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
466 if (((type) == MLX4_PORT_TYPE_IB ? (dev)->caps.port_mask : \
467 ~(dev)->caps.port_mask) & 1 << ((port) - 1))
468
469#define mlx4_foreach_ib_transport_port(port, dev) \
470 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
471 if (((dev)->caps.port_mask & 1 << ((port) - 1)) || \
472 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
473
474
475int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
476 struct mlx4_buf *buf);
477void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
478static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
479{
480 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
481 return buf->direct.buf + offset;
482 else
483 return buf->page_list[offset >> PAGE_SHIFT].buf +
484 (offset & (PAGE_SIZE - 1));
485}
486
487int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
488void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
489
490int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
491void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
492int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf);
493void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
494
495int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
496 struct mlx4_mtt *mtt);
497void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
498u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
499
500int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
501 int npages, int page_shift, struct mlx4_mr *mr);
502void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
503int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
504int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
505 int start_index, int npages, u64 *page_list);
506int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
507 struct mlx4_buf *buf);
508
509int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
510void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
511
512int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
513 int size, int max_direct);
514void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
515 int size);
516
517int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
518 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
519 unsigned vector, int collapsed);
520void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
521
522int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
523void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
524
525int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
526void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
527
528int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt,
529 u64 db_rec, struct mlx4_srq *srq);
530void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
531int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
532int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
533
534int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
535int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
536
537int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
538 int block_mcast_loopback, enum mlx4_protocol protocol);
539int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
540 enum mlx4_protocol protocol);
541int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
542int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
543int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
544int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
545int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
546
547int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn, u8 wrap);
548void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int qpn);
549int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac, u8 wrap);
550
551int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
552int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
553void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
554
555int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
556 int npages, u64 iova, u32 *lkey, u32 *rkey);
557int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
558 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
559int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
560void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
561 u32 *lkey, u32 *rkey);
562int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
563int mlx4_SYNC_TPT(struct mlx4_dev *dev);
564int mlx4_test_interrupts(struct mlx4_dev *dev);
565int mlx4_assign_eq(struct mlx4_dev *dev, char* name , int* vector);
566void mlx4_release_eq(struct mlx4_dev *dev, int vec);
567
568int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
569int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
570
571#endif /* MLX4_DEVICE_H */