Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/*
2 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
3 */
4#ifndef _ASM_POWERPC_SYSTEM_H
5#define _ASM_POWERPC_SYSTEM_H
6
7#include <linux/kernel.h>
8#include <linux/irqflags.h>
9
10#include <asm/hw_irq.h>
11
12/*
13 * Memory barrier.
14 * The sync instruction guarantees that all memory accesses initiated
15 * by this processor have been performed (with respect to all other
16 * mechanisms that access memory). The eieio instruction is a barrier
17 * providing an ordering (separately) for (a) cacheable stores and (b)
18 * loads and stores to non-cacheable memory (e.g. I/O devices).
19 *
20 * mb() prevents loads and stores being reordered across this point.
21 * rmb() prevents loads being reordered across this point.
22 * wmb() prevents stores being reordered across this point.
23 * read_barrier_depends() prevents data-dependent loads being reordered
24 * across this point (nop on PPC).
25 *
26 * *mb() variants without smp_ prefix must order all types of memory
27 * operations with one another. sync is the only instruction sufficient
28 * to do this.
29 *
30 * For the smp_ barriers, ordering is for cacheable memory operations
31 * only. We have to use the sync instruction for smp_mb(), since lwsync
32 * doesn't order loads with respect to previous stores. Lwsync can be
33 * used for smp_rmb() and smp_wmb().
34 *
35 * However, on CPUs that don't support lwsync, lwsync actually maps to a
36 * heavy-weight sync, so smp_wmb() can be a lighter-weight eieio.
37 */
38#define mb() __asm__ __volatile__ ("sync" : : : "memory")
39#define rmb() __asm__ __volatile__ ("sync" : : : "memory")
40#define wmb() __asm__ __volatile__ ("sync" : : : "memory")
41#define read_barrier_depends() do { } while(0)
42
43#define set_mb(var, value) do { var = value; mb(); } while (0)
44
45#ifdef __KERNEL__
46#define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */
47#ifdef CONFIG_SMP
48
49#ifdef __SUBARCH_HAS_LWSYNC
50# define SMPWMB LWSYNC
51#else
52# define SMPWMB eieio
53#endif
54
55#define smp_mb() mb()
56#define smp_rmb() __asm__ __volatile__ (stringify_in_c(LWSYNC) : : :"memory")
57#define smp_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory")
58#define smp_read_barrier_depends() read_barrier_depends()
59#else
60#define smp_mb() barrier()
61#define smp_rmb() barrier()
62#define smp_wmb() barrier()
63#define smp_read_barrier_depends() do { } while(0)
64#endif /* CONFIG_SMP */
65
66/*
67 * This is a barrier which prevents following instructions from being
68 * started until the value of the argument x is known. For example, if
69 * x is a variable loaded from memory, this prevents following
70 * instructions from being executed until the load has been performed.
71 */
72#define data_barrier(x) \
73 asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
74
75struct task_struct;
76struct pt_regs;
77
78#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
79
80extern int (*__debugger)(struct pt_regs *regs);
81extern int (*__debugger_ipi)(struct pt_regs *regs);
82extern int (*__debugger_bpt)(struct pt_regs *regs);
83extern int (*__debugger_sstep)(struct pt_regs *regs);
84extern int (*__debugger_iabr_match)(struct pt_regs *regs);
85extern int (*__debugger_dabr_match)(struct pt_regs *regs);
86extern int (*__debugger_fault_handler)(struct pt_regs *regs);
87
88#define DEBUGGER_BOILERPLATE(__NAME) \
89static inline int __NAME(struct pt_regs *regs) \
90{ \
91 if (unlikely(__ ## __NAME)) \
92 return __ ## __NAME(regs); \
93 return 0; \
94}
95
96DEBUGGER_BOILERPLATE(debugger)
97DEBUGGER_BOILERPLATE(debugger_ipi)
98DEBUGGER_BOILERPLATE(debugger_bpt)
99DEBUGGER_BOILERPLATE(debugger_sstep)
100DEBUGGER_BOILERPLATE(debugger_iabr_match)
101DEBUGGER_BOILERPLATE(debugger_dabr_match)
102DEBUGGER_BOILERPLATE(debugger_fault_handler)
103
104#else
105static inline int debugger(struct pt_regs *regs) { return 0; }
106static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
107static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
108static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
109static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
110static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
111static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
112#endif
113
114extern int set_dabr(unsigned long dabr);
115#ifdef CONFIG_PPC_ADV_DEBUG_REGS
116extern void do_send_trap(struct pt_regs *regs, unsigned long address,
117 unsigned long error_code, int signal_code, int brkpt);
118#else
119extern void do_dabr(struct pt_regs *regs, unsigned long address,
120 unsigned long error_code);
121#endif
122extern void print_backtrace(unsigned long *);
123extern void show_regs(struct pt_regs * regs);
124extern void flush_instruction_cache(void);
125extern void hard_reset_now(void);
126extern void poweroff_now(void);
127
128#ifdef CONFIG_6xx
129extern long _get_L2CR(void);
130extern long _get_L3CR(void);
131extern void _set_L2CR(unsigned long);
132extern void _set_L3CR(unsigned long);
133#else
134#define _get_L2CR() 0L
135#define _get_L3CR() 0L
136#define _set_L2CR(val) do { } while(0)
137#define _set_L3CR(val) do { } while(0)
138#endif
139
140extern void via_cuda_init(void);
141extern void read_rtc_time(void);
142extern void pmac_find_display(void);
143extern void giveup_fpu(struct task_struct *);
144extern void disable_kernel_fp(void);
145extern void enable_kernel_fp(void);
146extern void flush_fp_to_thread(struct task_struct *);
147extern void enable_kernel_altivec(void);
148extern void giveup_altivec(struct task_struct *);
149extern void load_up_altivec(struct task_struct *);
150extern int emulate_altivec(struct pt_regs *);
151extern void __giveup_vsx(struct task_struct *);
152extern void giveup_vsx(struct task_struct *);
153extern void enable_kernel_spe(void);
154extern void giveup_spe(struct task_struct *);
155extern void load_up_spe(struct task_struct *);
156extern int fix_alignment(struct pt_regs *);
157extern void cvt_fd(float *from, double *to);
158extern void cvt_df(double *from, float *to);
159
160#ifndef CONFIG_SMP
161extern void discard_lazy_cpu_state(void);
162#else
163static inline void discard_lazy_cpu_state(void)
164{
165}
166#endif
167
168#ifdef CONFIG_ALTIVEC
169extern void flush_altivec_to_thread(struct task_struct *);
170#else
171static inline void flush_altivec_to_thread(struct task_struct *t)
172{
173}
174#endif
175
176#ifdef CONFIG_VSX
177extern void flush_vsx_to_thread(struct task_struct *);
178#else
179static inline void flush_vsx_to_thread(struct task_struct *t)
180{
181}
182#endif
183
184#ifdef CONFIG_SPE
185extern void flush_spe_to_thread(struct task_struct *);
186#else
187static inline void flush_spe_to_thread(struct task_struct *t)
188{
189}
190#endif
191
192extern int call_rtas(const char *, int, int, unsigned long *, ...);
193extern void cacheable_memzero(void *p, unsigned int nb);
194extern void *cacheable_memcpy(void *, const void *, unsigned int);
195extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
196extern void bad_page_fault(struct pt_regs *, unsigned long, int);
197extern int die(const char *, struct pt_regs *, long);
198extern void _exception(int, struct pt_regs *, int, unsigned long);
199extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
200
201#ifdef CONFIG_BOOKE_WDT
202extern u32 booke_wdt_enabled;
203extern u32 booke_wdt_period;
204#endif /* CONFIG_BOOKE_WDT */
205
206struct device_node;
207extern void note_scsi_host(struct device_node *, void *);
208
209extern struct task_struct *__switch_to(struct task_struct *,
210 struct task_struct *);
211#define switch_to(prev, next, last) ((last) = __switch_to((prev), (next)))
212
213struct thread_struct;
214extern struct task_struct *_switch(struct thread_struct *prev,
215 struct thread_struct *next);
216
217extern unsigned int rtas_data;
218extern int mem_init_done; /* set on boot once kmalloc can be called */
219extern int init_bootmem_done; /* set once bootmem is available */
220extern phys_addr_t memory_limit;
221extern unsigned long klimit;
222extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
223
224extern int powersave_nap; /* set if nap mode can be used in idle loop */
225
226/*
227 * Atomic exchange
228 *
229 * Changes the memory location '*ptr' to be val and returns
230 * the previous value stored there.
231 */
232static __always_inline unsigned long
233__xchg_u32(volatile void *p, unsigned long val)
234{
235 unsigned long prev;
236
237 __asm__ __volatile__(
238 PPC_RELEASE_BARRIER
239"1: lwarx %0,0,%2 \n"
240 PPC405_ERR77(0,%2)
241" stwcx. %3,0,%2 \n\
242 bne- 1b"
243 PPC_ACQUIRE_BARRIER
244 : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
245 : "r" (p), "r" (val)
246 : "cc", "memory");
247
248 return prev;
249}
250
251/*
252 * Atomic exchange
253 *
254 * Changes the memory location '*ptr' to be val and returns
255 * the previous value stored there.
256 */
257static __always_inline unsigned long
258__xchg_u32_local(volatile void *p, unsigned long val)
259{
260 unsigned long prev;
261
262 __asm__ __volatile__(
263"1: lwarx %0,0,%2 \n"
264 PPC405_ERR77(0,%2)
265" stwcx. %3,0,%2 \n\
266 bne- 1b"
267 : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
268 : "r" (p), "r" (val)
269 : "cc", "memory");
270
271 return prev;
272}
273
274#ifdef CONFIG_PPC64
275static __always_inline unsigned long
276__xchg_u64(volatile void *p, unsigned long val)
277{
278 unsigned long prev;
279
280 __asm__ __volatile__(
281 PPC_RELEASE_BARRIER
282"1: ldarx %0,0,%2 \n"
283 PPC405_ERR77(0,%2)
284" stdcx. %3,0,%2 \n\
285 bne- 1b"
286 PPC_ACQUIRE_BARRIER
287 : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
288 : "r" (p), "r" (val)
289 : "cc", "memory");
290
291 return prev;
292}
293
294static __always_inline unsigned long
295__xchg_u64_local(volatile void *p, unsigned long val)
296{
297 unsigned long prev;
298
299 __asm__ __volatile__(
300"1: ldarx %0,0,%2 \n"
301 PPC405_ERR77(0,%2)
302" stdcx. %3,0,%2 \n\
303 bne- 1b"
304 : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
305 : "r" (p), "r" (val)
306 : "cc", "memory");
307
308 return prev;
309}
310#endif
311
312/*
313 * This function doesn't exist, so you'll get a linker error
314 * if something tries to do an invalid xchg().
315 */
316extern void __xchg_called_with_bad_pointer(void);
317
318static __always_inline unsigned long
319__xchg(volatile void *ptr, unsigned long x, unsigned int size)
320{
321 switch (size) {
322 case 4:
323 return __xchg_u32(ptr, x);
324#ifdef CONFIG_PPC64
325 case 8:
326 return __xchg_u64(ptr, x);
327#endif
328 }
329 __xchg_called_with_bad_pointer();
330 return x;
331}
332
333static __always_inline unsigned long
334__xchg_local(volatile void *ptr, unsigned long x, unsigned int size)
335{
336 switch (size) {
337 case 4:
338 return __xchg_u32_local(ptr, x);
339#ifdef CONFIG_PPC64
340 case 8:
341 return __xchg_u64_local(ptr, x);
342#endif
343 }
344 __xchg_called_with_bad_pointer();
345 return x;
346}
347#define xchg(ptr,x) \
348 ({ \
349 __typeof__(*(ptr)) _x_ = (x); \
350 (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
351 })
352
353#define xchg_local(ptr,x) \
354 ({ \
355 __typeof__(*(ptr)) _x_ = (x); \
356 (__typeof__(*(ptr))) __xchg_local((ptr), \
357 (unsigned long)_x_, sizeof(*(ptr))); \
358 })
359
360/*
361 * Compare and exchange - if *p == old, set it to new,
362 * and return the old value of *p.
363 */
364#define __HAVE_ARCH_CMPXCHG 1
365
366static __always_inline unsigned long
367__cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
368{
369 unsigned int prev;
370
371 __asm__ __volatile__ (
372 PPC_RELEASE_BARRIER
373"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
374 cmpw 0,%0,%3\n\
375 bne- 2f\n"
376 PPC405_ERR77(0,%2)
377" stwcx. %4,0,%2\n\
378 bne- 1b"
379 PPC_ACQUIRE_BARRIER
380 "\n\
3812:"
382 : "=&r" (prev), "+m" (*p)
383 : "r" (p), "r" (old), "r" (new)
384 : "cc", "memory");
385
386 return prev;
387}
388
389static __always_inline unsigned long
390__cmpxchg_u32_local(volatile unsigned int *p, unsigned long old,
391 unsigned long new)
392{
393 unsigned int prev;
394
395 __asm__ __volatile__ (
396"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
397 cmpw 0,%0,%3\n\
398 bne- 2f\n"
399 PPC405_ERR77(0,%2)
400" stwcx. %4,0,%2\n\
401 bne- 1b"
402 "\n\
4032:"
404 : "=&r" (prev), "+m" (*p)
405 : "r" (p), "r" (old), "r" (new)
406 : "cc", "memory");
407
408 return prev;
409}
410
411#ifdef CONFIG_PPC64
412static __always_inline unsigned long
413__cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
414{
415 unsigned long prev;
416
417 __asm__ __volatile__ (
418 PPC_RELEASE_BARRIER
419"1: ldarx %0,0,%2 # __cmpxchg_u64\n\
420 cmpd 0,%0,%3\n\
421 bne- 2f\n\
422 stdcx. %4,0,%2\n\
423 bne- 1b"
424 PPC_ACQUIRE_BARRIER
425 "\n\
4262:"
427 : "=&r" (prev), "+m" (*p)
428 : "r" (p), "r" (old), "r" (new)
429 : "cc", "memory");
430
431 return prev;
432}
433
434static __always_inline unsigned long
435__cmpxchg_u64_local(volatile unsigned long *p, unsigned long old,
436 unsigned long new)
437{
438 unsigned long prev;
439
440 __asm__ __volatile__ (
441"1: ldarx %0,0,%2 # __cmpxchg_u64\n\
442 cmpd 0,%0,%3\n\
443 bne- 2f\n\
444 stdcx. %4,0,%2\n\
445 bne- 1b"
446 "\n\
4472:"
448 : "=&r" (prev), "+m" (*p)
449 : "r" (p), "r" (old), "r" (new)
450 : "cc", "memory");
451
452 return prev;
453}
454#endif
455
456/* This function doesn't exist, so you'll get a linker error
457 if something tries to do an invalid cmpxchg(). */
458extern void __cmpxchg_called_with_bad_pointer(void);
459
460static __always_inline unsigned long
461__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
462 unsigned int size)
463{
464 switch (size) {
465 case 4:
466 return __cmpxchg_u32(ptr, old, new);
467#ifdef CONFIG_PPC64
468 case 8:
469 return __cmpxchg_u64(ptr, old, new);
470#endif
471 }
472 __cmpxchg_called_with_bad_pointer();
473 return old;
474}
475
476static __always_inline unsigned long
477__cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
478 unsigned int size)
479{
480 switch (size) {
481 case 4:
482 return __cmpxchg_u32_local(ptr, old, new);
483#ifdef CONFIG_PPC64
484 case 8:
485 return __cmpxchg_u64_local(ptr, old, new);
486#endif
487 }
488 __cmpxchg_called_with_bad_pointer();
489 return old;
490}
491
492#define cmpxchg(ptr, o, n) \
493 ({ \
494 __typeof__(*(ptr)) _o_ = (o); \
495 __typeof__(*(ptr)) _n_ = (n); \
496 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
497 (unsigned long)_n_, sizeof(*(ptr))); \
498 })
499
500
501#define cmpxchg_local(ptr, o, n) \
502 ({ \
503 __typeof__(*(ptr)) _o_ = (o); \
504 __typeof__(*(ptr)) _n_ = (n); \
505 (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \
506 (unsigned long)_n_, sizeof(*(ptr))); \
507 })
508
509#ifdef CONFIG_PPC64
510/*
511 * We handle most unaligned accesses in hardware. On the other hand
512 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
513 * powers of 2 writes until it reaches sufficient alignment).
514 *
515 * Based on this we disable the IP header alignment in network drivers.
516 */
517#define NET_IP_ALIGN 0
518
519#define cmpxchg64(ptr, o, n) \
520 ({ \
521 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
522 cmpxchg((ptr), (o), (n)); \
523 })
524#define cmpxchg64_local(ptr, o, n) \
525 ({ \
526 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
527 cmpxchg_local((ptr), (o), (n)); \
528 })
529#else
530#include <asm-generic/cmpxchg-local.h>
531#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
532#endif
533
534extern unsigned long arch_align_stack(unsigned long sp);
535
536/* Used in very early kernel initialization. */
537extern unsigned long reloc_offset(void);
538extern unsigned long add_reloc_offset(unsigned long);
539extern void reloc_got2(unsigned long);
540
541#define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x)))
542
543extern struct dentry *powerpc_debugfs_root;
544
545#endif /* __KERNEL__ */
546#endif /* _ASM_POWERPC_SYSTEM_H */