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Linux kernel mirror (for testing)
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1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _E1000_DEFINES_H_
30#define _E1000_DEFINES_H_
31
32#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
33#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
34#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
35#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
36#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
37#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
38#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
39#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
40#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
41#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
42#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
43#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
44#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
45#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
46#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
47#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
48#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
49#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
50
51/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
52#define REQ_TX_DESCRIPTOR_MULTIPLE 8
53#define REQ_RX_DESCRIPTOR_MULTIPLE 8
54
55/* Definitions for power management and wakeup registers */
56/* Wake Up Control */
57#define E1000_WUC_APME 0x00000001 /* APM Enable */
58#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
59#define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
60
61/* Wake Up Filter Control */
62#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
63#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
64#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
65#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
66#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
67#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
68
69/* Wake Up Status */
70#define E1000_WUS_LNKC E1000_WUFC_LNKC
71#define E1000_WUS_MAG E1000_WUFC_MAG
72#define E1000_WUS_EX E1000_WUFC_EX
73#define E1000_WUS_MC E1000_WUFC_MC
74#define E1000_WUS_BC E1000_WUFC_BC
75
76/* Extended Device Control */
77#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */
78#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
79#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
80#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
81#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */
82#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
83#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
84#define E1000_CTRL_EXT_EIAME 0x01000000
85#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
86#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
87#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
88#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
89#define E1000_CTRL_EXT_LSECCK 0x00001000
90#define E1000_CTRL_EXT_PHYPDEN 0x00100000
91
92/* Receive Descriptor bit definitions */
93#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
94#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
95#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
96#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
97#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
98#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
99#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
100#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
101#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
102#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
103#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
104#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
105#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
106
107#define E1000_RXDEXT_STATERR_CE 0x01000000
108#define E1000_RXDEXT_STATERR_SE 0x02000000
109#define E1000_RXDEXT_STATERR_SEQ 0x04000000
110#define E1000_RXDEXT_STATERR_CXE 0x10000000
111#define E1000_RXDEXT_STATERR_RXE 0x80000000
112
113/* mask to determine if packets should be dropped due to frame errors */
114#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
115 E1000_RXD_ERR_CE | \
116 E1000_RXD_ERR_SE | \
117 E1000_RXD_ERR_SEQ | \
118 E1000_RXD_ERR_CXE | \
119 E1000_RXD_ERR_RXE)
120
121/* Same mask, but for extended and packet split descriptors */
122#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
123 E1000_RXDEXT_STATERR_CE | \
124 E1000_RXDEXT_STATERR_SE | \
125 E1000_RXDEXT_STATERR_SEQ | \
126 E1000_RXDEXT_STATERR_CXE | \
127 E1000_RXDEXT_STATERR_RXE)
128
129#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
130
131/* Management Control */
132#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
133#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
134#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
135#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
136#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
137/* Enable MAC address filtering */
138#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
139/* Enable MNG packets to host memory */
140#define E1000_MANC_EN_MNG2HOST 0x00200000
141
142#define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */
143#define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */
144#define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */
145#define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */
146
147/* Receive Control */
148#define E1000_RCTL_EN 0x00000002 /* enable */
149#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
150#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
151#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
152#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
153#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
154#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
155#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
156#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
157#define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min threshold size */
158#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
159#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
160#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
161/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
162#define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
163#define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */
164#define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */
165#define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
166/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
167#define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */
168#define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */
169#define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */
170#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
171#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
172#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
173#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
174#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
175#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
176
177/*
178 * Use byte values for the following shift parameters
179 * Usage:
180 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
181 * E1000_PSRCTL_BSIZE0_MASK) |
182 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
183 * E1000_PSRCTL_BSIZE1_MASK) |
184 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
185 * E1000_PSRCTL_BSIZE2_MASK) |
186 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
187 * E1000_PSRCTL_BSIZE3_MASK))
188 * where value0 = [128..16256], default=256
189 * value1 = [1024..64512], default=4096
190 * value2 = [0..64512], default=4096
191 * value3 = [0..64512], default=0
192 */
193
194#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
195#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
196#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
197#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
198
199#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
200#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
201#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
202#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
203
204/* SWFW_SYNC Definitions */
205#define E1000_SWFW_EEP_SM 0x1
206#define E1000_SWFW_PHY0_SM 0x2
207#define E1000_SWFW_PHY1_SM 0x4
208#define E1000_SWFW_CSR_SM 0x8
209
210/* Device Control */
211#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
212#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
213#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
214#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
215#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
216#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
217#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
218#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
219#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
220#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
221#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
222#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
223#define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */
224#define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */
225#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
226#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
227#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
228#define E1000_CTRL_RST 0x04000000 /* Global reset */
229#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
230#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
231#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
232#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
233
234/*
235 * Bit definitions for the Management Data IO (MDIO) and Management Data
236 * Clock (MDC) pins in the Device Control Register.
237 */
238
239/* Device Status */
240#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
241#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
242#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
243#define E1000_STATUS_FUNC_SHIFT 2
244#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
245#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
246#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
247#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
248#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
249#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */
250#define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */
251#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
252
253/* Constants used to interpret the masked PCI-X bus speed. */
254
255#define HALF_DUPLEX 1
256#define FULL_DUPLEX 2
257
258
259#define ADVERTISE_10_HALF 0x0001
260#define ADVERTISE_10_FULL 0x0002
261#define ADVERTISE_100_HALF 0x0004
262#define ADVERTISE_100_FULL 0x0008
263#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
264#define ADVERTISE_1000_FULL 0x0020
265
266/* 1000/H is not supported, nor spec-compliant. */
267#define E1000_ALL_SPEED_DUPLEX ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
268 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
269 ADVERTISE_1000_FULL)
270#define E1000_ALL_NOT_GIG ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
271 ADVERTISE_100_HALF | ADVERTISE_100_FULL)
272#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
273#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
274#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
275
276#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
277
278/* LED Control */
279#define E1000_PHY_LED0_MODE_MASK 0x00000007
280#define E1000_PHY_LED0_IVRT 0x00000008
281#define E1000_PHY_LED0_MASK 0x0000001F
282
283#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
284#define E1000_LEDCTL_LED0_MODE_SHIFT 0
285#define E1000_LEDCTL_LED0_IVRT 0x00000040
286#define E1000_LEDCTL_LED0_BLINK 0x00000080
287
288#define E1000_LEDCTL_MODE_LINK_UP 0x2
289#define E1000_LEDCTL_MODE_LED_ON 0xE
290#define E1000_LEDCTL_MODE_LED_OFF 0xF
291
292/* Transmit Descriptor bit definitions */
293#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
294#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
295#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
296#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
297#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
298#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
299#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
300#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
301#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
302#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
303#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
304#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
305#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
306#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
307#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
308#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
309#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
310#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
311#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
312
313/* Transmit Control */
314#define E1000_TCTL_EN 0x00000002 /* enable Tx */
315#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
316#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
317#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
318#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
319#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
320
321/* Transmit Arbitration Count */
322
323/* SerDes Control */
324#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
325
326/* Receive Checksum Control */
327#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
328#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
329
330/* Header split receive */
331#define E1000_RFCTL_NFSW_DIS 0x00000040
332#define E1000_RFCTL_NFSR_DIS 0x00000080
333#define E1000_RFCTL_ACK_DIS 0x00001000
334#define E1000_RFCTL_EXTEN 0x00008000
335#define E1000_RFCTL_IPV6_EX_DIS 0x00010000
336#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
337
338/* Collision related configuration parameters */
339#define E1000_COLLISION_THRESHOLD 15
340#define E1000_CT_SHIFT 4
341#define E1000_COLLISION_DISTANCE 63
342#define E1000_COLD_SHIFT 12
343
344/* Default values for the transmit IPG register */
345#define DEFAULT_82543_TIPG_IPGT_COPPER 8
346
347#define E1000_TIPG_IPGT_MASK 0x000003FF
348
349#define DEFAULT_82543_TIPG_IPGR1 8
350#define E1000_TIPG_IPGR1_SHIFT 10
351
352#define DEFAULT_82543_TIPG_IPGR2 6
353#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
354#define E1000_TIPG_IPGR2_SHIFT 20
355
356#define MAX_JUMBO_FRAME_SIZE 0x3F00
357
358/* Extended Configuration Control and Size */
359#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
360#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
361#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008
362#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
363#define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080
364#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
365#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
366#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
367#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
368
369#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
370#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
371#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
372#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
373
374#define E1000_KABGTXD_BGSQLBIAS 0x00050000
375
376/* PBA constants */
377#define E1000_PBA_8K 0x0008 /* 8KB */
378#define E1000_PBA_16K 0x0010 /* 16KB */
379
380#define E1000_PBS_16K E1000_PBA_16K
381
382#define IFS_MAX 80
383#define IFS_MIN 40
384#define IFS_RATIO 4
385#define IFS_STEP 10
386#define MIN_NUM_XMITS 1000
387
388/* SW Semaphore Register */
389#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
390#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
391#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
392
393#define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */
394
395/* Interrupt Cause Read */
396#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
397#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
398#define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */
399#define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
400#define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */
401#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */
402#define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */
403#define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */
404#define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */
405#define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */
406#define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */
407
408/* PBA ECC Register */
409#define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */
410#define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */
411#define E1000_PBA_ECC_CORR_EN 0x00000001 /* ECC correction enable */
412#define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */
413#define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 for ECC */
414
415/*
416 * This defines the bits that are set in the Interrupt Mask
417 * Set/Read Register. Each bit is documented below:
418 * o RXT0 = Receiver Timer Interrupt (ring 0)
419 * o TXDW = Transmit Descriptor Written Back
420 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
421 * o RXSEQ = Receive Sequence Error
422 * o LSC = Link Status Change
423 */
424#define IMS_ENABLE_MASK ( \
425 E1000_IMS_RXT0 | \
426 E1000_IMS_TXDW | \
427 E1000_IMS_RXDMT0 | \
428 E1000_IMS_RXSEQ | \
429 E1000_IMS_LSC)
430
431/* Interrupt Mask Set */
432#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
433#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
434#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
435#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
436#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */
437#define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
438#define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
439#define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
440#define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */
441#define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */
442
443/* Interrupt Cause Set */
444#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
445#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
446#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
447
448/* Transmit Descriptor Control */
449#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
450#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
451#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
452#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
453#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
454#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
455/* Enable the counting of desc. still to be processed. */
456#define E1000_TXDCTL_COUNT_DESC 0x00400000
457
458/* Flow Control Constants */
459#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
460#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
461#define FLOW_CONTROL_TYPE 0x8808
462
463/* 802.1q VLAN Packet Size */
464#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
465
466/* Receive Address */
467/*
468 * Number of high/low register pairs in the RAR. The RAR (Receive Address
469 * Registers) holds the directed and multicast addresses that we monitor.
470 * Technically, we have 16 spots. However, we reserve one of these spots
471 * (RAR[15]) for our directed address used by controllers with
472 * manageability enabled, allowing us room for 15 multicast addresses.
473 */
474#define E1000_RAR_ENTRIES 15
475#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
476#define E1000_RAL_MAC_ADDR_LEN 4
477#define E1000_RAH_MAC_ADDR_LEN 2
478
479/* Error Codes */
480#define E1000_ERR_NVM 1
481#define E1000_ERR_PHY 2
482#define E1000_ERR_CONFIG 3
483#define E1000_ERR_PARAM 4
484#define E1000_ERR_MAC_INIT 5
485#define E1000_ERR_PHY_TYPE 6
486#define E1000_ERR_RESET 9
487#define E1000_ERR_MASTER_REQUESTS_PENDING 10
488#define E1000_ERR_HOST_INTERFACE_COMMAND 11
489#define E1000_BLK_PHY_RESET 12
490#define E1000_ERR_SWFW_SYNC 13
491#define E1000_NOT_IMPLEMENTED 14
492#define E1000_ERR_INVALID_ARGUMENT 16
493#define E1000_ERR_NO_SPACE 17
494#define E1000_ERR_NVM_PBA_SECTION 18
495
496/* Loop limit on how long we wait for auto-negotiation to complete */
497#define FIBER_LINK_UP_LIMIT 50
498#define COPPER_LINK_UP_LIMIT 10
499#define PHY_AUTO_NEG_LIMIT 45
500#define PHY_FORCE_LIMIT 20
501/* Number of 100 microseconds we wait for PCI Express master disable */
502#define MASTER_DISABLE_TIMEOUT 800
503/* Number of milliseconds we wait for PHY configuration done after MAC reset */
504#define PHY_CFG_TIMEOUT 100
505/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
506#define MDIO_OWNERSHIP_TIMEOUT 10
507/* Number of milliseconds for NVM auto read done after MAC reset. */
508#define AUTO_READ_DONE_TIMEOUT 10
509
510/* Flow Control */
511#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
512#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
513#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
514
515/* Transmit Configuration Word */
516#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
517#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
518#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
519#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
520#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
521
522/* Receive Configuration Word */
523#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
524#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
525#define E1000_RXCW_C 0x20000000 /* Receive config */
526#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
527
528/* PCI Express Control */
529#define E1000_GCR_RXD_NO_SNOOP 0x00000001
530#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
531#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
532#define E1000_GCR_TXD_NO_SNOOP 0x00000008
533#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
534#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
535
536#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
537 E1000_GCR_RXDSCW_NO_SNOOP | \
538 E1000_GCR_RXDSCR_NO_SNOOP | \
539 E1000_GCR_TXD_NO_SNOOP | \
540 E1000_GCR_TXDSCW_NO_SNOOP | \
541 E1000_GCR_TXDSCR_NO_SNOOP)
542
543/* PHY Control Register */
544#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
545#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
546#define MII_CR_POWER_DOWN 0x0800 /* Power down */
547#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
548#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
549#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
550#define MII_CR_SPEED_1000 0x0040
551#define MII_CR_SPEED_100 0x2000
552#define MII_CR_SPEED_10 0x0000
553
554/* PHY Status Register */
555#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
556#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
557
558/* Autoneg Advertisement Register */
559#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
560#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
561#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
562#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
563#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
564#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
565
566/* Link Partner Ability Register (Base Page) */
567#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
568#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
569
570/* Autoneg Expansion Register */
571#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
572
573/* 1000BASE-T Control Register */
574#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
575#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
576 /* 0=DTE device */
577#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
578 /* 0=Configure PHY as Slave */
579#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
580 /* 0=Automatic Master/Slave config */
581
582/* 1000BASE-T Status Register */
583#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
584#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
585
586
587/* PHY 1000 MII Register/Bit Definitions */
588/* PHY Registers defined by IEEE */
589#define PHY_CONTROL 0x00 /* Control Register */
590#define PHY_STATUS 0x01 /* Status Register */
591#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
592#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
593#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
594#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
595#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
596#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
597#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
598#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
599
600#define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */
601
602/* NVM Control */
603#define E1000_EECD_SK 0x00000001 /* NVM Clock */
604#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
605#define E1000_EECD_DI 0x00000004 /* NVM Data In */
606#define E1000_EECD_DO 0x00000008 /* NVM Data Out */
607#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
608#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
609#define E1000_EECD_PRES 0x00000100 /* NVM Present */
610#define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */
611/* NVM Addressing bits based on type (0-small, 1-large) */
612#define E1000_EECD_ADDR_BITS 0x00000400
613#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
614#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
615#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
616#define E1000_EECD_SIZE_EX_SHIFT 11
617#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
618#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
619#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
620#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
621
622#define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write registers */
623#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
624#define E1000_NVM_RW_REG_START 1 /* Start operation */
625#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
626#define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
627#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */
628#define E1000_FLASH_UPDATES 2000
629
630/* NVM Word Offsets */
631#define NVM_COMPAT 0x0003
632#define NVM_ID_LED_SETTINGS 0x0004
633#define NVM_INIT_CONTROL2_REG 0x000F
634#define NVM_INIT_CONTROL3_PORT_B 0x0014
635#define NVM_INIT_3GIO_3 0x001A
636#define NVM_INIT_CONTROL3_PORT_A 0x0024
637#define NVM_CFG 0x0012
638#define NVM_ALT_MAC_ADDR_PTR 0x0037
639#define NVM_CHECKSUM_REG 0x003F
640
641#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
642
643#define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */
644#define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */
645
646/* Mask bits for fields in Word 0x0f of the NVM */
647#define NVM_WORD0F_PAUSE_MASK 0x3000
648#define NVM_WORD0F_PAUSE 0x1000
649#define NVM_WORD0F_ASM_DIR 0x2000
650
651/* Mask bits for fields in Word 0x1a of the NVM */
652#define NVM_WORD1A_ASPM_MASK 0x000C
653
654/* Mask bits for fields in Word 0x03 of the EEPROM */
655#define NVM_COMPAT_LOM 0x0800
656
657/* length of string needed to store PBA number */
658#define E1000_PBANUM_LENGTH 11
659
660/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
661#define NVM_SUM 0xBABA
662
663/* PBA (printed board assembly) number words */
664#define NVM_PBA_OFFSET_0 8
665#define NVM_PBA_OFFSET_1 9
666#define NVM_PBA_PTR_GUARD 0xFAFA
667#define NVM_WORD_SIZE_BASE_SHIFT 6
668
669/* NVM Commands - SPI */
670#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
671#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */
672#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
673#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
674#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
675#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
676
677/* SPI NVM Status Register */
678#define NVM_STATUS_RDY_SPI 0x01
679
680/* Word definitions for ID LED Settings */
681#define ID_LED_RESERVED_0000 0x0000
682#define ID_LED_RESERVED_FFFF 0xFFFF
683#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
684 (ID_LED_OFF1_OFF2 << 8) | \
685 (ID_LED_DEF1_DEF2 << 4) | \
686 (ID_LED_DEF1_DEF2))
687#define ID_LED_DEF1_DEF2 0x1
688#define ID_LED_DEF1_ON2 0x2
689#define ID_LED_DEF1_OFF2 0x3
690#define ID_LED_ON1_DEF2 0x4
691#define ID_LED_ON1_ON2 0x5
692#define ID_LED_ON1_OFF2 0x6
693#define ID_LED_OFF1_DEF2 0x7
694#define ID_LED_OFF1_ON2 0x8
695#define ID_LED_OFF1_OFF2 0x9
696
697#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
698#define IGP_ACTIVITY_LED_ENABLE 0x0300
699#define IGP_LED3_MODE 0x07000000
700
701/* PCI/PCI-X/PCI-EX Config space */
702#define PCI_HEADER_TYPE_REGISTER 0x0E
703#define PCIE_LINK_STATUS 0x12
704
705#define PCI_HEADER_TYPE_MULTIFUNC 0x80
706#define PCIE_LINK_WIDTH_MASK 0x3F0
707#define PCIE_LINK_WIDTH_SHIFT 4
708
709#define PHY_REVISION_MASK 0xFFFFFFF0
710#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
711#define MAX_PHY_MULTI_PAGE_REG 0xF
712
713/* Bit definitions for valid PHY IDs. */
714/*
715 * I = Integrated
716 * E = External
717 */
718#define M88E1000_E_PHY_ID 0x01410C50
719#define M88E1000_I_PHY_ID 0x01410C30
720#define M88E1011_I_PHY_ID 0x01410C20
721#define IGP01E1000_I_PHY_ID 0x02A80380
722#define M88E1111_I_PHY_ID 0x01410CC0
723#define GG82563_E_PHY_ID 0x01410CA0
724#define IGP03E1000_E_PHY_ID 0x02A80390
725#define IFE_E_PHY_ID 0x02A80330
726#define IFE_PLUS_E_PHY_ID 0x02A80320
727#define IFE_C_E_PHY_ID 0x02A80310
728#define BME1000_E_PHY_ID 0x01410CB0
729#define BME1000_E_PHY_ID_R2 0x01410CB1
730#define I82577_E_PHY_ID 0x01540050
731#define I82578_E_PHY_ID 0x004DD040
732#define I82579_E_PHY_ID 0x01540090
733
734/* M88E1000 Specific Registers */
735#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
736#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
737#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
738
739#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
740#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
741
742/* M88E1000 PHY Specific Control Register */
743#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
744#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
745 /* Manual MDI configuration */
746#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
747/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
748#define M88E1000_PSCR_AUTO_X_1000T 0x0040
749/* Auto crossover enabled all speeds */
750#define M88E1000_PSCR_AUTO_X_MODE 0x0060
751/*
752 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold)
753 * 0=Normal 10BASE-T Rx Threshold
754 */
755#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
756
757/* M88E1000 PHY Specific Status Register */
758#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
759#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
760#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
761/* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */
762#define M88E1000_PSSR_CABLE_LENGTH 0x0380
763#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
764#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
765
766#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
767
768/*
769 * Number of times we will attempt to autonegotiate before downshifting if we
770 * are the master
771 */
772#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
773#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
774/*
775 * Number of times we will attempt to autonegotiate before downshifting if we
776 * are the slave
777 */
778#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
779#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
780#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
781
782/* M88EC018 Rev 2 specific DownShift settings */
783#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
784#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
785
786#define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020
787#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C
788
789/* BME1000 PHY Specific Control Register */
790#define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */
791
792
793#define PHY_PAGE_SHIFT 5
794#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
795 ((reg) & MAX_PHY_REG_ADDRESS))
796
797/*
798 * Bits...
799 * 15-5: page
800 * 4-0: register offset
801 */
802#define GG82563_PAGE_SHIFT 5
803#define GG82563_REG(page, reg) \
804 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
805#define GG82563_MIN_ALT_REG 30
806
807/* GG82563 Specific Registers */
808#define GG82563_PHY_SPEC_CTRL \
809 GG82563_REG(0, 16) /* PHY Specific Control */
810#define GG82563_PHY_PAGE_SELECT \
811 GG82563_REG(0, 22) /* Page Select */
812#define GG82563_PHY_SPEC_CTRL_2 \
813 GG82563_REG(0, 26) /* PHY Specific Control 2 */
814#define GG82563_PHY_PAGE_SELECT_ALT \
815 GG82563_REG(0, 29) /* Alternate Page Select */
816
817#define GG82563_PHY_MAC_SPEC_CTRL \
818 GG82563_REG(2, 21) /* MAC Specific Control Register */
819
820#define GG82563_PHY_DSP_DISTANCE \
821 GG82563_REG(5, 26) /* DSP Distance */
822
823/* Page 193 - Port Control Registers */
824#define GG82563_PHY_KMRN_MODE_CTRL \
825 GG82563_REG(193, 16) /* Kumeran Mode Control */
826#define GG82563_PHY_PWR_MGMT_CTRL \
827 GG82563_REG(193, 20) /* Power Management Control */
828
829/* Page 194 - KMRN Registers */
830#define GG82563_PHY_INBAND_CTRL \
831 GG82563_REG(194, 18) /* Inband Control */
832
833/* MDI Control */
834#define E1000_MDIC_REG_SHIFT 16
835#define E1000_MDIC_PHY_SHIFT 21
836#define E1000_MDIC_OP_WRITE 0x04000000
837#define E1000_MDIC_OP_READ 0x08000000
838#define E1000_MDIC_READY 0x10000000
839#define E1000_MDIC_ERROR 0x40000000
840
841/* SerDes Control */
842#define E1000_GEN_POLL_TIMEOUT 640
843
844#endif /* _E1000_DEFINES_H_ */